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soc: add npck soc driver

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For npck3m8k:
1. Update code ram from 320KB to 416KB (0x1005_8000~0x100B_FFFF).
2. Update data ram from 32KB to 64KB.
3. Move fiudiv from hfcbcd1 to hfcbcd2 register

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Alvis Sun 2025-04-21 18:24:55 +08:00 • committed by Benjamin Cabé
commit 7e23f8b408
19 changed files with 2532 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

21
include/zephyr/dt-bindings/clock/npcx_clock.h
View file

@ -23,15 +23,16 @@
#define NPCX_CLOCK_BUS_MCLKD 12
/* clock enable/disable references */
#define NPCX_PWDWN_CTL1 0
#define NPCX_PWDWN_CTL2 1
#define NPCX_PWDWN_CTL3 2
#define NPCX_PWDWN_CTL4 3
#define NPCX_PWDWN_CTL5 4
#define NPCX_PWDWN_CTL6 5
#define NPCX_PWDWN_CTL7 6
#define NPCX_PWDWN_CTL8 7
#define NPCX_PWDWN_CTL9 8
#define NPCX_PWDWN_CTL_COUNT 9
#define NPCX_PWDWN_CTL0 0
#define NPCX_PWDWN_CTL1 1
#define NPCX_PWDWN_CTL2 2
#define NPCX_PWDWN_CTL3 3
#define NPCX_PWDWN_CTL4 4
#define NPCX_PWDWN_CTL5 5
#define NPCX_PWDWN_CTL6 6
#define NPCX_PWDWN_CTL7 7
#define NPCX_PWDWN_CTL8 8
#define NPCX_PWDWN_CTL9 9
#define NPCX_PWDWN_CTL_COUNT 10
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_ */

4
soc/nuvoton/npcx/Kconfig
View file

@ -31,6 +31,7 @@ config NPCX_IMAGE_OUTPUT_HEX
config NPCX_HEADER_CHIP
string
default "npck3m8" if SOC_NPCK3M8K
default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
default "npcx7m7" if SOC_NPCX7M7FC
default "npcx9m3" if SOC_NPCX9M3F
@ -136,7 +137,8 @@ config NPCX_HEADER_ENABLE_FIRMWARE_CRC
choice NPCX_HEADER_FLASH_SIZE_CHOICE
prompt "Flash size"
default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
SOC_SERIES_NPCX9
SOC_SERIES_NPCX9 || \
SOC_SERIES_NPCK3
default NPCX_HEADER_FLASH_SIZE_16M
help
This sets the SPI flash size.

2
soc/nuvoton/npcx/common/ecst/ecst.py
View file

@ -214,7 +214,7 @@ def _check_chip(output, ecst_args):
if ecst_args.chip_name == INVALID_INPUT:
message = f'Invalid chip name, '
message += "should be npcx4m3, npcx4m8, npcx9m8, npcx9m7, npcx9m6, " \
"npcx7m7, npcx7m6, npcx7m5."
"npcx7m7, npcx7m6, npcx7m5, npck3m8k."
_exit_with_failure_delete_file(output, message)
def _set_anchor(output, ecst_args):

1
soc/nuvoton/npcx/common/ecst/ecst_args.py
View file

@ -47,6 +47,7 @@ POINTER_OFFSET_DEFAULT = 0x0
# Chips: convert from name to index.
CHIPS_INFO = {
'npck3m8': {'ram_address': 0x10058000, 'ram_size': 0x68000},
'npcx7m5': {'ram_address': 0x100a8000, 'ram_size': 0x20000},
'npcx7m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},

97
soc/nuvoton/npcx/common/npckn/include/clock_def.h Normal file
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@ -0,0 +1,97 @@
/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NUVOTON_NPCX_CLOCK_DEF_H_
#define _NUVOTON_NPCX_CLOCK_DEF_H_
#include <stdbool.h>
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <soc_clock.h>
/* FMUL clock */
#if (OFMCLK > (MAX_OFMCLK / 2))
#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
#else
#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
#endif
/* APBs source clock */
#define APBSRC_CLK OFMCLK
/* AHB6 clock */
#if (CORE_CLK > (MAX_OFMCLK / 2))
#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
#else
#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
#endif
/* FIU clock divider */
#if (CORE_CLK > (MAX_OFMCLK / 2))
#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
#else
#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
#endif
#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
#if (CORE_CLK > (MAX_OFMCLK / 2))
#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
#else
#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
#endif
#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
/* I3C clock divider */
#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
#define MCLKD_SL 2 /* I3C_CLK = (MCLK / 3) */
#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
#define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */
#else
#define MCLKD_SL 0 /* I3C_CLK = MCLK */
#endif
/* Get APB clock freq */
#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
/*
* Frequency multiplier M/N value definitions according to the requested
* OFMCLK (Unit:Hz).
*/
#if (OFMCLK > (MAX_OFMCLK / 2))
#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */
#else
#define HFCGN_VAL 0x02
#endif
#if (OFMCLK == 120000000)
#define HFCGMH_VAL 0x0E
#define HFCGML_VAL 0x4E
#elif (OFMCLK == 100000000)
#define HFCGMH_VAL 0x0B
#define HFCGML_VAL 0xEC
#elif (OFMCLK == 96000000)
#define HFCGMH_VAL 0x0B
#define HFCGML_VAL 0x72
#elif (OFMCLK == 90000000)
#define HFCGMH_VAL 0x0A
#define HFCGML_VAL 0xBA
#elif (OFMCLK == 80000000)
#define HFCGMH_VAL 0x09
#define HFCGML_VAL 0x89
#elif (OFMCLK == 66000000)
#define HFCGMH_VAL 0x07
#define HFCGML_VAL 0xDE
#elif (OFMCLK == 50000000)
#define HFCGMH_VAL 0x0B
#define HFCGML_VAL 0xEC
#elif (OFMCLK == 48000000)
#define HFCGMH_VAL 0x0B
#define HFCGML_VAL 0x72
#else
#error "Unsupported OFMCLK Frequency"
#endif
#endif /* _NUVOTON_NPCX_CLOCK_DEF_H_ */

1958
soc/nuvoton/npcx/common/npckn/include/reg_def.h Normal file
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File diff suppressed because it is too large Load diff

234
soc/nuvoton/npcx/common/npckn/registers.c Normal file
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@ -0,0 +1,234 @@
/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <soc.h>
#include "reg_def.h"
/* CDCG register structure check */
NPCX_REG_SIZE_CHECK(cdcg_reg, 0x116);
NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD, 0x010);
NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD2, 0x014);
NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL, 0x100);
NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL2, 0x114);
/* PMC register structure check */
NPCX_REG_SIZE_CHECK(pmc_reg, 0x013);
NPCX_REG_OFFSET_CHECK(pmc_reg, ENIDL_CTL, 0x003);
NPCX_REG_OFFSET_CHECK(pmc_reg, PWDWN_CTL0, 0x007);
/* SCFG register structure check */
NPCX_REG_SIZE_CHECK(scfg_reg, 0x020);
NPCX_REG_OFFSET_CHECK(scfg_reg, DEV_CTL4, 0x006);
NPCX_REG_OFFSET_CHECK(scfg_reg, DEVALT0, 0x010);
/* GLUE register structure check */
NPCX_REG_SIZE_CHECK(glue_reg, 0x03b);
NPCX_REG_OFFSET_CHECK(glue_reg, SMB_EEN, 0x003);
NPCX_REG_OFFSET_CHECK(glue_reg, SDPD0, 0x010);
NPCX_REG_OFFSET_CHECK(glue_reg, SMB_SEL, 0x021);
NPCX_REG_OFFSET_CHECK(glue_reg, PSL_CTS, 0x027);
NPCX_REG_OFFSET_CHECK(glue_reg, EPURST_CTL, 0x030);
NPCX_REG_OFFSET_CHECK(glue_reg, PSL_CTS3, 0x038);
/* UART register structure check */
NPCX_REG_SIZE_CHECK(uart_reg, 0x027);
NPCX_REG_OFFSET_CHECK(uart_reg, UPSR, 0x00e);
NPCX_REG_OFFSET_CHECK(uart_reg, UFCTRL, 0x016);
NPCX_REG_OFFSET_CHECK(uart_reg, URXFLV, 0x01A);
/* GPIO register structure check */
NPCX_REG_SIZE_CHECK(gpio_reg, 0x008);
NPCX_REG_OFFSET_CHECK(gpio_reg, PTYPE, 0x006);
/* PWM register structure check */
NPCX_REG_SIZE_CHECK(pwm_reg, 0x012);
NPCX_REG_OFFSET_CHECK(pwm_reg, PWMCTL, 0x004);
NPCX_REG_OFFSET_CHECK(pwm_reg, DCR, 0x006);
NPCX_REG_OFFSET_CHECK(pwm_reg, PWMCTLEX, 0x00c);
NPCX_REG_OFFSET_CHECK(pwm_reg, N_STEP_RS, 0x005);
NPCX_REG_OFFSET_CHECK(pwm_reg, N_STEP_FL, 0x00D);
NPCX_REG_OFFSET_CHECK(pwm_reg, EXT_OFF, 0x00F);
/* ADC register structure check */
NPCX_REG_SIZE_CHECK(adc_reg, 0x108);
NPCX_REG_OFFSET_CHECK(adc_reg, THRCTS, 0x01a);
NPCX_REG_OFFSET_CHECK(adc_reg, ADCCNF2, 0x020);
NPCX_REG_OFFSET_CHECK(adc_reg, MEAST, 0x026);
/* TWD register structure check */
NPCX_REG_SIZE_CHECK(twd_reg, 0x012);
NPCX_REG_OFFSET_CHECK(twd_reg, T0CSR, 0x006);
NPCX_REG_OFFSET_CHECK(twd_reg, TWMWD, 0x00e);
NPCX_REG_OFFSET_CHECK(twd_reg, WDCP, 0x010);
/* ESPI register structure check */
NPCX_REG_SIZE_CHECK(espi_reg, 0x900);
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHCFG, 0x034);
NPCX_REG_OFFSET_CHECK(espi_reg, NPCX_ONLY_ESPI_REG1, 0x0f0);
NPCX_REG_OFFSET_CHECK(espi_reg, VWEVMS, 0x140);
NPCX_REG_OFFSET_CHECK(espi_reg, VWGPSM, 0x180);
NPCX_REG_OFFSET_CHECK(espi_reg, VWCTL, 0x2fc);
NPCX_REG_OFFSET_CHECK(espi_reg, OOBTXBUF, 0x380);
NPCX_REG_OFFSET_CHECK(espi_reg, OOBCTL_DIRECT, 0x3fc);
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHTXBUF, 0x480);
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHCTL_DIRECT, 0x4fc);
/* MSWC register structure check */
NPCX_REG_SIZE_CHECK(mswc_reg, 0x030);
NPCX_REG_OFFSET_CHECK(mswc_reg, HCBAL, 0x008);
NPCX_REG_OFFSET_CHECK(mswc_reg, HCBAH, 0x00a);
NPCX_REG_OFFSET_CHECK(mswc_reg, SRID_CR, 0x01c);
NPCX_REG_OFFSET_CHECK(mswc_reg, SID_CR, 0x020);
NPCX_REG_OFFSET_CHECK(mswc_reg, VW_SLPST1, 0x02e);
/* SHM register structure check */
NPCX_REG_SIZE_CHECK(shm_reg, 0x088);
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_WIN_SIZE, 0x005);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_SIZE, 0x007);
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_SEM, 0x00b);
NPCX_REG_OFFSET_CHECK(shm_reg, SHCFG, 0x00e);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN1_WR_PROT, 0x010);
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_WR_PROT, 0x016);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_BASE1, 0x020);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_BASE2, 0x024);
NPCX_REG_OFFSET_CHECK(shm_reg, RST_CFG, 0x03a);
NPCX_REG_OFFSET_CHECK(shm_reg, DP80BUF, 0x040);
NPCX_REG_OFFSET_CHECK(shm_reg, DP80CTL, 0x044);
NPCX_REG_OFFSET_CHECK(shm_reg, HOFS_STS, 0x048);
NPCX_REG_OFFSET_CHECK(shm_reg, COFS1, 0x04c);
#if defined(CONFIG_SOC_SERIES_NPCK3)
NPCX_REG_OFFSET_CHECK(shm_reg, SHM_CTL2, 0x04e);
#endif
/* KBC register structure check */
NPCX_REG_SIZE_CHECK(kbc_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(kbc_reg, HIKMDI, 0x00a);
NPCX_REG_OFFSET_CHECK(kbc_reg, SHIKMDI, 0x00b);
/* PMCH register structure check */
NPCX_REG_SIZE_CHECK(pmch_reg, 0x012);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDO, 0x002);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDOC, 0x006);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDOM, 0x008);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDIC, 0x00a);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMIE, 0x010);
/* C2H register structure check */
NPCX_REG_SIZE_CHECK(c2h_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(c2h_reg, LKSIOHA, 0x004);
NPCX_REG_OFFSET_CHECK(c2h_reg, CRSMAE, 0x008);
NPCX_REG_OFFSET_CHECK(c2h_reg, SIBCTRL, 0x00a);
/* SMB register structure check */
NPCX_REG_SIZE_CHECK(smb_reg, 0x030);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBCTL1, 0x006);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBADDR6, 0x016);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBCST2, 0x018);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBTXF_STS, 0x01a);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBSCLHT, 0x01e);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBRXF_CTL, 0x01e);
NPCX_REG_OFFSET_CHECK(smb_reg, DMA_CTRL, 0x00f);
NPCX_REG_OFFSET_CHECK(smb_reg, DMA_ADDR3, 0x022);
NPCX_REG_OFFSET_CHECK(smb_reg, TIMEOUT_CTL1, 0x029);
/* ITIM register structure check */
NPCX_REG_SIZE_CHECK(itim32_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(itim32_reg, ITPRE32, 0x001);
NPCX_REG_OFFSET_CHECK(itim32_reg, ITCTS32, 0x004);
NPCX_REG_OFFSET_CHECK(itim32_reg, ITCNT32, 0x008);
NPCX_REG_SIZE_CHECK(itim64_reg, 0x010);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITPRE64, 0x001);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCTS64, 0x004);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCNT64L, 0x008);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCNT64H, 0x00c);
/* TACH register structure check */
NPCX_REG_SIZE_CHECK(tach_reg, 0x01e);
NPCX_REG_OFFSET_CHECK(tach_reg, TPRSC, 0x008);
NPCX_REG_OFFSET_CHECK(tach_reg, TECLR, 0x010);
NPCX_REG_OFFSET_CHECK(tach_reg, TCPA, 0x014);
NPCX_REG_OFFSET_CHECK(tach_reg, TCPCFG, 0x018);
NPCX_REG_OFFSET_CHECK(tach_reg, TCFG, 0x01c);
/* PS/2 Interface register structure check */
NPCX_REG_SIZE_CHECK(ps2_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSDAT, 0x000);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSTAT, 0x002);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSCON, 0x004);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSOSIG, 0x006);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSISIG, 0x008);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSIEN, 0x00a);
/* FIU register structure check */
#if defined(CONFIG_SOC_SERIES_NPCX9) || defined(CONFIG_SOC_SERIES_NPCX4)
NPCX_REG_SIZE_CHECK(fiu_reg, 0x040);
#elif defined(CONFIG_SOC_SERIES_NPCK3)
NPCX_REG_SIZE_CHECK(fiu_reg, 0x044);
#else
NPCX_REG_SIZE_CHECK(fiu_reg, 0x034);
#endif
NPCX_REG_OFFSET_CHECK(fiu_reg, BURST_CFG, 0x001);
NPCX_REG_OFFSET_CHECK(fiu_reg, SPI_FL_CFG, 0x014);
NPCX_REG_OFFSET_CHECK(fiu_reg, UMA_CTS, 0x01e);
NPCX_REG_OFFSET_CHECK(fiu_reg, CRCCON, 0x026);
#if defined(CONFIG_SOC_SERIES_NPCK3)
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_RD_CMD_BACK, 0x02E);
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_RD_CMD_PVT, 0x030);
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_RD_CMD_SHD, 0x031);
#else
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_RD_CMD, 0x030);
#endif
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_EXT_CFG, 0x033);
/* PECI register structure check */
NPCX_REG_SIZE_CHECK(peci_reg, 0x050);
NPCX_REG_OFFSET_CHECK(peci_reg, PECI_ADDR, 0x002);
NPCX_REG_OFFSET_CHECK(peci_reg, PECI_WR_LENGTH, 0x007);
NPCX_REG_OFFSET_CHECK(peci_reg, PECI_WR_FCS, 0x00b);
/* KBS register structure check */
NPCX_REG_SIZE_CHECK(kbs_reg, 0x010);
NPCX_REG_OFFSET_CHECK(kbs_reg, KBSIN, 0x004);
NPCX_REG_OFFSET_CHECK(kbs_reg, KBSOUT0, 0x006);
NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a);
/* SWRST register structure check */
NPCX_REG_SIZE_CHECK(swrst_reg, 0x014);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_TRG, 0x000);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[0], 0x004);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[1], 0x008);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[2], 0x00c);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[3], 0x010);
/* MBI register structure check */
NPCX_REG_SIZE_CHECK(mbi_reg, 0x076);
NPCX_REG_OFFSET_CHECK(mbi_reg, GPD, 0x010);
NPCX_REG_OFFSET_CHECK(mbi_reg, DINMR, 0x050);
NPCX_REG_OFFSET_CHECK(mbi_reg, MBIHWP, 0x060);
NPCX_REG_OFFSET_CHECK(mbi_reg, MBICCON, 0x070);
/* LCT register structure check */
NPCX_REG_OFFSET_CHECK(lct_reg, LCTCONT, 0x002);
NPCX_REG_OFFSET_CHECK(lct_reg, LCTHOUR, 0x008);
NPCX_REG_OFFSET_CHECK(lct_reg, LCTWEEK, 0x00c);
#if DT_HAS_COMPAT_STATUS_OKAY(nuvoton_npcx_lct_v2)
NPCX_REG_OFFSET_CHECK(lct_reg, LCTWEEKM, 0x00d);
NPCX_REG_SIZE_CHECK(lct_reg, 0x00e);
#else
NPCX_REG_SIZE_CHECK(lct_reg, 0x00d);
#endif
/* GDMA register structure check */
NPCX_REG_SIZE_CHECK(gdma_reg, 0x020);
NPCX_REG_OFFSET_CHECK(gdma_reg, CONTROL, 0x000);
NPCX_REG_OFFSET_CHECK(gdma_reg, SRCB, 0x004);
NPCX_REG_OFFSET_CHECK(gdma_reg, DSTB, 0x008);
NPCX_REG_OFFSET_CHECK(gdma_reg, TCNT, 0x00C);

16
soc/nuvoton/npcx/common/npcxn/include/clock_def.h
View file

@ -94,20 +94,4 @@
#error "Unsupported OFMCLK Frequency"
#endif
/* Clock prescaler configurations in different series */
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
#if defined(FIU1DIV_VAL)
#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
#else
#define VAL_HFCBCD (FIUDIV_VAL << 4)
#endif /* FIU1DIV_VAL */
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
#if defined(APB4DIV_VAL)
#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
#else
#define VAL_HFCBCD2 APB3DIV_VAL
#endif /* APB4DIV_VAL */
/* I3C1~I3C3 share the same configuration */
#define VAL_HFCBCD3 MCLKD_SL
#endif /* _NUVOTON_NPCX_CLOCK_DEF_H_ */

13
soc/nuvoton/npcx/common/npcxn/include/reg_def.h
View file

@ -93,18 +93,9 @@ struct pmc_reg {
volatile uint8_t PWDWN_CTL7[1];
};
/* PMC internal inline functions for multi-registers */
static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
{
if (ctl_no < 6) {
return 0x008 + ctl_no;
} else {
return 0x024 + ctl_no - 6;
}
}
/* Macro functions for PMC multi-registers */
#define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + npcx_pwdwn_ctl_offset(n)))
#define NPCX_PWDWN_CTL(base, n) \
(*(volatile uint8_t *)(base + NPCX_PWDWN_CTL_OFFSET(n)))
/* PMC register fields */
#define NPCX_PMCSR_DI_INSTW 0

12
soc/nuvoton/npcx/npck3/CMakeLists.txt Normal file
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@ -0,0 +1,12 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(
.
${ZEPHYR_BASE}/drivers
)
zephyr_sources(
soc.c
)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

30
soc/nuvoton/npcx/npck3/Kconfig Normal file
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@ -0,0 +1,30 @@
# Nuvoton NPCK3 EC series
# Copyright (c) 2025 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NPCK3
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_PM
select HAS_SWO
if SOC_SERIES_NPCK3
config SOC_NPCK_EPURST_DISABLE
bool "Disable all External Power-Up Reset Inputs"
default y
help
Disable all External Power-Up Reset Inputs during initialization. All
signals such as EXT_PURST# are disabled by default. The users can
enable it if needed.
config SOC_NPCK_DEBUG_DISABLE
bool "Disable all K3 debug interfaces"
help
Disable all K3 debug interface during initialization.
endif # SOC_SERIES_NPCK3

18
soc/nuvoton/npcx/npck3/Kconfig.defconfig Normal file
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@ -0,0 +1,18 @@
# Nuvoton Cortex-M4 Embedded Controller
# Copyright (c) 2025 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_NPCK3
config NUM_IRQS
default 64
config CORTEX_M_SYSTICK
default !NPCX_ITIM_TIMER
config ESPI_TAF_NPCX
default y
depends on ESPI_TAF
endif # SOC_SERIES_NPCK3

22
soc/nuvoton/npcx/npck3/Kconfig.soc Normal file
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@ -0,0 +1,22 @@
# Nuvoton NPCK3 EC series
# Copyright (c) 2025 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NPCK3
bool
select NPCX_SOC_VARIANT_NPCKN
help
Enable support for Nuvoton NPCK3 series
config SOC_NPCK3M8K
bool
select SOC_SERIES_NPCK3
help
NPCK3M8K
config SOC_SERIES
default "npck3" if SOC_SERIES_NPCK3
config SOC
default "npck3m8k" if SOC_NPCK3M8K

32
soc/nuvoton/npcx/npck3/soc.c Normal file
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@ -0,0 +1,32 @@
/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
void soc_early_init_hook(void)
{
struct glue_reg *inst_glue = (struct glue_reg *)
DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), glue);
struct scfg_reg *inst_scfg = (struct scfg_reg *)
DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg);
if (IS_ENABLED(CONFIG_SOC_NPCK_EPURST_DISABLE)) {
/* EXT_PURST# signal is not selected to the pin by default */
inst_glue->EPURST_CTL &= ~BIT(NPCX_EPURST_CTL_EPUR2_EN);
}
if (IS_ENABLED(CONFIG_SOC_NPCK_DEBUG_DISABLE)) {
/* Core debugging interface is disabled */
inst_scfg->DEVCNT |= BIT(1);
}
}

80
soc/nuvoton/npcx/npck3/soc.h Normal file
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@ -0,0 +1,80 @@
/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NUVOTON_NPCX_SOC_H_
#define _NUVOTON_NPCX_SOC_H_
#include <cmsis_core_m_defaults.h>
/* NPCK3 SCFG multi-registers */
#define NPCX_DEVALT_OFFSET(n) ((n < 0x10) ? (0x010 + n) : \
((n < 0x13) ? (0x0b + (n - 0x10)) : \
(0x024 + (n - 0x13))))
#define NPCX_PUPD_EN_OFFSET(n) (0x028 + n)
#define NPCX_LV_GPIO_CTL_OFFSET(n) (0x02a + n)
#define NPCX_DEVALT_LK_OFFSET(n) (0)
/* NPCK3 MIWU multi-registers */
#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 2) + ((n < 5) ? 0 : 0x01e))
#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 2) + ((n < 5) ? 0 : 0x01e))
#define NPCX_WKMOD_OFFSET(n) (0x070 + n)
#define NPCX_WKPND_OFFSET(n) (0x00a + (n * 4) + ((n < 5) ? 0 : 0x010))
#define NPCX_WKPCL_OFFSET(n) (0x00c + (n * 4) + ((n < 5) ? 0 : 0x010))
#define NPCX_WKEN_OFFSET(n) (0x01e + (n * 2) + ((n < 5) ? 0 : 0x012))
#define NPCX_WKINEN_OFFSET(n) (0x01f + (n * 2) + ((n < 5) ? 0 : 0x012))
/* NPCK3 PMC multi-registers */
#define NPCX_PWDWN_CTL_OFFSET(n) (0x007 + n)
/* NPCK3 ADC multi-registers */
#define NPCX_CHNDAT_OFFSET(n) (0x040 + n * 2)
#define NPCX_THRCTL_OFFSET(n) (0x014 + n * 2)
#define NPCX_TCHNDAT_OFFSET(n) (0x10E + n * 2)
#define NPCX_TEMP_THRCTL_OFFSET(n) (0x180 + n * 2)
#define NPCX_TEMP_THR_DCTL_OFFSET(n) (0x1A0 + n * 2)
/* NPCK3 ADC register fields */
#define NPCX_THRCTL_THEN 15
#define NPCX_THRCTL_L_H 14
#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
#define NPCX_THRCTL_THRVAL FIELD(0, 10)
/* NPCK3 FIU register fields */
#define NPCK_FIFO_EN 0
#define NPCK_RX_FIFO_LEVEL FIELD(6, 2)
#define NPCK_SZ_UART_FIFO 16
#define NPCX_FIU_EXT_CFG_SPI1_2DEV 0
/* NPCK3 GLUE register fields */
#define NPCX_EPURST_CTL_EPUR1_AHI 0
#define NPCX_EPURST_CTL_EPUR1_EN 1
#define NPCX_EPURST_CTL_EPUR2_AHI 2
#define NPCX_EPURST_CTL_EPUR2_EN 3
#define NPCX_EPURST_CTL_EPUR_LK 7
/* NPCK3 TWD register fields */
#define NPCX_T0CSR_T0EN 6
/* No DEVALT_LK mechanism in NPCK3 series */
#define NPCX_DEVALT_LK_GROUP_MASK 0x00000000
/* NPCK3 Clock configuration and limitation */
#define MAX_OFMCLK 100000000
#include "reg_def.h"
#include "clock_def.h"
#include <soc_dt.h>
#include <soc_espi_taf.h>
#include <soc_pins.h>
#include <soc_power.h>
/* NPCK3 Clock prescaler configurations */
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
#define VAL_HFCBCD (APB1DIV_VAL | (APB2DIV_VAL << 4))
#define VAL_HFCBCD1 0 /* Keep the same as reset value 0*/
#define VAL_HFCBCD2 (APB3DIV_VAL | (FIUDIV_VAL << 4))
#endif /* _NUVOTON_NPCX_SOC_H_ */

10
soc/nuvoton/npcx/npcx4/soc.h
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@ -25,6 +25,9 @@
#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
/* NPCX4 PMC multi-registers */
#define NPCX_PWDWN_CTL_OFFSET(n) (((n - 1) < 6) ? (0x008 + (n - 1)) : (0x01e + (n - 1)))
/* NPCX4 ADC multi-registers */
#define NPCX_CHNDAT_OFFSET(n) (0x040 + n * 2)
#define NPCX_THRCTL_OFFSET(n) (0x080 + n * 2)
@ -57,4 +60,11 @@
#include <soc_pins.h>
#include <soc_power.h>
/* NPCX4 Clock prescaler configurations */
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
#define VAL_HFCBCD3 MCLKD_SL /* Used by I3C1/2/3 modules */
#endif /* _NUVOTON_NPCX_SOC_H_ */

9
soc/nuvoton/npcx/npcx7/soc.h
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@ -24,6 +24,9 @@
#define NPCX_WKEN_OFFSET(n) (0x01e + (n * 2) + ((n < 5) ? 0 : 0x012))
#define NPCX_WKINEN_OFFSET(n) (0x01f + (n * 2) + ((n < 5) ? 0 : 0x012))
/* NPCX7 PMC multi-registers */
#define NPCX_PWDWN_CTL_OFFSET(n) (((n - 1) < 6) ? (0x008 + (n - 1)) : (0x01e + (n - 1)))
/* NPCX7 ADC multi-registers offset */
#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
#define NPCX_THRCTL_OFFSET(n) (0x014 + (n * 2))
@ -48,4 +51,10 @@
#include <soc_pins.h>
#include <soc_power.h>
/* NPCX7 Clock prescaler configurations */
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
#define VAL_HFCBCD (FIUDIV_VAL << 4)
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
#define VAL_HFCBCD2 APB3DIV_VAL
#endif /* _NUVOTON_NPCX_SOC_H_ */

9
soc/nuvoton/npcx/npcx9/soc.h
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@ -25,6 +25,9 @@
#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
/* NPCX9 PMC multi-registers */
#define NPCX_PWDWN_CTL_OFFSET(n) (((n - 1) < 6) ? (0x008 + (n - 1)) : (0x01e + (n - 1)))
/* NPCX9 ADC multi-registers */
#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
#define NPCX_THRCTL_OFFSET(n) (0x060 + (n * 2))
@ -53,4 +56,10 @@
#include <soc_pins.h>
#include <soc_power.h>
/* NPCX9 Clock prescaler configurations */
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
#define VAL_HFCBCD (FIUDIV_VAL << 4)
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
#endif /* _NUVOTON_NPCX_SOC_H_ */

3
soc/nuvoton/npcx/soc.yml
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@ -1,6 +1,9 @@
family:
- name: npcx
series:
- name: npck3
socs:
- name: npck3m8k
- name: npcx4
socs:
- name: npcx4m3f