Commit graph

1403 commits

Author SHA1 Message Date
Kiril Zyapkov
23cb7dd660 soc: st: add STM32L471xG
This commit adds support for STM32L471xG. Since STM32L475 only adds
USB, stm32l475.dtsi now includes stm32l471.dtsi

Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
2018-11-20 14:09:04 -06:00
Aurelien Jarno
6194b7676c drivers: flash: add flash driver support for Atmel SAM E70
This patch adds a flash driver for the Atmel SAM E70 SoC. The driver has
been kept simple by considering that the flash is only composed of 8-KiB
blocks. Indeed an area at the beginning of the flash might be erased
with a smaller granularity, and the other blocks can also be erased with
a higher granularity. It also only handles the global read/write
protection, not the 128-KiB lock regions. A write error is returned if
a region is locked.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-11-20 14:11:07 -05:00
Andrei Gansari
a5174be648 mimxrt1050_evk: enabling networking hardware
Enables Networking hardware on i.MX-RT 1050-EVKB board.
Pinout enabled board specific etherenet connection, also pin
initialization was moved later to PRE_KERNEL_2 in order to have
sysclock initialized before.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-20 09:54:25 -06:00
Henrik Brix Andersen
e5460c6bcc drivers: watchdog: wdt_sam0: Convert Atmel SAM0 driver to the new API
Convert the Atmel SAM0 watchdog driver to the new watchdog API and
enable DTS support.

This fixes #10914.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2018-11-19 08:40:15 -06:00
Stanislav Poboril
871fc0f3c2 imx: Add Messaging Unit peripheral support for i.MX6SoloX soc
Add Messaging Unit B peripheral support for i.MX6SoloX soc so it can
use IMX IPM.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-11-19 08:38:38 -06:00
Michael Scott
7f6fcf2198 dts-binding: modem: wnc-14a2a: remove base_label to fix build errors
When the WNC-14A2A modem binding was originally introduced, I thought
the base_label would shorten the define keeping the result short and
easily portable.  Turns out with the latest changes, it has a side
effect of removing the "DT_*" prefix which is breaking the build.

Let's remove "base_label" from the modem binding and adjust all of
the dts_fixups referring to the WNC14A2A defines.

NOTE: This commit moves the left-over WNC14A2A dts_fixup defines from
the nRF52 soc into samples/net/lwm2m_client as the new values.
They will stay there until the modem can be re-configured as a shield.

Signed-off-by: Michael Scott <mike@foundries.io>
2018-11-17 00:50:15 -05:00
Andrei Gansari
db7d1da896 dts: added nxp.kinetis-ptp interrupts
Kinetis device K64F's PTP interrupt crashed the system becase it was not
generated from dts. Device interrupt correctly set now.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-17 00:44:28 +01:00
Kumar Gala
1634cf2248 drivers/spi: Always selecet HAS_DTS_SPI once SPI is enabled
All drivers require DTS for their primary SPI settings.

Removing SPI_[0-9]_NAME config option added some more samples changes.
Usage of these options there was anyway not relevant.

Fixes #11064

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-16 14:02:00 -05:00
Kumar Gala
ea198e3e4b ieee802154: mcr20a: Cleanup Kconfig and DT support
Now that all SPI controllers support DTS we can remove the Kconfig
support for non-DTS options.  We also cleanup some defines that should
have be DT_MCR20A_ instead of CONFIG_MCR20A_.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-16 14:02:00 -05:00
Kumar Gala
fd6e9c6f58 dts: i2c: cleanup CONFIG_I2C_x_IRQ_PRI
The majority of cases of CONFIG_I2C_x_IRQ_PRI should be
DT_I2C_x_IRQ_PRI.  So go ahead and fix them up.  Only the i2c_nios
driver still uses Kconfig for getting priority.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-16 13:57:02 -05:00
Kumar Gala
ee9b08d7da drivers: watchdog: Convert Atmel SAM driver to DTS
The majority of bits where already in place, but some minor support
get the driver name from DTS was needed.  Now we select HAS_DTS_WDT
for the driver.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-16 11:19:36 -06:00
Andrew Boie
42cfd4ff26 kernel: expose k_busy_wait() to user mode
If we just had the kernel's implementation, we could
just move this to lib/, but possible arch-specific
implementations dictate that we just make this a
syscall.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-15 16:20:36 -05:00
Kumar Gala
71c3dd11c5 spi: sam: Specify pinmux for chipselect via Kconfig
Move to using Kconfig (like other Atmel SAM drivers do) to specify the
pinmux setting for SAMe70 SoCs.  Updated the sam_e70_xplained board to
set the default in Kconfig.defconfig instead of via board.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-15 07:29:44 -06:00
Rajavardhan Gundi
f75b5f6c55 intel_s1000: DTS: fix dts_fixup.h with new DT_ prefix for SPI driver
This fixes the SPI driver references in dts_fixup.h with DT_ prefixes.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-11-15 07:43:38 -05:00
Andy Ross
953a81a194 esp32: Enable an early-boot printk hook
The firmware starts us with an already-initialized UART and a simple
ROM hook.  Use that as the default printk handler so we can log in
very early boot.  It will be overriden later (as it happens, by
another handler based on the same firmware hooks).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-14 19:08:27 -05:00
Anas Nashif
14ba292870 xtensa: fix dts_fixup.h with new DT_ prefix
This fixes majority of drivers, however we still see build failures with
the interrupt handler.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-11-14 12:59:12 -05:00
Aurelien Jarno
16994088fd drivers: entropy: add Atmel SAM entropy generator driver
Tested on the Atmel SAM E70 Xplained board.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-11-14 12:58:49 -05:00
Savinay Dharmappa
cf58f83dd6 boards: xtensa: intel_s1000_crb: Enable SPI Master driver
patch enables SPI Master driver on intel_s1000_crb

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-11-13 18:49:03 -05:00
Kumar Gala
128fef2c09 dts: Fix builds of arc EMSK & NSIM SoCs
With the DT_ prefix change we missed adding prefixes in dts_fixup.h
on snps_emsk & snps_nsim for ARC_ICCM_0_BASE_ADDRESS and
ARC_ICCM_0_SIZE.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-13 18:47:16 -05:00
Ulf Magnusson
4638652214 Kconfig: Use 'default' instead of 'def_bool' in Kconfig.defconfig files
This can help find unused symbols. Those end up without a type if
'default' is used instead of 'def_bool', which generates a warning.

Search for "Kconfig.defconfig" in
https://docs.zephyrproject.org/latest/application/kconfig-tips.html for
a longer explanation.

Keep the 'def_bool' for the following symbols, which seem to be
deliberately defined only in Kconfig.defconfig files:

 - ALTERA_AVALON_I2C
 - ALTERA_AVALON_MSGDMA
 - ALTERA_AVALON_PIO
 - ALTERA_AVALON_QSPI
 - ALTERA_AVALON_SYSID
 - CLOCK_CONTROL_IMX_CCM
 - CPU_EM4_DMIPS
 - CPU_EM4_FPUDA
 - CPU_EM4_FPUS
 - FP_FPU_DA
 - I2C_GECKO

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2018-11-13 16:04:01 -05:00
Andrzej Głąbek
20202902f2 dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig
These changes were obtained by running a script  created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:

1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
   #define X Y)
3. Check if that name is also the name of a Kconfig option
   3.a If it is, then do nothing
   3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
       has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
   (.c, .h, .ld)

Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.

Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 10:44:42 -06:00
Andrzej Głąbek
d4a17b4085 soc: cc2650: Update DTS-derived labels with DT_ prefix
Update a couple of labels generated from DTS used directly (not through
dts_fixups) in TI CC2650 system initialization code and a few drivers
for this SoC.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 10:44:42 -06:00
Andrzej Głąbek
f39ba7230d dts_fixups: Update labels generated from DTS with DT_ prefix
All labels containing "_<8-hex-digits>_" or "16550_<3or6-hex-digits>_"
in their names, assumed to be generated by the extracting script,
are updated with the DT_ prefix, to reflect the recent changes made
to the script.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 10:44:42 -06:00
Aurelien Jarno
1b1f832197 arch: arm: stm32f7: Kconfig: select CPU_HAS_ARM_MPU
Now that Cortex-M7 cache issues have been fixed in commits 828ae6b8 and
13972693, it is possible to safely enable the MPU on the STM32F7 SoC
series.

Note that the ITCM area is not mapped into an MPU region. This should
not be an issue for now, as Zephyr does not provide yet a way to
populate and use this area.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-11-13 08:58:29 -05:00
Endre Karlson
bfb45055f1 soc: silabs: Enable Segger RTT
This change allows you to use RTT with EFR32 chips.

Signed-off-by: Endre Karlson <endre.karslon@gmail.com>
2018-11-13 10:53:47 +01:00
Pavel Kral
86a4967365 dts: stm32f103: add missing dts binding for port G
STM32F103 micros starting from 64-pin (xE) packages upward have
available port G. This patch defines a dts binding for them.

Signed-off-by: Pavel Kral <pavel.kral@omsquare.com>
2018-11-12 08:26:49 -05:00
Erwan Gouriou
0d81496fc5 soc/st/stm32f7: Fix typo in stm32f7 fixup file
Fix address field STM32 USART8 NAME macro

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-11-12 08:17:28 -05:00
Erwan Gouriou
d76a5592e4 drivers/serial: stm32: Get clocks information from device tree
Provide CONFIG macros for clocks bits and bus properties in fixup
files and use them to simplify logic in uart devices instanciation
code

Fixes #10448

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-11-12 08:17:28 -05:00
Andrew Boie
506f15c381 interrupts: simplify position of sw ISR table
We now place the linker directives for the SW ISR table
in the common linker scripts, instead of repeating it
everywhere.

The table will be placed in RAM if dynamic interrupts are
enabled.

A dedicated section is used, as this data must not move
in between build phases.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Tomasz Bursztyka
8c3a1cb23a soc: Remove useless Kconfig options and config for Galileo and SPI
These are set via DTS now.

Fixes #11064

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-11-09 05:25:11 -06:00
Tomasz Bursztyka
11d13d94eb dts: Add the dts entries for Intel SPI on Galileo
With approriate fixups.

Fixes #11064

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2018-11-09 05:25:11 -06:00
Martin Bertsche
9892f40204 gpio: stm32 use dts extracted information to populate gpio instances.
The information extracted from the device tree is now used to initialize
GPIO device instances. Up until now the GPIO device driver made no use
of this information. Actual instance creation is still controlled using
the Kconfig method. Missing GPIO device tree nodes were added in the
process for STM32L073, STM32F413 and STM32F373.

The information for gpio instance initialization has already been
present for supported STM32 SoCs but remained unused. Changes in the
device tree had no effect on GPIO functionality and was essentially
redundant. Using the device tree for hardware description seems
plausible and less painful than a myriad of defines in some SoC
description header.

The change was implemented under the assumption that current device
trees provide a correct description of the SoCs. Base register addresses
and RCC register bits were not explicitly checked for each device.

Manual tests were executed on:
	- NUCLEO-F103RB
	- STM32F429I-DISCO
	- STM32F746G-DISCO
	- NUCLEO-F767ZI

Manual tests consisted of blinky on different GPIOs and pins on each
board.

sanitycheck was executed for all STM32 based boards

Fixes: #10629

Signed-off-by: Martin Bertsche <martin72216@googlemail.com>
2018-11-09 04:49:59 -06:00
Piotr Mienkowski
d9e2171aa9 drivers: flash_gecko: Add flash driver for SiLabs Gecko SoCs
Tested with SLWSTK6061A / BRD4250B wireless starter kit.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2018-11-08 17:56:44 -05:00
Sathish Kuttan
3d19f891a3 soc: intel_s1000: GNA model - linker script entry
Add a linker script entry for embedding a GNA model at a
4KB page aligned address in .data section

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-08 17:08:19 -05:00
Benoit Leforestier
270ec15482 board: Add support of STM32F143xG SOC
The only difference between the F413xH and F413xG is flash memory size.
STMF413xH: 1536 Kbytes
STMF413xG: 1024 Kbytes

Signed-off-by: Benoit Leforestier <benoit.leforestier@gmail.com>
2018-11-08 07:05:04 -06:00
Sathish Kuttan
c91faf9008 drivers: dmic: Intel PDM digital mic driver
Added an implementation of driver for Intel PDM digital microphone
controller .

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-08 00:40:28 -05:00
Martin Benda
4a2837f866 arch: arm: sam0: enable SEGGER RTT on Atmel sam0 SoCs
Add `select HAS_SEGGER_RTT` under `SOC_FAMILY_SAM0`.

Signed-off-by: Martin Benda <martin.benda@omsquare.com>
2018-11-07 06:42:02 -06:00
Aurelien Jarno
6b6e54321a drivers: usb: add usb device driver for Atmel SAM E70 family
This patch adds a USB device driver for the USBHS device that can be
found on Atmel SAM E70 SoC family. Only the FIFO mode is supported
(as opposed to DMA). It supports LS, FS and HS modes, but defaults to
FS mode as Zephyr does not fully support HS mode yet.

Tested examples on an Atmel SMART SAM E70 Xplained Board:
* usb/cdc_acm
* usb/hid-mouse
* usb/mass

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-11-06 16:32:35 -05:00
Erwan Gouriou
9df3a1f67f drivers/i2c: stm32: get clock bits/bus from dts files
Get STM32 I2C clocks bus and bits information from
device tree files.

Fixes #10435

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-11-06 16:14:13 -05:00
Kumar Gala
bfc4281cc0 arm: kinetis: Add basic DTS support for TRNG
Add dts binding and info for TRNG device and enable basic support to
get the device name from DTS.  We leave for now the base addresses
coming from the MCUX HAL.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-06 08:49:50 -06:00
Kumar Gala
727a9a7f99 arm: kinetis: Add basic DTS support for RNGA
Add dts binding and info for RNGA device and enable basic support to
get the device name from DTS.  We leave for now the base addresses
coming from the MCUX HAL.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-06 08:49:50 -06:00
Kumar Gala
ac7da0b65c gpio: ti cc32xx: Add device tree support for GPIO
Convert gpio_cc32xx driver over to using device tree. Added binding
files, updates to dts for various SoCs that use cc32xx.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-05 11:08:35 -06:00
Anas Nashif
c2c6a6a245 qemu_riscv32: use hifive1 configuration
Use hifive1 configuration for this qemu and set
SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000

Fixes #10043

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-11-05 11:00:38 -05:00
Kumar Gala
ddc2a3d9df drivers: spi_sam0: move sercom pad info to dts
Move the setting of the SERCOM PAD for dipo/dopo for the spi driver
into device tree out of board.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-05 10:05:47 -05:00
Kumar Gala
6d08958ad5 drivers: uart_sam0: move sercom pad info to dts
Move the setting of the SERCOM PAD for rxpo/txpo for the uart driver
into device tree out of board.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-05 10:05:47 -05:00
Sebastian Bøe
3215dd862f cmake: nrf51: Don't #define NRF51822
The define NRF51822 has no in-tree users and is believed to have been
added by accident. The define NRF51 should be referenced in it's
place.

To avoid users accidentally referencing NRF51822 instead of NRF51, and
to avoid confusing users into believing that NRF51822 has semantics we
remove it.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-11-04 22:03:01 +01:00
Sebastian Bøe
c4266a8cd2 cmake: Move MDK-defines from 'soc' to the MDK build script
The build script ext/hal/nordic/CMakeLists.txt manages the MDK
dependency. The MDK is not aware of Zephyr and uses it's own defines
to indicate what HW we are building for.

This commit moves these MDK-specific defines out of the 'soc' build
scripts and into the MDK build script where they belong.

This is expected to be a pure refactoring without side-effects.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-11-04 22:03:01 +01:00
Savinay Dharmappa
79a790829f soc: xtensa: intel_s1000: fix fatal exception.
disable XTENSA_ASM2 Config to fix fatal exection
on intel_s1000.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-11-03 22:39:15 -04:00
Kumar Gala
751b02a49c drivers: serial: uart_miv: Convert to use DTS
Update the uart_miv driver to get params like name, addr, baud-rate,
clock freq from DTS generated defines.  Fixup related board and soc code
as needed.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-03 06:58:23 -04:00
Kumar Gala
11cb8778c7 riscv: Add min dts support for miv SoC & m2gl025_miv board
Add minimal DTS support for the m2gl025_miv.  The dts just has the core,
SoC, PLIC, and UART described.  We still get memory related info from
Kconfig.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-03 06:58:23 -04:00
Daniel Leung
a87a6d82ac soc: apollo_lake: fix build errors for GPIO due to DTS changes
The DTS changes introduced in 7ae220c845
changes the naming of GPIO related macros. This updates the usage
of previous macros via DTS fixup.

Fixes #10993

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-11-02 21:58:02 -04:00
David B. Kinder
ee47f7fb7a doc: fix kconfig misspellings
Fix misspellings in Kconfig files that show up in the configuration
documentation (and make menuconfig screens).

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-11-02 17:58:16 -04:00
Subramanian Meenakshi Sundaram
4e1179bba5 drivers: watchdog: Adding watchdog support for sam SOC
Adding watchdog driver for sam SoC. The current implemntation just
diables the watchdog on device boot.
This PR adds the following support for SAM3X, SAM4S and SAME70
1. Activate processor reset
2. Activate all reset
3. Generate interrupt on watchdog timer expiration.

Signed-off-by: Subramanian Meenakshi Sundaram <subbu147@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-02 15:09:22 -05:00
Daniel Leung
2ce9d81a88 cmake: xcc: fix compile warnings and errors
XCC does not support the "-undef" flag so set NOSYSDEF_CFLAGS to
empty string to fix compile warning.

Also, XCC does not supply the macro __SIZEOF_LONG__ which breaks
the build. So define it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-11-01 16:30:02 -04:00
Kumar Gala
10976dda23 soc: Remove board.h include
The soc code doesn't need anything from board.h so lets remove the
include.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-11-01 13:15:18 +01:00
Jamie McCrae
183e7445c6 soc: nordic: Add Nordic GPREGRET setting support
Adds support for setting GPREGRET register when rebooting.

Signed-off-by: Jamie McCrae <jamie.mccrae@lairdtech.com>
2018-10-29 21:43:23 +00:00
Alberto Escolar Piedras
025c106061 posix arch: Improve description of posix_halt_cpu
Improved the description of posix_halt_cpu().

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
2018-10-27 21:35:51 -04:00
Leandro Pereira
d3528cf001 soc: esp32: Update auto-generated _soc_inthandlers.h
Remove the auto-generated `handle_irq` label for the unneeded cases
to get rid of a compile warning.

Fixes #10801.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-27 21:25:57 -04:00
qianfan Zhao
7ac2ade110 arch: sam: Enable SEGGER RTT on all sam0 and same70 SoCs
All chip from Atmel's sam series can support SEGGER RTT.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-10-27 07:54:28 +01:00
Sebastian Bøe
b9c125f64c kconfig: Hide the DesignWare I2C driver on unsupported platforms
When users are configuring nRF applications they are given the option
to enable the DesignWare I2C driver. But they should not be given this
option because nRF SoCs do not have DesignWare I2C HW.

This commit hides the driver by default by introducing the config
option HAS_I2C_DW.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-10-25 07:32:05 +01:00
Ioannis Glaropoulos
1cc66cf800 arch: high-level Kconfig symbol structure for Trusted Execution
This commit contributes a Kconfig symbol hierarchy which allows
the user to build Zephyr Secure and Non-Secure images on ARMv8-M
MCUs with support for Trusted Execution. However, the high-level
configuration structure is generic, thus, can be potentially
used for any platform that supports Trusted Execution.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-10-24 16:38:33 +01:00
Christian Taedcke
743938b450 dts/arm/st_stm32: Add SPI nodes to STM32 F7 series
This patch adds SPI nodes to STM32 F7 series, as well as the
corresponding dts fixup entries.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-10-23 09:19:15 +01:00
Christian Taedcke
5575594ce9 drivers: spi_ll_stm32: Enable SPI driver for F7 family
Enables SPI driver for STM32F7 SoCs

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-10-23 09:19:15 +01:00
Christian Taedcke
2e06fd50fd drivers/rtc: Enable RTC driver for STM32F7 series
Enable RTC driver for STM32F7 series.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-10-23 09:19:15 +01:00
Leandro Pereira
7cea94942c soc: esp32: Use the smaller interrupt handling routines
Re-generate the ISR for ESP32, after modifying xtensa_intgen.py to
generate shorter code.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2018-10-22 13:38:29 -07:00
Daniel Leung
c229126f55 xtensa: intel_s1000: turn on XTENSA_ASM2
This adds the necessary bits to support ASM2 with XCC
for Intel S1000 SoC. With ASM2 enabled, xcc is now
required to build for Intel S1000 SoC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 17:52:45 -04:00
qianfan Zhao
da0ce2e542 soc: same70: Auto select SAME70 SoC drivers based Kconfig
Auto select drivers on Kconfig.defconfig.series based on Kconfig

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-10-19 16:19:16 -04:00
Daniel Leung
6600c64331 linker: warn about orphan sections
(Previous patch set was reverted due to issue with priv_stack.
 Resubmitting after fixing the faults caused by priv_stack.noinit
 not at the end of RAM.)

This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.

Relates to #5534.

Fixes #10473, #10474, #10515.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 16:11:34 -04:00
Daniel Leung
20e2e5bad8 arm: cypress/psoc6: add SoC specific linker input sections
The Cypress PSoC6 specifies some input sections in the startup
scripts. These sections (.heap, .stack, etc.) need to be placed
at correct location.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 16:11:34 -04:00
Daniel Leung
1134e59bd2 linker: allow SoC to insert linker script fragments
This allows the SoC to specify some additional linker script
fragments into the bss, data and read-only data sections.

For example, the Cypress PSOC6 has a few input sections that
must be put into bss and data sections. Without specifying
these in the linker script, they are consider orphan sections
and the placement is based on linker heuristic which is
arbitrary.

POSIX is not supported as the main linker script is
provided by the host system's binutils and we have no control
over it. Also, currently Xtensa SoCs have their own linker
scripts so there is no need to this feature.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 16:11:34 -04:00
Diego Sueiro
537798db0d soc: arm: exx32: Add Silabs EFR32MG12P soc files
The Silicon Labs EFR32MG12P Mighty Gecko MCU includes:
* Cortex-M4F core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* integrated Sub-GHz and/or 2.4GHz radio
* multiple low power peripherals

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Signed-off-by: Endre Karlson <endre.karslon@gmail.com>
2018-10-19 13:47:49 -05:00
Andrei Gansari
02e217df50 drivers: eth_mcux: kinetis networking device Tree
Partially replaces Kinetis MCUX driver configuration from Kconfig to
Device Tree. Interrputs moved from defines configuration to DT.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-10-19 07:57:20 -05:00
Pawel Dunaj
ecae736e0b dts: Add support for Nordic QDEC
Add QDEC binding and entry in Nordic SoC DTSI files.

This closes issue #9364

Jira:DESK-259

Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
2018-10-17 13:45:51 -05:00
Galen Seitz
498fa532c9 soc: arm: st_stm32: stm32f3: Add support for STM32F302x8
Add Kconfig support for STM32F302x8 SoC.

Signed-off-by: Galen Seitz <galens@seitzassoc.com>
2018-10-16 22:52:07 -04:00
Galen Seitz
d509100e11 soc: arm: st_stm32: stm32f3: Add defines for I2C3
Add definitions for I2C3 which is present in some stm32f3 devices.

Signed-off-by: Galen Seitz <galens@seitzassoc.com>
2018-10-16 22:52:07 -04:00
Galen Seitz
da891b7ab2 soc: arm: st_stm32: stm32f3: Add defines for USART3
Add definitions for USART3 which is present in some stm32f3
devices.

Signed-off-by: Galen Seitz <galens@seitzassoc.com>
2018-10-16 22:52:07 -04:00
Diego Sueiro
0c7a28c4cc drivers: serial: Rework Silabs Gecko UART Driver
Introduces the location property and adds the ability to use values
generated by the device tree configuration.

Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-16 15:59:37 -05:00
qianfan Zhao
10bdfcfdbe boards: same70: Enable SPI0 on dts
Enable the SPI interface on Arduino Shield(J505 Header) default

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-10-16 14:01:29 -05:00
qianfan Zhao
7ec9057f51 dts_fixup: fix atmel same70 CONFIG_UART_SAM_PORT_2_NAME define
Remove the extra space in front of _LABEL

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-10-15 11:58:08 -05:00
Alberto Escolar Piedras
eea73e13bd soc: Kconfig: Add options for compatible NRF SOCs
Simulated NRF boards based on the POSIX ARCH cannot directly
use the current SOC_*NRF options as these pull options from
the ARM CPU and other peripherals.
This commit adds a new set of hidden SOC_COMPATIBLE_* options to
be selected both by the real SOCs and the simulated ones.
In this manner we can have the common code depend on the
SOC_COMPATIBLE* options instead of the current ones where
neccessary.

Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>

(f) arm kconfig
2018-10-15 09:36:37 -04:00
Savinay Dharmappa
bf389e0853 drivers: watchdog: Add dts support for QMSI based watchdog.
patch adds the device binding for qmsi watchdog and device node
for socs which are using wdt qmsi driver.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 14:16:03 -04:00
Savinay Dharmappa
7b6776a36a drivers: wdt: Migrate esp32 wdt driver api to new wdt interface
patch migrates the esp32 wdt driver to new wdt interfaces

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2018-10-14 14:16:03 -04:00
Anas Nashif
1d0136ef3b Revert "linker: allow SoC to insert linker script fragments"
This reverts commit 2fed930f4e.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 12:14:04 -04:00
Anas Nashif
a220e2690f Revert "arm: cypress/psoc6: add SoC specific linker input sections"
This reverts commit 08c165f2b0.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 12:14:04 -04:00
Anas Nashif
0d4b5daeaa Revert "linker: warn about orphan sections"
This reverts commit 8ce758a8ff.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 12:14:04 -04:00
Rajavardhan Gundi
47bd922f70 xtensa: intel_s1000: Remove redundant call to soc_get_ref_clk_freq
Call to soc_get_ref_clk_freq function is redundant in soc.c as it
simply returns a global static variable. Hence removed that call.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-10-12 07:52:17 -04:00
Rajavardhan Gundi
6bcb9c6a98 xtensa: intel_s1000: Move some functions to SoC level SYS_INIT
Mux configuration for I2C and GPIO are now done in SYS_INIT
which were earlier done in the respective tests.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-10-12 07:52:17 -04:00
Paweł Zadrożniak
68cb7b3e38 drivers: usb: Add nRF52840 USBD driver
* Add usbd_dc_nrfx shim

The shim is based on the previous one usbd_dc_nrf5.
For handling the USBD hardware, tested nrfx_usbd driver from nRF SDK
was used.

Briefly tested examples:
* usb/cdc_acm
* usb/dfu (USB communication only due to flash handling issues)
* usb/hid-mouse
* bluetooth/hci_usb

Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
2018-10-12 13:14:12 +02:00
Jun Li
08d5c5ef1d soc: stm32f4: enable dma options for soc
Enable "CONFIG_DMA_STM32F4X" when "CONFIG_DMA" is enabled.

Signed-off-by: Jun Li <jun.r.li@intel.com>
2018-10-11 12:58:30 -05:00
Armando Visconti
31f2e81e10 soc/arm/stm32f4xx: Add I2S defines to dts.fixup
For the stm32f4xx family the SPI and I2S are sharing same
controller, so we can reuse same definitions.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2018-10-11 16:55:00 +02:00
Armando Visconti
411dc003ee arch: arm: soc: stm32f4xx: Add LL include file also for I2S case
stm32f4xx_ll_spi.h include file is shared between I2S and SPI
(controller is same). So we need to include it even when I2S_STM32
is enabled.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2018-10-11 16:55:00 +02:00
Kumar Gala
0acc0fdd4b soc: silabs: efm32hg: Move USART fixups from board to SoC
The USART fixup in the board dir really are SoC level fixup's.  So move
them there and remove the board fixup file since there isn't anything in
it now.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-10 13:04:09 -05:00
Yannis Damigos
84737529d3 dts: st: f2/l4: Add missing maximum-speed property
Add missing maximum-speed property to usb nodes
for F2 and L4 series.

Fixes: #10472

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-10-10 12:27:55 -05:00
Marcio Montenegro
17b2ac6967 arm: exx32: Add Silabs EFM32HG soc files
The Silicon Labs EFM32 Happy Gecko MCU includes:
        * Cortex-M0+ core at 24MHz
        * Up to 64KB of flash and 8KB of RAM
        * Full speed (12 MHz) USB 2.0 Device
        * Multiple low power peripherals

Signed-off-by: Marcio Montenegro <mtuxpe@gmail.com>
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-10-10 12:00:06 -05:00
qianfan Zhao
3974978ea3 same70: Add SPI1, SPI2 support
Add SPI1/2 pinmap, dts.fixup for atmel sam series soc

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
2018-10-10 11:29:49 -05:00
Oleg Zhurakivskyy
65ea181c92 drivers: eth: e1000: Add driver for Intel PRO/1000 Ethernet controller
This patch adds a driver for Intel PRO/1000 Gigabit Ethernet controller.

The driver currently supports only a single instance of the NIC.

Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
2018-10-10 04:17:15 -04:00
Kumar Gala
c3076d6eb2 gpio: silabs gecko: Add device tree support for GPIO
Convert gpio_gecko driver over to using device tree. Added binding
files, updates to dts for various SoCs that use gpio_gecko.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-09 22:34:56 -04:00
Yannis Damigos
1c4f22edaf arch: stm32f4/f7/l4: Add usb maximum speed defines to dts fixup
Add CONFIG_USB_MAXIMUM_SPEED defines to dts fixup files.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-10-09 12:59:34 -04:00
Daniel Leung
8ce758a8ff linker: warn about orphan sections
This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.

Relates to #5534.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Daniel Leung
08c165f2b0 arm: cypress/psoc6: add SoC specific linker input sections
The Cypress PSoC6 specifies some input sections in the startup
scripts. These sections (.heap, .stack, etc.) need to be placed
at correct location.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Daniel Leung
2fed930f4e linker: allow SoC to insert linker script fragments
This allows the SoC to specify some additional linker script
fragments into the bss, data and read-only data sections.

For example, the Cypress PSOC6 has a few input sections that
must be put into bss and data sections. Without specifying
these in the linker script, they are consider orphan sections
and the placement is based on linker heuristic which is
arbitrary.

POSIX is not supported as the main linker script is
provided by the host system's binutils and we have no control
over it. Also, currently Xtensa SoCs have their own linker
scripts so there is no need to this feature.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Anas Nashif
071c9dc0f3 soc: logging: move soc tree to new logger
Use the new logger framework for soc related code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-08 17:49:12 -04:00
Pushpal Sidhu
3ed0375c8d arch: arm: mpu: add support for 640k SRAM
The STM32L4+ parts have 640k of SRAM.

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2018-10-08 12:52:00 -04:00
Pushpal Sidhu
f1d78d8f38 arm: st: add stm32l4r5xx support
New parts from ST. See http://www.st.com/en/microcontrollers/stm32l4r5-s5.html
for more details.

Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
2018-10-08 12:52:00 -04:00
Sebastian Bøe
8eb734cd82 DT: Rename from dts.fixup to dts_fixup.h
The Zephyr configuration system uses many different files in many
different formats. It makes it a lot easier for users to understand
what these files do if when we use the correct file extensions.

To this end we rename the dts.fixup files to the correct file
extension '.h'.

This is a breaking change for out-of-tree fixup files. Such files will
be detected and given an appropriate error message.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-10-08 11:38:56 -04:00
Kumar Gala
11e98fa925 riscv32: sifive-freedom: Move dts.fixup into soc dir
The dts.fixup for the hifive1 board was not board specific but related
to the SoC.  Move the dts.fixup into the SoC dir so any other boards
using this same SoC will take advantage of it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-05 13:21:49 -05:00
Chen Han
d7a6b7e101 dts: stm32f1: fix UART4 define
fix stm32f1 UART4 define in dst.fixup

Signed-off-by: Chen Han <qq1433255094@outlook.com>
2018-10-05 08:49:26 -05:00
Kumar Gala
db2ca70a23 dts: pulpino: Add device tree support for GPIO controller
Add the needed bits to get device tree support for the GPIO controller
on the Zedboard-Pulpino.  This will allow us to move LED & button info
into the board.dts.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-04 07:48:32 -05:00
Kumar Gala
be4f53fa50 riscv: Add device tree support to pulpino
Add simple device tree support for the Pulpino SoC and Zedboard-Pulpino
board port.  This gets the UART info from device tree instead of soc.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-04 07:48:32 -05:00
Kumar Gala
de78ecd79c arm: beetle: Use device tree for IRQs
Get the IRQs for the devices we define in the device tree from the dts
file.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-10-03 09:47:25 -05:00
Vincent van der Locht
b941561e74 soc: sam4s: added missing devices in sam4s range
added sam4s16b, sam4s8c, sam4s8b, sam4s4c, sam4s4b,
sam4s4a, sam4s2c, sam4s2b and sam4s2a.
Used the same order as in the data sheet and code structure
equal to same70. Updated the sam4s_xplained board to match
the altered .dtsi location of the specific SoC.

Signed-off-by: Vincent van der Locht <vincent@vlotech.nl>
2018-10-02 16:17:54 -05:00
Aurelien Jarno
335222d189 dts/arm/st_stm32: Add timers and PWM nodes to STM32 F7 series
This patch adds timers and PWM nodes to STM32 F7 series, as well as the
corresponding dts fixup entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2018-10-02 14:08:00 -07:00
Maureen Helm
89ccead382 drivers: boards: Merge HAS_DTS_SPI_DEVICE with HAS_DTS_SPI
Every board that uses dts-enabled spi drivers has a board-level dts, so
there is no need to have separate configs HAS_DTS_SPI_DEVICE and
HAS_DTS_SPI.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-10-01 21:15:06 -05:00
Maureen Helm
75bc6ba454 drivers: boards: Merge HAS_DTS_I2C_DEVICE with HAS_DTS_I2C
Every board that uses dts-enabled i2c drivers has a board-level dts, so
there is no need to have separate configs HAS_DTS_I2C_DEVICE and
HAS_DTS_I2C.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-10-01 21:15:06 -05:00
Ramakrishna Pallala
3a8e37caae soc: x86: quark_se: Select the supported Power States
Select the Low Power States supported by Intel Quark SE SoC series.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-09-28 06:54:15 +05:30
Ramakrishna Pallala
a404d4df6b soc: arc: quark_se_c1000_ss: Select the supported Power States
Select the Low Power States supported by Quark_SE_C1000_SS SoC series.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-09-28 06:54:15 +05:30
Maureen Helm
0be600016c soc: x86: arc: Remove spi base address and irq macros
Now that we get the spi base address and irq numbers from dts, we can
remove the preprocessor macros from soc.h

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-28 06:27:06 +05:30
Maureen Helm
55caa7b743 drivers: spi: Select HAS_DTS_SPI in designware driver
Makes the designware spi driver consistent with other spi drivers by
selecting HAS_DTS_SPI in the driver. This required adding spi nodes and
dts fixups to several arc and x86 socs, as well as enabling those nodes
in associated boards.

Also refactors the driver to use the base address, interrupt number, and
interrupt priority from dts.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-28 06:27:06 +05:30
Maureen Helm
c73d5c7880 boards: mimxrt1050_evk: Enable lpuart3 for bluetooth hci
Enables instance 3 of the lpuart driver, adds dts fixups, and configures
pinmuxes to use bluetooth hci on the mimxrt1050_evk board. Updates board
documentation accordingly.

Tested with samples/bluetooth/peripheral_hr, with frdm_kw41z attached as
an arduino shield running the nxp hci controller application.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-27 05:55:55 +05:30
Maureen Helm
3b72a54506 soc: nxp_imx: Use generated clock controller in dts fixup
Use the generated "_CLOCK_CONTROLLER" macro for the lpuart clock name.
This change is similar to commit
e81d9b98fe, but applied to nxp_imx.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-27 05:55:55 +05:30
Ryan QIAN
5b62ea0e7a arch: arm: nxp: imxrt1060: add device support
- Add SoC information for RT1060

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-09-26 18:14:22 -05:00
Ioannis Glaropoulos
ccffca4a5d soc: arm: mps2: remove un-necessary Kconfig option selection
Remove the selection of MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
in SOC_MPS2_AN3385, as this is selected automatically by
ARM_MPU option (for ARMv7-M MCUs).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-09-24 14:34:53 -05:00
Nazar Chornenkyy
93f938c44e arm: Add Cypress PSoC6 SoC support
Added initial support and created the corresponding device tree part for
building PSoC6 SoC as part of Zephyr.

Signed-off-by: Nazar Chornenkyy <nazar.chornenkyy@cypress.com>
Signed-off-by: Oleg Kapshii <oleg.kapshii@cypress.com>
2018-09-21 18:50:59 -04:00
Dominik Kilian
67ca29a0e7 dts: nrf: Expand nRF DTS to support ARM TrustZone CryptoCell 310
Commit introduces support for ARM TrustZone CryptoCell 310
for Nordic Semiconductor nRF SoCs in device tree.

Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
2018-09-21 00:29:58 -07:00
Adithya Baglody
0e60644ff8 soc: mps2_an385: Enable Memory Protection unit.
This patch will enable the MPU in MPS2_AN385 soc.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-20 20:35:25 -04:00
Adithya Baglody
023bc923b0 soc: mps2_an385: Added support for MPU
Added required files/support for the MPU in MPS2-AN358 (Cortex-M3).

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-20 20:35:25 -04:00
Ramakrishna Pallala
f0a2f2b423 soc: arm: nrf52: Select the supported Power States
Select the Low Power States supported by nrf52 SoC series.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-09-20 10:20:23 -04:00
Ramakrishna Pallala
6320043669 qemu: nios2: Enable UART 16550 driver for QEMU
Enable UART 16550 driver for Nios-II QEMU platform.

Note: This PR is tested with patched version Qemu 3.0.0 which
adds support for altera_10m50_zephyr machine type.

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
2018-09-20 08:51:51 -04:00
Piotr Zięcik
1c16cfcc30 arch: arm: Make ARM_MPU the sole option controlling MPU usage
This commit removes all MPU-related (ARM_CORE_MPU and NXP_MPU)
options exept ARM_MPU, which becomes master switch controlling
MPU support on ARM.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
d393186d51 arch: arm: Introduce CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options
This commit introduces CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options,
which indicate which flavour of MPU is supported by given SoC family.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
d9cc147c60 arch: nxp_kinetis: Remove HAS_SYSMPU option.
The HAS_SYSMPU option is just selecting NXP_MPU option,
which could be also controlled through menuconfig.

This commit removes the HAS_SYSMPU option and replaces
its usage by NXP_MPU option.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
edfcab428b arch: nxp_imx: Remove ARM_MPU_IMX_RT option.
The ARM_MPU_IMX_RT option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.

This commit removes the ARM_MPU_IMX_RT option and replaces
its usage by ARM_MPU option.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
9331064ff9 arch: nrf52: Remove ARM_MPU_NRF52X option.
The ARM_MPU_NRF52X option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.

This commit removes the ARM_MPU_NRF52X option and replaces
its usage by ARM_MPU option.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
c4cd4cfe7f arch: beetle: Remove ARM_MPU_ENABLE option.
The ARM_MPU_ENABLE option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.

This commit removes the ARM_MPU_ENABLE option and replaces
its usage by ARM_MPU option.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Piotr Zięcik
eb1ee5f1ee arch: stm32: Remove STM32_ARM_MPU_ENABLE option.
The STM32_ARM_MPU_ENABLE option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.

This commit removes the STM32_ARM_MPU_ENABLE option and replaces
its usage by ARM_MPU option.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-09-20 14:16:50 +02:00
Daniel Leung
8d18ebde9b gpio: add driver for Intel Apollo Lake SoC
This adds a driver for GPIO controller on the Intel
Apollo Lake SoC.

Origin: Original

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-09-19 21:36:16 -04:00
Maureen Helm
ae8d4edede soc: arm: Enable the lpspi driver and clock for the imxrt soc
Enables the mcux lpspi shim driver and subsystem clock for the imxrt
soc.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-19 09:15:29 -04:00
Kumar Gala
e4a96ccbc4 dts: Cleanup warnings associated with unit_address_format and leading 0s
We get several warnings of the form:

	Warning (unit_address_format): /soc/uart@000003f8:
	unit name should not have leading 0s

Fix these by remove the leading 0s.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-09-18 10:43:58 -07:00
Flavio Ceolin
67ca176754 headers: Fix headers across the project
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Christian Taedcke
2eb347b174 arm: exx32: Use one common soc.c for all exx32 socs
The differentiation between the MCUs is handled in the HAL from Silabs.
So all EXX32 MCUs should use the same soc.c file.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2018-09-16 08:36:41 -05:00
Yannis Damigos
0c1725116a drivers/rtc: Enable RTC driver for STM32F3 series
Enable RTC driver for STM32F3 series.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-09-14 22:48:54 -05:00
Yannis Damigos
10c763cfbc drivers/rtc: Enable RTC driver for STM32F4 series
Enable RTC driver for STM32F4 series.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2018-09-14 22:48:54 -05:00
Flavio Ceolin
da49f2e440 coccicnelle: Ignore return of memset
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.

The only directory excluded directory was ext/* since it contains
only imported code.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
Sebastian Bøe
d98e046a24 cmake: move ti_lm3s6965-specific code into the soc directory
As far as possible SoC-specific code should be contained to it's
directory and core systems should not be referencing specific
SoCs. This keeps the common code clean and makes it easier to maintain
out-of-tree SoCs.

To this end we move CONFIG_SOC_TI_LM3S6965_QEMU's soft-reset related
code out of arch/arm/core/cortex_m and into arch/arm/soc/ti_lm3s6965.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-14 10:22:20 -05:00
Anas Nashif
96455d5881 build: support out of tree SoC definition
Add the glue to make this work with SoC code outside of the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
abcf2ad5a8 kconfig: move soc selection to ZEPHYR_BASE/soc/
Rather than do that for each architecture, source SoC Kconfigs where the
code is maintained, under ZEPHYR_BASE/soc.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
563c161a80 posix: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
696aa869d5 nios2: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
279cc2e448 riscv32: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
f183444682 arc: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
70d819b405 arm: soc: move arm SoCs to top-dir
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Anas Nashif
cff0005a87 x86: move soc/cpu to top-level under soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00