Updates to MEC172x eSPI driver to support ACPI shared
memory region and EC Host Command Subsystem through
ACPI_EC1 and Embedded Memory Interface (EMI).
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add Kconfig items that can be used to query if the current SoC
support the HW peripherals for some peripherals that are missing.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Provide some factorization in pm_power_state_set procedure
to prepare shutdown case introduction.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The mismatch between the slot number and the sequence ("id") made me
suspect a bug for too long. Fix one related comment and add two more. No
code change.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Use i2c_hal functions to enable support for
multiple SoCs.
Use DT compat to enable I2C from device
tree configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add baseline support for mimxrt1160_evk Cortex M4 and M7 cores
UART shell, synchronization, and hello world have all been verified to
build and run correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface
to access the SPI flash. This commit adds the driver support for it.
With this commit, the application can call the flash APIs
(via spi_nor.c) to access the internal flash of NPCX EC chips.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
Add the power state of deep doze. When system enters deep doze, the
clock of CPU and EC can be stopped to reduce power consumption. And
enable the UART Rx WUI before entering deep doze to wake up EC and
CPU.
Tested on it8xxx2_evb board. It will reduce 5.25mA when system enters
deep doze mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit removes usage of Xen emulated PL011 SBSA UART in favor of
Xen PV console minimal implementation. Now boot log and application
output can be directly taken from hypervisor domain console, instead of
virtual UART.
Also Xen VM doc was updated according to these changes.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Add SoC-specific code, the basic device tree and Kconfig data as well
as the corresponding linker command file for the Xilinx Zynq-7000
family of SoCs. This SoC - either as a QEMU simulation or on actual
hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini-
tial target for the ARMv7 Cortex-A support.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Errata ES0392 Rev 8:
2.2.9: Reading from AXI SRAM may lead to data read corruption
Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
register.
This is applicable only to RevY (REV_ID 0x1003)
Fixes#38933
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When built with XCC for Apollolake, Zephyr fails to boot with the
default multi-core option enabled. Invalidate cache before reading
the firmware image to fix that.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add support for i.MX8MP target.
This has a 1 Xtensa HiFi4 core, with 64 KB TCM,
256KB OCRAM, 8MB SDRAM and 1 SAI as audio interface.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Refactors all of the ADC drivers to use a shared driver class
initialization priority configuration, CONFIG_ADC_INIT_PRIORITY, to
allow configuring ADC drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The
exceptions are lmp90xxx, mcp320x, and mcux_adc16 drivers which have
dependencies on GPIO, SPI, and/or DMA drivers and must therefore
initialize later than the default device priority.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Use the shared CONFIG_SERIAL_INIT_PRIORITY for driver initialization
priority.
Override the default value for the NEORV32 SoC to ensure the serial
driver is initialized after the syscon driver by default.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add a Kconfig option, similar to the one that is already available
for nRF5340, that allows enabling the REG0 (VDDH) DC/DC converter
in nRF52840. Make use of this option in Nordic boards: nRF52840 DK
and nRF52840 Dongle.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Configures the default serial driver initialization priority for NXP
SoCs to ensure that serial drivers initialize after clock control
drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Uses the stats subsys to provide simple but useful debugging stats for
power management state changes and timing.
Removes the no longer needed PM_DEBUG config option
Replaces the use of PM_DEBUG for a test clock output pin for mec1501 and
adds in its place an SoC Kconfig option to enable it.
Adds a STATS_SET macro for assigning a value to a stat group field
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The parameters to FIELD() should be the position and size of each bit
field. Correct the size of IOMODE and MAXFREQ. Otherwise, the MAXFREQ
field is overwritten by the IOMODE update during espi_npcx_configure().
Signed-off-by: Diana Zigterman <dzigterman@google.com>
Add common header files for Intel SoC FPGA. The header files define the
handoff data structure and system manager base addresses needed by
Agilex initial bring up.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Replaces the prefixes of gpio_matrix_in and gpio_matrix_out
to unify those function calls on all supported socs.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Implement the CPU idle task. The system should enter this task when
there is no any task to ensure power saving.
Tested on it8xxx2_evb board. It will reduce 12.5mA when system enters
the CPU idle task.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Provide power modes implementation for u5 socs.
For now STOP3 mode is not implemented as this mode is not
compatible with LPTIM activation and hence cannot be used
as a workable suspend to idle state using LPTIM as kernel
tick source.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When existing stop mode 1&2, VCO is set to range 4
and should be set back to range 1 to allow full speed
operations.
Rather than setting VCO at startup, set it inside clock
setting procedure so that it could done
in clock reset procedure when existing stop modes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
