At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Fix cmake depreciation warning on pre-defined linker.id
(soc/arm/renesas_ra/ra4m1/linker.ld) used for arduino_uno_r4_minima.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Allow user to disable CONFIG_ADJUST_DCDC for their board, rather than
selecting it at the SOC level. The symbol still defaults to enabled,
preserving existing behavior unless a user explicitly chooses to disable
it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.
Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Several paths are checked for existence before added as global Zephyr
include path.
The existence check was needed because some tooling emit warnings on
non-existing paths.
Only few SoCs are using those pre-defined paths, yet this code runs
for all SoCs. The principle originates back from Kbuild days, and with
CMake it's more common and generally more visible to let the CMake code
defining libraries to specify include paths.
Furthermore it appears that several SoC implementation following the
<soc-path>/include was unaware that the path would be automatically
added as include path, cause they contain lines like:
zephyr_library_include_directories(include)
Remove pre-defineds path except the `<SOC_PATH>` path, which is
guaranteed to exists.
This simplifies the CMake logic in the top-level Zephyr CMakeLists.txt
file.
This cleanup further prepares for future work where SoCs need not to
be organised under architectures which is important for multi-arch SoCs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture
For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.
Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.
Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This is support for AArch64 development board.
The board uses 4-core Cortex-A55, which are based on
the ARMv8.2 architecture.
In addition,we support smp support and
it can use 4-cores to run basic samples.
Signed-off-by: Charlie Xiong <1981639884@qq.com>
Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
For this SoC, an additional section is conditionally included on top of
the default linker script for Cortex-M. Set `SOC_LINKER_SCRIPT` to the
local `linker.ld`.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.
Update NXP HAL to remove this Kconfig as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates all x86 SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all xtensa SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all sparc SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all riscv SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all posix SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all mips SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all arm64 SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all arm SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all arc SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Save secondary dsp context when it is powered off in idle thread
and restore it when the secondary dsp is powered up. The algorithm
is aligned with ace platform.
Tested on a tgl platform.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Settings which defaults to `y` but is architecture related should have
a arch dependency for safety reasons.
Thefore add `if SPARC` to the SPARC_CASA Kconfig to ensure this setting
is only enabled on the sparc arch.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Fix a bug on cavs platform that secondary core is not powered off
by SET_DX ipc message sometimes. Secondary core is set into idle
state when switching to SOF_OFF state and then halted by primary
core. The interrupt is enabled before entring idle state, so the
secondary core may be woken up by interrupt and soc_cpus_active
is set to true before it is halted by hardware power gating. This
result to error when SOF check soc_cpus_active after the secondary
is halted.
This patch doesn't enable interrupt before idle entry to avoid above issue.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Locate common mpu code together with other arm / nxp mpu code in the
arch folder where it logically belongs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
it8xxx2 uses a custom linker script, which was not updated on
dfb3674c4c. This patch naively updates it
to support DEVNULL_REGION.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Mark .noinit section as NOLOAD and move it
next to the other NOLOAD sections. This way
it is removed from a generated image that is
embedded in the rt595 app image.
Signed-off-by: Mike J. Chen <mjchen@google.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Relocate multi-level interrupts APIs out of `irq.h` into
a new file named `irq_multilevel.h` to provide cleaner
separation between typical irq & multilevel ones.
Added preprocessor versions of `irq_to_level_x` as `IRQ_TO_Lx`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This adds a if CONFIG_SOC_FAMILY_NXP_ADSP guard in
Kconfig.defconfig for nxp_adsp. Or else all of its default
get applied everywhere. For example, qemu_xtensa fails
kernel.logging.message_capture tests because
CONFIG_TEST_LOGGING_DEFAULTS is disabled in
nxp_adsp/Kconfig.defconfig which should not have applied
to qemu_xtensa at all. So put a guard in there.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
PM should not be enabled by default at the soc level. This is an
application decision and not a platform decision whether to enable or
disable PM features.
Enabling PM by default will result in descripencies and test scope and
failures in tests that do not account for PM being enabled.
Fixes#60359
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Force STM32_ENABLE_DEBUG_SLEEP_STOP option when running tests.
This option enables Debug in Sleep/stop states and disables it when
disabled (default state).
When disabled, it may be impossible to flash the device with runner
such as openocd. It's generally working using cubeprogrammer, but it might
fail as well with fault configuration.
Instead of fixing each test or breaking CI each time a new test is created
with CONFIG_PM=y, force this option to be enabled when ZTEST=y (as it was
already the case when DEBUG=y).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.
Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
In preparation for RT500 ADSP enablement, consolidate common Xtensa
configuration parameters in top level Kconfig.defconfig.
Signed-off-by: Dmitry Lukyantsev <dmitrylu@google.com>
ESP32 flash_mmap() function requires `_rodata_reserved_start` address
to be at the beginning of RODATA. This allows adding memory-mapped flash
areas.
Fixes#52764
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit adds an implementation of poweroff, which first
uses SUPC to enable all defined wakeup sources (except for
sam4l), followed by entering backup mode.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Now the API to manage GPREGRET register is unified for all devices
having one or more GPREGRET entries.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
