Commit graph

5973 commits

Author SHA1 Message Date
Gerard Marull-Paretas
a8c93478db soc: arm: nordic_nrf: move soc_nrf_common.h to common folder
Since the addition of pinctrl the common folder is added to the Zephyr
include path. This can be re-used to place the soc_nrf_common.h header
in the common folder and include it directly, without the need of
relative paths.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 14:20:51 +01:00
Gerard Marull-Paretas
22c8c02145 drivers: pinctrl: nrf: initial support
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.

Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.

Thanks to Marti Bolivar for bindings documentation.

Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 14:20:51 +01:00
Gerard Marull-Paretas
9c10e1e988 drivers: pinctrl: stm32: initial version
Add initial version for STM32 pinctrl driver. Driver has been written
re-using many of the already existing parts in
drivers/pinmux/pinmux_stm32.c.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-26 11:36:42 +01:00
Andy Ross
4648b63661 soc/intel_adsp: Add support for legacy IDC driver for pre-2.5 hardware
The IDC driver was written for Tiger Lake era devices, but works fine
on the earlier hardware too.  Make it selectable; if you don't
configure IPM_CAVS_IDC, then you get the new driver.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
c6de46c87e soc/intel_adsp: Simplify boot ROM protocol
There was an attempt in the old code to express this as a formal
protocol with a proper field definitions, etc...  But in fact no such
protocol really exists.  This scheme is only used in one place to send
one specific message to code fixed in ROM on legacy devices that only
knows how to recognize this specific value.  And 2.5 and later
hardware are moving away from it anyway.

Just express it directly, and explain in comments.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
a7af0acfc2 soc/intel_adsp: Clean up IPM compiler guards
The CAVS_IDC_IPM driver happens to be used only on non-2.5 hardware,
but it's best to be clear in the conditional compilation when we're
talking about hardware-dependencies and when we mean software
configuration.  This was mixed up in a few spots.

Also fix a warning that creeps in on non-default drivers choices about
an undeclared ipm function.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
a3c9443c4a soc/intel_adsp: Unify linker scripts
While the linker scripts for these platforms had diverged in form, the
behavior remained compatible.  Link all cAVS devices with the same
linker script included from the common directory (it's a verbatim copy
of the cavs_v25 script).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
73b2f5544b soc/intel_adsp: Move generated interrupt routines to common code
While technically this file can change for any instantiation of Xtensa
hardware, in practice all these devices have identical interrupts
setups.  These files were duplicates, so there's no value in keeping
them in per-sub-soc directories.  (Really we should wire it up so that
the generator gets run automatically with the build, but that will
need to wait for a rework of interrupt entry).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
430cbf430a soc/intel_adsp: Eliminate platform configuration headers
All the in-use contents of these files have now been moved to the
intel_adsp core, and they are configured via devicetree and kconfig.
Remove the legacy headers.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
9cba8501df soc/intel_asdp: Unify misc. initialization registers
These two register blocks are defined in the platform layers, but
never change (except on 1.5 where they don't exist).  I don't want to
write a full devicetree interface for them as I can't find good docs
currently.  They are used only at system initialization, so move the
definitions to the single file where they're used.  In the longer term
we will want to move at least the GPDMA setup into a driver anyway.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
cb73032a32 soc/intel_adsp: Unify/dtsify L2 local memory control block
These registers were hardwired in the platform layer.  Move to
devicetree, via a struct interface that looks like the pre-existing
shim layer.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
73f3374764 soc/intel_adsp: Unify boot loader memory layout
These values (used to arrange the bootloader within IMR memory) are
mostly computed or fixed to values that don't chagne between
platforms.  Only the manifest address and the location of the data
section change.  Put those in kconfig, move the rest to the global
header.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
dea61d2099 soc/intel_adsp: Add workarounds for building bootloader with xcc
The bootloader code on this SOC has its own cmake rules, which means
it doesn't get the Zephyr-specific magic from the toolchain layer and
the code needs to handle fixups manually.  (Specifically: we have a
xcc_missing_defs.h header to provide gcc symbols that xcc doesn't
have, and assembly needs to be built with _ASMLANGUAGE so headers
don't include C syntax.)

Long term the right solution here is to build the bootloader as part
of the Zephyr binary.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
0732b1a087 soc/intel_adsp: Clean up host memory window layout
The locations of the memory windows within the reserved SRAM region
was being construted via a bunch of magic numbers referencing
(potentially historical?) SOF usage of those areas.  But Zephyr only
ever touches two of these windows, and only cares about the sizes and
offsets.  The complexity was hurting and not helping (especially since
there was no attempt made to unify these values with the ones that are
actually live in the SOF tree).

Replace with kconfig variables that simply specify the offset.  Only
one platform has a nonstandard layout anyway.  That allows SOF to move
things around in a clean way if it wants.  Ideally we should be
presenting a proper API for managing this region, though.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
dd959bd270 soc/intel_adsp: Unify LP-SRAM sizing
Same as for the HP-SRAM memory region.  It's already exposed in
devicetree, so take the per-platform values out (including some dead
code on 2.5) and put them in a global header.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
de01a4419a soc/intel_adsp: Remove magic entry point addresses
The platform layer (except cAVS 1.5, which computed it via alternate
means as an offset on other stuff) was specifying the entry point as
an explicit address needlessly.  In fact the linker scripts already
are written to place the entry point at the first address of linkable
RAM, which is already available as the RAM_BASE symbol.

Unify.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
ef372d055d soc/intel_adsp: Unify host window register interface
These registers are identical on all platforms, the only difference
being that cAVS 1.5 places them at a different address.

Create a devicetree node to track the register block, and replace the
platform header code with a global API defined once (it works like the
pre-existing shim struct).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
003c878245 soc/intel_adsp: Unify "firmware status register" window size
There is a diverged definition for SRAM_REG_FW_END, which exists to
prevent the Zephyr window initialization from changing values that
were already set by the ROM or bootloader (though this is incomplete,
as we're not ensuring the memory is actually the same space except by
convention; we also don't have any Zephyr-side visibility as to the
content of this struct).

That was silly; the only thing worse than one magic number is four
magic numbers in different files.  Write a formula that works for all
the platforms and put it in the C file where it's used.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
33bd649d4e soc/intel_adsp: Unify "RAM" region
There was a divergent set of definitions for a "RAM" region for the
benefit of memory layout in the platform headers.  In fact there was
only one platform dependence (cAVS 1.5 has 32k instead of 64k
reserved).  Put that into kconfig in a single place, and add a warning
that this is a trap region with hidden dependencies in both Zephyr and
SOF.  Good enough until we clean this up and make everything visible
to the linker.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
f4686eb010 soc/intel_adsp: Unify fake linker sections
There are multiple "fake" (not part of image) sections needless linked
to explicit addresses right now.  This should be cleaned up, but in
the meantime let's at least put their definitions all in one place so
they aren't cut/pasted into every platform.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
f487b672f3 soc/intel_adsp: Move invariant bootloader params out of platform layer
These macros (LPSRAM_MASK, SRAM_BANK_SIZE, HOST_PAGE_SIZE) never
change, and are always used in just one file.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
c6e0ada4bf soc/intel_adsp: Unify HP-SRAM definition
The HP SRAM block address and size is specified in four different ways
(devicetree, "SRAM_*", "HP_SRAM_*" and "L2_SRAM_*" macros).  Unify,
moving the C definition (which just fetches it from dts) to a single
header and out of the platform layer.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
411d8b9624 soc: intel_adsp: Unify vector table generation
This was an abstraction layer without a purpose.  All existing
platforms have the same (LXn core) layout.  When we need to split this
out in the future, the right thing will be to use the values already
provided by the platform core-isa.h and not duplicate them anyway.

Think of this as a first step to an incoming rework of the Zephyr
Xtensa interrupt entry generation, which is long overdue.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
ff1ccbd83c soc: intel_adsp: Unify bootloader configuration
The generic bootloader code used a per-device "platform.h" file
imported from SOF.  These turn out to have very little actual content.
Move them to the core directory in a single header for now, pending
some rework to place the settings in devicetree.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
9d7da4cdec soc: intel_adsp: Remove old support for cAVS 2.5 "alternate boot"
The linker script (and a little bit of SOF) still has support for an
older mechanism for bootstrapping secondary cores by copying code into
lp-sram from a "manifest" emitted by the linker.  This actually never
worked in Zephyr, and we've implemented a different scheme that uses a
small runtime-copied trampoline instead.

Remove.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
ed9434c812 soc: intel_adsp: Clean up shim driver
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions.  This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.

Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.

Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block.  Those will be unified in separate
patches.

Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
12df8fca4e soc: intel_asdp: Clean up soc_init() code
Reorganize the initialization code to cleanly separate the platforms
and clarify which code is common.  The #if'ery was sort of a mess.
This is in preparation for an incoming patch that unifies the shim
register definitions across platform variants.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
4652d6534e soc: intel_adsp: General soc_mp.c cleanup
Misc cleanup, no non-trivial logic changes.

Swap in new ("rsr <reg>, REGISTER_NAME") syntax for Xtensa SR's in
place of inconsistent usage of the older one ("rsr.REGISTER_NAME
<reg>").

Remove the legacy handling of !KERNEL_COHERENCE cases for allocating
the cpu start record.  That has long been a requirement of
multiprocessor code on this platform.

Remove the synchronous testing of the "alive" flag in
arch_start_cpu().  Nothign about that API is intended to be
synchronous, and in fact the Zephyr SMP layer is already doing the
same trick.

Remove some vestigial dead code at the end of z_mp_entry().  It was
apparently intended to handle the case where a CPU function returned,
but that's not legal anyway.  And it was only enabled in the case
where there was only one CPU anyway, which was an impossible situation
(you can't evercall arch_start_cpu() successfully on a system with
only one core, for obvious reasons -- the only core is already
running!).  Replace with an assertion.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Andy Ross
2cb75dc463 soc/intel_adsp: Fix _ASMLANGUAGE declaration for boot_entry.S
The cAVS bootloader code (for... somewhat silly reasons) doesn't build
via the same paths as regular Zephyr object files, so it wasn't
getting the _ASMLANGUAGE define.  That meant that Zephyr headers
defining BIT() were using syntax incompatible with some assemblers
(specifically the Cadence xcc assembly; current gas versions were
fine).

Not 100% sure this is the best spot to put this, but the root fix is
to get the bootloader building into the same link as the rest of
Zephyr anyway.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-11-23 13:23:54 -05:00
Daniel DeGrasse
e70907f52d drivers: mcux_flexspi: Default logging to disabled when XIP is used
Program flow will behave incorrectly (memory and instruction fetches
return invalid data) if Flexspi is accessed by the Flexspi driver while
being used as XIP memory by the Cortex M7.

Set logging to disabled by when XIP mode is used in the memc and
flexspi drivers, and warn the user if they attempt to enable it.

Fixes #40133

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-22 22:27:13 -05:00
Gerard Marull-Paretas
037869e28d soc: arm: gigadevice: enable pinctrl by default
Enable pinctrl by default, since it is an essential component on almost
every firmware. Inclusion of series defconfig has also been guarded with
SoC availability (was missing).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
f45c2668e3 soc: arm: gigadevice: gd32f403: select AFIO pinmux
GD32F403 series use AFIO pinmux model.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
f8017dc5ad drivers: pinctrl: gd32: initial support for AFIO based SoCs
Add a pin control driver for GD32 SoCs using the AFIO model.

Thanks to Gerson Fernando Budke for testing and implementation
suggestions.

Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
5c44620753 soc: arm: gigadevice: gd32f4xx: select AF pinmux
GD32F4XX series have AF based pinmux.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Gerard Marull-Paretas
543a3843ff drivers: pinctrl: gd32: initial support for AF based SoCs
Add a pin control driver for GD32 SoCs using the AF model.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-22 16:30:28 -05:00
Glauber Maroto Ferreira
ddd0a82ac7 esp32 & esp32s2: lint: kconfig
fixes indentation of esp32 and esp32s2 kconfig
soc files.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-11-22 08:31:56 -05:00
Glauber Maroto Ferreira
963a707ae4 soc: esp32s2: refactor cache and bss initialization
- refactors cache initialization functions by moving it from
soc.c and placing it in soc_cache.c
- moves SPIRAM's bss zeroing before SPIRAM initialization

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-11-20 11:57:38 -05:00
Glauber Maroto Ferreira
c5857dc0cd soc: esp32s2: SPIRAM: remove unused configs
and updates hal_espressif's revision.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-11-20 11:57:38 -05:00
Glauber Maroto Ferreira
89ec6f6863 soc: esp32s2: add SPI RAM support
brings support to external esp32s2 RAM memory.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-11-20 11:57:38 -05:00
Glauber Maroto Ferreira
661b5cf84d soc: xtensa: esp32s2: add data cache initialization
during esp32s2 boot.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-11-20 11:57:38 -05:00
Gerard Marull-Paretas
95fd99aba3 soc: arm: gigadevice: add support for GD32F4XX SoCs
Add support for the F4XX series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
2dc24bbac8 soc: arm: gigadevice: gd32f403: cleanup soc.h
- Remove unnecessary include guard
- Fix comments

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
96966d180b soc: arm: gigadevice: gd32f403: simplify soc selection
There is no need to specify SoC suffixes, so simplify the selection.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
Gerard Marull-Paretas
fcbb9476f8 soc: arm: gigadevice: use specific series for GD32F403
Despite the "F4" prefix, GD32F403 is an SoC with significant differences
compared to other F4 MCUs:

- It has a completely different HAL
- It has significant hardware differences, for example, the pinctrl
  mechanism uses AFIO (all others use AF)

The grouping principles applied to other similar vendors such as ST
can't be applied for GD32 due to these reasons, so the approach taken
here is to define series based on the used HAL. A different HAL likely
means that there are significant hardware differences between, e.g. F403
and F405. The vendor likely chose a confusing naming scheme, but we need
to deal with it.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-11-18 17:42:57 +01:00
David Leach
a09ba37334 MXRT600: Fix secure/non-secure definition for FLEXSPI
The Flexspi memory address defines the location of the externally
attached flash to the MXRT600 based board. The flexspi has two
different memory spaces for secure and non-secure access that are
not aligned for the Flexspi register space and the memory map
address space. The normal method of handling this via the two
different dts files for secure/non-secure is not able to handle
this because a base address is applied uniformly across multiple
reg items.

Changes include:

- pull flexspi out of peripherals block to allow it to be explicitly
expressed in the respective secure/non-secure SOC DTS files.
- move the flash size definition to the board level definition and
use the size of the actual flash device found on the board.
:
Signed-off-by: David Leach <david.leach@nxp.com>
2021-11-18 14:29:53 +01:00
Manojkumar Subramaniam
22186c7c51 soc: arm: st_stm32: use SMPS power supply only if enabled
Use SMPS power supply only if enabled.

The default power supply configuration for the
NUCLEO board with -Q subfix is SMPS,
so it's essential to match with hardware configuration
to avoid deadlocks due to mismatch.

if a custom board with LDO configuration is in use,
then no need to enable `CONFIG_POWER_SUPPLY_SMPS`

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2021-11-18 13:56:39 +01:00
Manojkumar Subramaniam
7a690a56c5 soc: arm: st_stm32: add kconfig entry for STM32 SMPS
Add support for SMPS

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2021-11-18 13:56:39 +01:00
Tim Lin
e29a15c0e3 ITE: drivers/serial: add the UART driver for the PM callback function
IT8XXX2 uses shared ns16550.c driver which does not provide a power
management callback(pm_action_cb), so create driver to handle
IT8XXX2 specific UART features.

note: pm_action_cb(old name: pm_control_fn)

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-11-16 21:23:42 -05:00
Daniel Leung
566c466343 soc: intel_adsp/cavs_v20: correct linker syntax for old binutils
Applying similar changes to cavs_v20 as in commit
8bc4539cec:

  Older binutils, like the (nine-year-old!) 2.23 version that powers
  many Cadence XCC toolchains, happen not to support the "~" operator to
  perform bitwise negation.  And they generate an absolutely hilarious
  series of inscrutable error messages when they try to tell you this
  fairly simple fact.

  Just fold it into the constant.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-11-16 10:13:46 -05:00
Daniel Leung
2d5c724ed8 Revert "soc: intel_adsp: fix linker script for cavs_v20"
This reverts commit 3cc14b2c2b.

Revert this due to the same reason as commit
a29b66bbf5:

  Unfortunately this mechanism doesn't seem to actually work on the SDK
  linker.  The emitted sections, when passed a symbol name as the "start
  address" just appear wherever the "." variable was pointing (in this
  case, into the cached region).  That breaks the kernel coherence
  layer, obviously.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-11-16 10:13:46 -05:00