Commit graph

5973 commits

Author SHA1 Message Date
Andy Ross
1a2fecec6d soc/intel_adsp: Unify Xtensa CPU reset between cores
Startup on these devices was sort of a mess, with multiple variants of
Xtensa and platform initialization code from multiple ancestries being
invoked at different places for different purposes.  Just use one code
path for everyone.

Bootloader entry starts with a minimal assembly stub that simply sets
WINDOW{START,BASE}, PS and a stack pointer and then jumps to C code.
That then uses the cpu_early_init() implementation from cAVS 2.5's
secondary cores to finish Xtensa initialization, and then flows
directly into the pre-existing bootloader C code to initialize cache
and memory and copy the HP-SRAM image, then it invokes Zephyr via a
simple C function call to z_cstart().

Likewise, remove the "reset vector" from Zephyr.  This was never a
reset vector, reset on these devices goes to a fixed address in a ROM.
CPU initialization is handled explicitly and completely in the
bootloader now, in a way that can be unified between the main and
secondary cores.  Entry from the bootloader now goes directly into
z_cstart() via a C call (via a single jump instruction placed at the
entry point address -- that's going away soon too once we're using a
unified link).

Now that vector table initialization happens in a uniform way, there's
no need to copy the VECBASE value during arch_start_cpu().

Finally note that this also reverts the
CONFIG_RESET_VECTOR_IN_BOOTLOADER kconfig variable added for these
platforms, because it's no longer a tunable and true always.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-14 18:43:05 -06:00
Andy Ross
887eeb74d3 soc/intel_adsp: Refactor boot loader initialization path
Remove an unused strcmp() implementation.  Flatten the call tree for
HP-SRAM initialization for clarity.  Better isolate the platform
dependencies so e.g. hp_sram_pm_banks() becomes a clean noop on 1.5.

Also removes some dead/vestigial "error" handling, which wasn't being
propagated anywhere.  Note that error detection and handling is a bad
idea, but this is VERY early code.  We don't have even a theoretical
way of getting information back to the host until after SRAM is
initialized and window zero is set up.  (And even then there's no
protocol available other than signaling "FW_ENTERED" or... not).

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-14 18:43:05 -06:00
Andy Ross
1a9310efa1 soc/intel_adsp: Rework Xtensa region protection initialization
Our "TLB"[1] initialization on secondary cores for cAVS 2.5 was
forgetting to initialize instruction caching, leading to a performance
regression.  Clean this up and augment so that it matches the (larger,
non-C-callable) HAL implementation.

This will also allow us to use the same code on the main core in
upcoming changes.

[1] It's not a TLB, it just uses the TLB management instructions

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-14 18:43:05 -06:00
Andy Ross
f1e941acd4 soc/intel_adsp: Align .rodata with .data in bootloader
This seems to be a mistake in rimage: it wants the text and data
segments of the output module to be page-aligned, but it assumes
.rodata is part of "data" and not "text".  So this reorders the
segments to make that happen.

Note that the page alignment is entirely artificial.  Nothing is
interpreting the segment boundaries rimage is enforcing except for the
code in the bootloader itself, which doesn't care.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-14 18:43:05 -06:00
Andy Ross
fd622eb419 soc/intel_adsp: Remove dead code in bootloader
There was some vestigial handling here for Sue Creek (which this code
has never supported, that's a different board in Zephyr) and some code
that apparently managed a bug workaround in the ancestral SOF code.
Neither was buildable.  Remove.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-14 18:43:05 -06:00
Andy Ross
b6635456d1 soc/intel_adsp: Refactor, move CPU init into a separate header
Move the very-early core initialization hooks (which are a mix of
Xtensa architectural features and Intel-specific hardwareisms) into a
separate header so they can be shared between the bootloader, main
core, and MP cores.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-14 18:43:05 -06:00
Lauren Murphy
c1711997bc debug: coredump: add xtensa coredump
Adds Xtensa as supported architecture for coredump. Fixes
a few typos in documentation, Kconfig and a C file. Dumps
minimal set of registers shown by 'info registers' in GDB
for the sample_controller and ESP32 SOCs. Updates tests.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2021-12-14 07:40:55 -05:00
Daniel DeGrasse
91a25cc59a soc: mimxrt685_evk: Fix usdhc driver build failure
USDHC driver build failure fix for mimxrt685_evk, dat3 pull function was
not defined at the SOC level.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-13 20:30:06 -05:00
HaiLong Yang
b863420013 soc: arm: gigadevice: add support for GD32F3X0 SoCs
Add support for GigaDevice GD32F3X0 series.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2021-12-13 20:27:30 -05:00
Daniel DeGrasse
b330f18a39 boards: mimxrt1xxx: Added support for GPT hardware timer on RT1xxx
Adds support for using GPT as the hardware timer source (as opposed to
systick) for all RT1xxx platforms. This requires moving the clock
frequency of these devices into a defconfig so it can be overridden by
the GPT clock frequency.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-13 20:13:21 -05:00
Daniel DeGrasse
e99eb6bb70 drivers: mcux_gpt_timer: Enabled GPT timer on MIMXRT1064 EVK
This enables the GPT timer for use as a hardware clock on the
MIMXRT1064. The timer will be disabled when builds use the GPT timer as
a counter, and the build will fall back to using the Cortex M systick as
a timer. This was tested using the kernel tickless test, to verify the
driver functions as expected.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-13 20:13:21 -05:00
Daniel DeGrasse
fa56e9ee2b drivers: mcux_gpt_timer: Added GPT timer for HW clock
Added a driver to enable the GPT timer on RT1xxx parts to be used
instead of systick as a clock source. The timer is set to run in reset
mode, and uses the low frequency 32kHz oscillator for power savings

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-13 20:13:21 -05:00
Kai Vehmanen
af31478e16 Revert "soc: cavs_v25: increase core count default to 4"
This reverts commit af79664da3.

The patch caused regression on TGL-H systems where only 2 DSP
cores are available. The Kconfig override used by existing SOF
application does not work with Zephyr. A quick fix using
Zephyr board revisions was considered, but review feedback
was that core count difference should be reflected in SoC-level
device tree. This will take more time to develop, so the revert
is needed to fix the immediate regression.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2021-12-13 19:31:45 -05:00
Daniel DeGrasse
cd4cc7af42 soc: MIMXRT11xx: Enable FlexSPI on MIMXRT11xx
Enable flexspi for RT11xx SOCs. This requires selecting the correct
KConfig symbol for the cortex m4 and m7 SOCs, as well as correcting an
error in the flexspi DTS node and updating the clock init for RT11xx
SOCs.

Note that in addition, the NXP hal must be updated to properly support
including the cache management driver for the Cortex M4.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-09 19:32:45 -05:00
Jordan Yates
f408f42e36 linker: link into derived section names
Link variables into derived section names instead of hardcoded names.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-12-09 16:23:03 +01:00
Jordan Yates
7b2a388d1d linker: remove manual name specification
As memory region names are now derived purely from devicetree, remove
the `name` parameter from `DT_REGION_FROM_NODE_STATUS_OKAY`. Name is
`zephyr,linker-region` if it exists, otherwise the node path.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2021-12-09 16:23:03 +01:00
Mahesh Mahadevan
1d44e281a6 soc: Include PINT include file conditionally
Include fsl_pint.h header file only when the
CONFIG_GPIO_MCUX_LPC is enabled

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-12-09 09:18:10 -06:00
Kumar Gala
91d4b7766c soc: arm: mps3: Only enable MVE if not QEMU
QEMU doesn't currently support MVE until the QEMU 6.2 release is out.
So for now only enable MVE support if we are NOT targetting QEMU.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-12-08 16:50:27 -06:00
Gennady Kovalev
b49766f001 drivers: clock_control: More power supply modes for STM32H7
STM32H7 has different power supply modes but now Zephyr supports just LDO
and direct SMPS. This commit introduses POWER_SUPPLY_CHOICE configuration
parameter and add support for missed power supply modes.

Signed-off-by: Gennady Kovalev <gik@bigur.com>

Fixes #40730.
2021-12-08 09:12:12 -05:00
Jay Vasanth
fd43c725d2 drivers: spi: Add MEC172x QMSPI-LDMA driver
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2021-12-08 08:43:05 -05:00
Daniel DeGrasse
459d9dc43f soc: MIMXRT11xx update clock init code
RT11xx clock init code was not handling difference between RT1160 and
RT1170 Bus_Lpsr clock correctly. Fix this.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-08 08:40:06 -05:00
Daniel DeGrasse
b18aefdfd3 dts: rt685: enabled flexcomm15
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-08 08:27:44 -05:00
Andy Ross
43d1d15da8 soc/intel_adsp: Remove interrupt masking from secondary core startup
There is some legacy code that tries to mask IDC interrupts when
starting up cores.  This is there because the IDC interrupt is both
the system IPI when Zephyr is running (and can thus be signaled
asynchronously to the code calling arch_start_cpu()) and the messaging
protocol to the boot ROM on the other CPU.  So the idea is that we
mask interrupts after startup so nothing is confused.

But that's needless in the current architecture.  We maintain a
synchronized cpus_active[] record that will show true/active for any
CPU between the end of its SMP startup sequence and the beginning of
the shutdown process in soc_halt_cpu(), and false at all other times.
An IPI will never be sent to a CPU that is running in the boot ROM,
because such a CPU will be flagged as inactive.  Likewise a ROM
startup IDC will never be sent to a CPU running Zephyr code for the
converse reason.  Remove all that code.

Unfortunately SOF itself still needs an interrupt unmask step at CPU
startup, because it's still doing its own masking (probably according
to the same algorithm that we imported).  Leave that in place as a
minimal workaround until we get that fixed upstream.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
29b99aa93a soc/intel_adsp: Add MP startup delay on cAVS 1.5
Investigation by Kai Vehmanen has shown that there is a very short
delay needed before starting the secondary core on cAVS 1.5 hardware.
What we finally realized is happening is that on these devices,
secondary core power is managed by the host.  The cavs-fw.py test
integration powers the second core on at system startup and lets
Zephyr start it later, but SOF will power it up and send an IPC to the
firmware immediately.

There is a period after power-up but before the ROM is available
(unclear whether this is a race vs. hardware, the ROM firmware, or the
kernel driver, or potentially some combination); interrupts latched
earlier than that seem to be cleared by CPU initialization.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
7319bd3425 soc/intel_adsp: Clean up cavs PWRCTL/PWRSTS/CLKCTL usage
These registers were defined in the new interface, but still being
used with bare bits (and in one spot a legacy field access macro).
Clean things up and use macros pervasively.  To be fair: in this
particular case the field names aren't particularly descriptive...

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
cf2134fb9b soc/intel_adsp: Fix IDC register description
The usage of this interface is correct, but the docs in the header
spoonerized the source and destination of masking in the INTCTL
registers.  Oops.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
35845dc67d soc/intel_adsp: Remove support for legacy IPM driver
Remove support for the legacy IPM-based sched_ipi implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
4ee79fed81 soc/intel_adsp_cavs15: Use new IDC driver
Disable the use of the legacy IDC driver and IPM-based sched_ipi()
implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
7d9a72816c soc/intel_adsp_cavs20: Use new IDC driver
Disable the use of the legacy IDC driver and IPM-based sched_ipi()
implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
923277a842 soc/intel_adsp_cavs18: Use new IDC driver
Disable the use of the legacy IDC driver and IPM-based sched_ipi()
implementation.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:09:02 -05:00
Andy Ross
692770a2f0 soc/intel_adsp: Move boot stack to IMR memory
Put the initial stack in (slow) IMR memory instead of HP-SRAM.  Very
little happens on this stack anyway before Zephyr switches off to the
interrupt stack and/or main thread.  And this will allow us to start
running stackful C code much earlier in the boot process.

This puts the stack into the region of memory immediately below the
IMR image (because that edge of the image is easier to detect in
code).  On all current platforms, that's offset quite a bit into IMR
space and leaves plenty of room.  But we should have some kind
architectural way to reserve this space...

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:07:53 -05:00
Andy Ross
a42da8dcdb soc/intel_adsp: Minimize bootloader linker script
The memory layout for the boot loader was needlessly complicated, with
separate fixed regions defined at fixed addresses, all in a file that
needs to be contiguous and DMA'd from the host in a single block.  The
end result was a lot of magic numbers and wasted space.

Clean things up so that it links in a single region expressed (for the
benefit of rimage, I think) as a single program header in the ELF
file.

This is in preparation for further changes to unify the bootloader
stage with the main Zephyr image in a single link.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:07:53 -05:00
Andy Ross
1e1830de95 soc/intel_s1000: Add new cAVS shim & IDC interfaces
This board, whose hardware is just a cAVS 1.8 device without an x86
host CPU, started life (as all the cAVS devices did) as a
cut-and-pasted copy of the same basic code.

Because of hardware and schedule limitations, it didn't get the same
unification treatment that all the other platforms did.  But it turns
out that in SMP configurations (which... it's not clear if we actually
test on hardware?) it wants to use the cavs_timer driver, which now
uses the new SOC API and not the old one.  Which s1000 doesn't expose.

So... I guess we have to continue to cut and paste until we can find
time to unify this.  Add a copy of the new shim/IDC headers to this
SOC and expose them via devivcetree.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-07 12:06:21 -05:00
Pieter De Gendt
4d161a3b23 drivers: counter: NXP SNVS rtc: Add support for NXP imx SNVS RTC
Adds a driver using the SNVS high power and optionally low power
RTC instances. A device specific function `mcux_snvs_rtc_set` is
provided to update the current counter value.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2021-12-07 09:45:43 -06:00
Daniel DeGrasse
57f35bbf5a drivers: USDHC: Enable detection using DAT3 pulldown
Enable USDHC host to detect inserted SD card via DAT3 line pulldown.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-06 15:27:25 -05:00
Daniel DeGrasse
9ee2709e0a soc: rt11xx: Enable USDHC for RT11xx devices
RT11xx SOC definitions did not enable USDHC controller. Select Kconfig
symbols required to enable it.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-06 15:27:25 -05:00
Gerard Marull-Paretas
7d1bfb51ae drivers: timer: cortex_m_systick: improve ISR installation
A Cortex-M specific function (sys_clock_isr()) was defined as a weak
function, so in practice it was always available when system clock was
enabled, even if no Cortex-M systick was available. This patch
introduces an auxiliary Kconfig option that, when selected, the ISR
function gets installed. External SysTick drivers can also make use of
this function, thus achieving the same functionality offered today but
in a cleaner way.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-12-04 07:34:53 -05:00
Glauber Maroto Ferreira
31e5b1b861 soc: esp32s2: fix: data cache setup
data cache mode setup and enabling should be done only when
CONFIG_ESP_SPIRAM is enabled. Otherwise, memory layout will
conflict with defaults.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-12-03 16:45:16 -06:00
Daniel DeGrasse
20b43d7e8d boards: mimxrt1170_evk: Enable PWM on RT1170 EVK
PWM is enabled on RT1170 EVK, for both Cortex M4 and M7 cores. Tested
using led_pwm sample.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-03 16:44:12 -06:00
Kai Vehmanen
af79664da3 soc: cavs_v25: increase core count default to 4
The default config for cavs25 should be a 4 core config. Variants that
have less cores, need to override the config option to a smaller value.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2021-12-02 23:56:27 -05:00
Yuguo Zou
abeaf94855 soc: arc: fix ARC_HAS_ACCL_REGS settings
ARC_HAS_ACCL_REGS should set to y to protect ACCL and ACCH registers
during irq. These registers could be used as GPRs by compilers and
therefore need store/restore during irq.

Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
2021-12-02 11:32:14 -06:00
Hake Huang
57b23c7308 boards: i2s: enable i2s support for mimxrt1060_evk
add i2s(sai) support for mimxrt1060_evk and related
pinmux

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2021-12-02 10:50:21 +01:00
BJ Chen
8d895a7d7a soc: it8xxx2: cleanup: Obsolete PS/2 registers definitions removal
Removed the obsolete PS/2 registers definitions
for the PS/2 module was removed from the chip

Signed-off-by: BJ Chen <bj.chen@ite.com.tw>
2021-12-01 13:50:27 -06:00
Wealian Liao
230378aebe driver: uart_npcx: Fix uart to use PM constrain
The device PM callback needs to be used only to suspend/resume devices.
If the system cannot be suspended because UART is in a particular
state, the pm_constraint_set/release API should be used. For NPCX UART,
the chip can't enter low power idle state until UART completes the data
transmission.
This commit changes NPCX UART to use pm_constraint_set/release & fixes
UART lost data from low power idle.

Fix #40621

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2021-12-01 13:49:17 -06:00
Daniel Leung
5d19da4507 soc: esp32: add support for GDB stub
This adds the SoC specific bits to enable GDB stub,
mainly the description for the register file, and
memory regions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-11-30 15:24:00 -05:00
Daniel DeGrasse
662a131713 soc: rt6xx: Default flexspi logging to disabled
RT600 uses the mcux flexspi driver, which can produce RWW hazards when
calling code linked into flash (such as the logging subsystem). Disable
logging in flexspi driver by default for RT600 series.

Fixes #40744

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-11-30 13:54:06 -06:00
Antonio Tessarolo
cc1cd4d65b arm: Nxp imx6sx added PWM support
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.

Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
2021-11-30 11:54:11 -06:00
Ruibin Chang
fad78a2c07 ITE drivers/sensor: add tachometer driver for it8xxx2_evb
Add tachometer driver for it8xxx2_evb.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-11-29 08:25:19 -05:00
Gerard Marull-Paretas
51df9fc8d9 soc: arm: st_stm32: stm32u5: fix pm_power_state_set
Some PM cases were not handled correctly (missing default statement).
The error was caught by CI while doing other PM related work.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-11-29 11:08:38 +01:00
Dino Li
f1f0dadad3 driver: espi: it8xxx2: enable ESPI_OOB_CHANNEL
This enable eSPI out-of-band channel.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-11-26 10:26:52 -05:00