cavs15, cavs18 and cavs20 were removed from Zephyr there is no
need to handle those platforms in the tool.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fix USB w/ SPEED_OPTIMIZATIONS for LPC55xxx SoCs
Root cause was non-volatile register access,
which could get optimized by the compiler
(by -fschedule-insns, specifically)
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Imply CONFIG_INIT_AUDIO_PLL on nxp,dmic driver selection on
mimxrt685s/cm33. Make DMIC clock config dependent on the use of the
RT685's audio PLL.
Fixes a regression described in #77851.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
The STM32WB06 and STM32WB07 SoCs do not support SMPS output current limit.
This makes the LL_PWR_SetSMPSPrechargeLimitCurrent function and all the
LL_PWR_SMPS_PRECH_LIMIT_CUR_xxx defines not visible when one of these SoCs
is selected, resulting in a build failure.
Fix this by only handling SMPS current limit when the feature is available.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
On platforms with enforced memory access modes, .text is read-only.
Move hpsram_mask to a cached data section to fix PTL.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Rework how flash is initialized in esp32 SoC.
"esp_flash_app_init()" will make sure proper cache handling
will be set in place.i
Fixes#77551
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Generic hook infrastrucutre was added to Zephyr, but NXP MCXC SoCs
were not updated accordingly.
Use generic hook infrastrucutre for MCXC SoCs.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
This patch addresses an issue in the ACE platform power management code
where the HST domain suspend operation was performed after the IMR
context save. This resulted in the power management context being
restored with outdated values upon wake-up from D3 state, leading to a
failure to resume the HST domain correctly.
By moving the `pm_device_runtime_put(INTEL_ADSP_HST_DOMAIN_DEV)` call
before the IMR context save, we ensure that the HST domain is suspended
with the current context, and upon resume, the power management context
has the correct information to restore the HST domain state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
check if two or three I2C instances with same irq are enabled
at same time then enable shared_interrupt handler.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The i.MX95 applications processor features advanced graphics and
video cores, powerful vision and machine learning acceleration,
efficient CPU performance, real-time processing, and advanced
security with the integrated EdgeLock® secure enclave to support
energy-efficient edge computing.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Get console baudrate property from device tree to allow
proper configuration for 26 and 40 Mhz devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
The custom linker script was required because SOF needed
some extra linker sections. Other than that, the custom linker
script was identical to the common architecture script. This
commit removes the custom linker script because:
* keeping the custom linker script in sync with the
common one is troublesome.
* application-specific linker sections shouldn't be
included in the generic soc linker script. Instead,
they should be handled at the application level
(i.e: via cmake commands if additional sections are
needed or via a new, custom linker script if more
changes are needed)
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add condition for KConfig Renesas FSP hal module
Move the DUAL_BANK_MODE from SOC to flash driver KCONFIG
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Fix flexspi xip configuration issue regarding code relocation
due to the order of kconfig defaults being sourced
The flexspi setup was not being relocated to an on chip location
Also remove rt1060 conf file in flash common test which changes the
code relocation location to RAM, just keep as ITCM for all M7 which
as of now all have ITCM from NXP with flexspi.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove all entries that as not being used.
This also update hal to re-enable warning flags
as such as -Wno-unused-variable.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
VPR addresses are platform-dependent, so let's use a common symbol -
CONFIG_NRF_PLATFORM_HALTIUM - to cover both nRF54H and nRF92 series.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
PMIC service should be supported on Application and Radiocore, whereas
DVFS service is currently unsupported.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Booting VPRs requires changing the default value of CONFIG_RV_BOOT_HART.
This must be reverted (back to zero) for a future nRF9230 SoC revision,
which will align more closely with the RISC-V spec.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Production version of the nRF54L15 SoC needs reset reason
to be cleared before going into system off.
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Assembly in power_down() in power_down.S already defines data and
code to be locked in cache when powering down SRAM. Instead of adding
another such location in power.c, move the hpsram_mask[] array into
power_down.S. This fixes hard to debug failures when shutting down
the ADSP.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARC.
Replace soc_early_asm_init_percpu() with platform_reset()
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.
Replace z_arm_platform_init() with platform_reset().
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Include compile of the flash file when FlexSPI_XIP is enabled
even when the FlexSPI driver is not enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
- Update `MAX_IRQ_PER_AGGREGATOR` to 1024 to match with the
devicetree
- Update `2ND_LEVEL_INTERRUPT_BITS` to 11 bits to
be able to encode the L2 IRQs.
- Update `NUM_IRQS` to 1036 (L1 has 12, L2 has 1024)
Update the `MAX_IRQ_PER_AGGREGATOR` config in testcase
accordingly, so that it won't overflow the configured bits.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
In order to get all data from STMESP written to ETR and processed
on time we need to write dummy data before sleep.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add functions for local domain suspend to RAM. Add matching resume
procedure. Add pm_s2ram function for determining source of reset.
Add preserving NVIC and MPU state in retained RAM when CPU is powered off
during S2RAM procedure.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Rather setting the driver default in soc, make it directly at symbol
level rather than soc and clean up redundant `select` occurrences.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
CLOCK_CONTROL subsystem is expected to be enabled systematically on all
STM32 devices.
Make it a series default.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Use the correct define for checking if the DCDC converter shall be
enabled.
This resolves the opposite behavior where boards that enable the DCDC
converter uses the LDO and boards where LDO is used they enable the
DCDC.
Fixes: e189fb0720 ("soc: nordic: nrf52: add support for DT-based
regulators config")
Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Add custom clock_control API for nRF platforms that allows requesting
clocks with specified minimal required attributes (accuracy, precision,
and frequency). Provide an implementation of this API for FLL16M, HFXO,
HSFLL, and LFCLK controllers in the nRF54H20 SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This commit introduces a new Kconfig option `CONFIG_SRAM_RETENTION_MODE`
that allows the configuration of SRAM retention mode during the
initialization phase of the firmware boot-up process. By default, the
retention mode is enabled to maintain the existing behavior. However,
this option provides the flexibility to disable the retention mode if
needed, without modifying the Zephyr codebase.
The SRAM initialization functions `hp_sram_init` and `lp_sram_init` in
`sram.c` have been updated to conditionally set the retention mode based
on the value of this Kconfig option.
Additionally, an unused macro `DELAY_COUNT` has been removed from
`sram.c` to clean up the code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
