Improve the radio off code, mainly:
- Compile the file only if necessary, ie, LORA radio not in use
- Use pin information from DT, so that we do not need to hardcode pins
and can switch to dt-spec APIs.
- Improve error handling, includes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Although existing nRF SoCs have only one I2S instance, the nrfx_i2s
driver has now multi-instance API and the related nrfx configuration
symbols need to be used appropriately.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Ensure code cache is enabled at boot for RT11xx. CMSIS SystemInit should
enable the code cache, but if CONFIG_INIT_ARCH_HW_AT_BOOT=y and
CONFIG_CACHE_MANAGEMENT=y, then the cache will be disabled after
SystemInit is called. Since calling SCB_EnableICache will not
change hardware settings if the ICACHE is already enabled, just
call it unconditionally during init.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
For certain combinations of configuration parameters,
z_arm_init_arch_hw_at_boot() disables the instruction cache. Make sure
to re-enable it if required.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
Do not use XTENSA_HAL when building with xt-clang, instead use the HAL
that is provided by the toolchain, similarly to xt-xcc.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Clearing of shared memory by one side of the communication
is no longer required after
commit 0620cb1fe1
("ipc: ipc_service: icmsg: Increase reliability of bonding")
was merged.
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This patch moves cache flush/invalidation to section executed only when
IMR context saving is enabled. If this option is disabled no FW context
is stored so any lost data doesn't matter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Masking out all interrupt during power state transition and restoring
them after is now common thing for all power states. No need to
duplicate code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing primary core context save/restore flow for purpose of secondary
core D0 -> D3 -> D0 transitions. If core is re-enabled we use
dsp_restore_vector as the FW entry point.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is preparing cpu context save and restore code so it can be
later used by the multiple cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch replace temporary stack of the restore vector with interrupt
stack to reduce memory usage. Additionally we can assign seprate stack
for each core. This will allow to reuse this vector for secondary cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Build of Intel cAVS2.5 platforms fails due to undefined reference
sys_cache_data_flush_and_invd_all(). Fix this by adding missing
header include to bring in the inline definition for this function.
Fixes: 6388f5f106 ("xtensa: use sys_cache API instead of custom interfaces")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Move additional cache code related to architecture support into arch.h
and leave cache.h with cache API implementation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Disable the hardware I2C target detection on the IT82xx2 SoC family.
Note: The register setting of I2C target detection is different in
IT81XX2 and IT82XX2 SOC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
It is enabled by default if Device Tree includes a flash controller,
and disabled otherwise. SoC defconfig should not touch it.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The mps3 soc is missing PMU defines required for CMSIS. This
adds the defines __PMU_PRESENT and __PMU_NUM_EVENTCNT
enabling the api for the PMU.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Move STM32H7_DUAL_CORE to
soc/arm/st_stm32/stm32h7/Kconfig.soc
add select STM32H7_DUAL_CORE for SOC_STM32H745XX/H747XX
Cleanup old occurences where was set to y
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This new Kconfig option lets the developer configure if the Cortex M4
core should be force-booted during M7 init independent of the BCM4
option byte.
This allows to disable this default behaviour via Kconfig which was not
possible so far.
Signed-off-by: Jan Krautmacher <jan@krautmacher.org>
Deprecates setting GPREGRET to the reset reason as this has been
replaced with the boot mode retention subsystem for nRF51/nRF52.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Secure Element's mailbox is needed for entropy gathering purposes.
Enable it in the EFR32MG24 SoC series Kconfig.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
use helper macros from csr.h instead of inline assembly which results
in cleaner and more maintainable code
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
To enable IMR on LNL platform new header added to
support context save/restore must be added also to LNL.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit adds the SiLabs Bluetooth HCI driver. It also enables this
BLE HCI driver on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
HAL API changes in ethernet and pwm
SoC RT595 power management code change
west.yml update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This prevents configuration errors if a board is configured when
the SoC indicates segger RTT support but the segger module is
not available.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This adds some structs for interrupt stack frames to make it
easier to access individual elements, and ultimately getting
rid of magic array element numbers in the code. Hopefully,
this would aid in debugging where you can view the whole
struct in debugger.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Introduce config for all ESP32 chips which
may be using different architectures but
shares common peripherals and features.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit adds a missing `__weak` symbol to the `pm_policy_next_state`
function.
This is needed for e.g. `tests/kernel/profiling/profiling_api` to build
correctly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit creates identity mappings for all memory regions required
by SOF. This is needed because drivers using these memory regions have
not yet been ported to Zephyr.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since SOF uses some extra sections we need to add them to the linker
script. The used linker script is simply a copy of arm64 linker script
with SOF regions included. This is because conditionally adding sections
to the main arm64 linker script is not really desirable.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
1. Increase sram to 256KB.
A block sram of SCAR0~15 is 4KB.
A block sram of SCAR16~19 is 16KB.
A block sram of SCAR20~23 is 32KB.
2. Removed the register of RVILMCR which has no effect.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
