Commit graph

5973 commits

Author SHA1 Message Date
Tim Lin
491e3e6477 ITE: drivers/gpio: Add gpio_ite_it8xxx2_v2 driver
This driver is made for it82xx2 series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Tim Lin
7f3d61c608 ITE: dts: it8xxx2: Add the option of 512k flash size
Add the option of 512k flash size.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Tim Lin
051bd7098a ITE: dts: it82xx2: Add pinctrl node and kscan's pinctrl
Add the pinctrl node that has been remapped in the chip of it82xx2.
And modify kscan's pinctrl for the it82xx2.
And swap I2C default pins.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Tim Lin
e1ae5c02cb ITE: dts: it82xx2: Add GPIO general control node in it82xx2.dtsi
Add the GPIO general control node that has been remapped in the
chip of it82xx2.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Ruibin Chang
3fb097c1ff ITE: it82xx2.dtsi: add watchdog device node
With this change, it82xx2 series can use the same
watchdog driver as it81xx2 series.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2023-04-19 03:48:38 -04:00
Ruibin Chang
b9a7340ded ITE drivers/interrupt_controller: add intc_ite_it8xxx2_v2 driver
This driver is made for it82xx2 series.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2023-04-19 03:48:38 -04:00
Tim Lin
44250a9e67 ITE: soc: it8xxx2: Add it82302 and it82202 chip configuration
Add the chip configuration for it82302 and it82202.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-04-19 03:48:38 -04:00
Andrzej Głąbek
2a4373ce0d soc: nordic_nrf: nrf91: Add support for nRF9161 SiP / nRF9120 SoC
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-04-17 09:30:12 -07:00
Andrzej Głąbek
d05a95e5c1 soc: nordic_nrf: nrf52: Clean up option dependencies in Kconfig.soc
Use one common `if SOC_SERIES_NRF52X` instead of `depends on` for
each particular SoC option.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-04-17 09:30:12 -07:00
Andrzej Głąbek
399fa64e7e soc: nordic_nrf: Remove unnecessary inclusions
This is a follow-up to commit 4be102f8e05a9fa12290d8209a8cb38569265478.

Inclusion of `<system_nrf*.>` from `soc.c` files is no longer needed
since `SystemInit()` is not called from those files.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-04-17 09:30:12 -07:00
Jaska Uimonen
bdffde3695 soc: xtensa: intel_adsp: do power off only with custom pm policy
The power off sequence in cavs is meant to be used only by custom pm
policy handler thus guard it with proper ifdefs.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-04-17 15:12:24 +02:00
Maxime Vincent
006f16de25 USB: NXP LPC55S16 USB-HS support
This adds USB-HS support for LPC55S16, much in the same way that
LPC55S28 support was added previously.

Signed-off-by: Maxime Vincent <maxime@veemax.be>
2023-04-13 10:28:00 -05:00
Alberto Escolar Piedras
659e2292a5 soc_inf: Refactor native tasks into own header
The native_tasks definition was directly in the soc_inf soc.h
header. But soc.h pulls a lot of other headers.
Some of those could cause conflicts, say with application
headers, for users who only wanted the be able to register
native tasks in a module.

Let's refactor the native tasks definitions into their own header
and include that header from soc_inf's soc.h.
In this way users who need only need to register a native tasks
can just include posix_native_tasks.h, and all previous users
see no change.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-04-13 13:35:20 +02:00
Gerard Marull-Paretas
4863c5f05b sys/util: extend usage of DIV_ROUND_UP
Many areas of Zephyr divide and round up without using the DIV_ROUND_UP
macro. Make use of it, so that we make use of a tested system macro and
at the same time we make code more readable.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 16:42:29 +02:00
Gerard Marull-Paretas
a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Franciszek Zdobylak
fe9d6d5737 soc: riscv: sifive: fu740: add DDR clk
Add code that initializes DDR clk alongside other clocks.

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
2023-04-12 13:05:55 +02:00
Thomas Stranger
053697cd5f soc: arm: rpi_pico: use aarch32 common nmi init definitions
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2023-04-12 08:59:36 +02:00
Thomas Stranger
f1263f5868 soc: arm: nordic_nrf: use aarch32 common nmi init definitions
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2023-04-12 08:59:36 +02:00
Nikodem Kastelik
d5f83d2a7f soc: nordic_nrf: nrf53: remove startup part of anomaly 160 workaround
Initialization part of this anomaly is now handled internally
by the startup code provided by the MDK.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2023-04-11 14:39:59 +02:00
Gerard Marull-Paretas
0ebe14beb4 sys: util: migrate all files to DIV_ROUND_UP
ceiling_fraction is deprecated, use DIV_ROUND_UP.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-11 12:00:37 +02:00
Gerard Marull-Paretas
1f14506c37 soc: arm: aspeed: remove unused DIV_ROUND_UP
Helper macro is not used, so delete it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-11 12:00:37 +02:00
Marc Herbert
fad2da39aa intel_adsp: move west sign from west flash to earlier west build
Invoking `west sign` in `west build` accelerates twister because `west
build` is run in parallel, see rationale in superseded and very
different (CMake-based) PR #52942.

To maximize backwards compatibility:
- `west sign` is optional in `west build`
- `west flash` will sign (again) if any rimage --option is passed

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-04-10 22:04:47 -04:00
Lucas Tamborrino
fcd9234111 soc: xtensa: esp32s3: Add FPU support
Enable FPU on esp32s3

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-04-08 12:34:25 +02:00
scott worley
cfcd92b893 soc: mec172x: Fix interrupt unmasking in SoC PM restore path
Zephyr PM expects the SoC layer upon wake to unmask interrupts
the PM layer masked. MEC172x was re-enabling interrupt globally
in the Cortex-M4 but not clearing the mask set by Zephyr PM.
This worked in previous Zephyr releases but broke in the latest
Zephyr changes. Fixed the SoC to re-enable interrupts globally
and call irq_unlock(0) as Zephyr PM does if pm_state_exit_post_ops
is not implemented. Tested on MEC172x EVB with PLL clock out pin
enabled and verified PLL goes off in deep sleep, system wakes,
and interrupts are firing.

Signed-off-by: scott worley <scott.worley@microchip.com>
2023-04-07 13:38:56 +02:00
Pawel Czarnecki
91bea1f93b soc: efr32bg2: Kconfig: enable UART interrupt API when PM is used
Power Management works correctly with interrupt API of the UART driver

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2023-04-07 13:33:28 +02:00
Filip Kokosinski
c939d6a473 soc/arm/silabs_exx32/common: support power management for EFR32BG
This commit introduces power management support for EFR32BG SoCs.

Tested on the efr32bg_sltb010a board.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-04-07 13:33:28 +02:00
Rodrigo Cataldo
a25996a661 soc: arm64: qemu: bump highest IRQ when ITS is enabled
The purpose of the GIC ITS is to translate message-passing interrupts into
LPIs. The LPI range starts at value 8192, which means the current default
value (200) is too low. Therefore, bump the highest IRQ number when ITS
is enabled.

Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2023-04-07 13:26:01 +02:00
Ionut Catalin Pavel
f450153c64 soc: arm: atmel_sam0: improved samd20/samd21/samr21 clocking mechanism
There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.

Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).

Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.

Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.

Mostly insipred by the SAML21 implementation.

Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
2023-04-07 13:21:44 +02:00
Mahesh Mahadevan
174824f1cb drivers: gpio: Update NXP GPIO driver for the updated IP Block
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2023-04-06 14:14:11 -05:00
Anas Nashif
c71b71a662 soc: intel_adsp: simplify for only cavs25
Remove conditional code now that we only support CAVS25.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Anas Nashif
98e3699cf7 soc: remove intel_adsp_cavs20
Remove SoC definition for cavs20.
Support for this platform was removed in SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Anas Nashif
683a9d90ab soc: remove intel_adsp_cavs18
Remove SoC for cavs18.
Support for this platform was removed in SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Anas Nashif
d2cf740e68 soc: remove intel_adsp_cavs15
Remove SoC for cavs15.
Support for this platform was removed in SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-06 18:51:56 +02:00
Jerzy Kasenberg
884d7ea706 drivers: clock_control: smartbond: initial support
This commit adds basic support for the clock controller used in
SmartBond MCUs.

Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
2023-04-05 15:09:04 +02:00
Pieter De Gendt
6b532ff43e treewide: Update clock control API usage
Replace all (clock_control_subsys_t *) casts with (clock_control_subsys_t)

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-04-05 10:55:46 +02:00
Scott Worley
5a6cf526ef soc: mec172x: Add hardware debug configuration
Add configuration items to select various ARM debug options
such as SWD only, SWD plus SWV, or SWD plus ETM. The default
is SWD only.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2023-04-04 16:46:07 -04:00
Andrei Emeltchenko
c6b3f009ff boards: rpl_crb: Indicate support for SMBus
Indicate support for SMBus in the board documentation and yaml file.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-04-04 08:15:00 -04:00
Andrei Emeltchenko
42e9751fcf boards: ehl_crb: Indicate support for SMBus
Indicate support for SMBus in the board documentation and yaml file.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2023-04-04 08:15:00 -04:00
Mateusz Sierszulski
7e2852fe95 boards: Add support for SiLabs efr32xg24_dk2601b board
This commit adds support for Silicon Labs efr32xg24_dk2601b board.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2023-04-04 13:34:45 +02:00
Mateusz Sierszulski
7f40908e9d soc: silabs_exx32: Add support for SiLabs efr32mg24 SoC
This commit adds support for Silicon Labs EFR32MG24 SoC.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2023-04-04 13:34:45 +02:00
Jaroslaw Stelter
872907f42c intel_adsp: ace20_lnl: Enable PM on LNL platform
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-04-03 15:17:21 +02:00
Jaroslaw Stelter
55caa18f3e intel_adsp: ace20_lnl: Update power and status registers
PWRCTL and PWRSTS registers for ACE 2.0 must be updated.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-04-03 15:17:21 +02:00
Jaroslaw Stelter
feee9405b2 intel_adsp: ace20_lnl: dts: add L3 memory definitions macros
Add helper macros for l3 memory definitions from
the Device Tree

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2023-04-03 15:17:21 +02:00
Flavio Ceolin
bfcef7da8c intel_adsp: ace20_lnl: Add L3 region definition
Add L3_MEM* definitions to adsp_memory.h

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-04-03 15:17:21 +02:00
Jaroslaw Stelter
e2881fe61a intel_adsp: ace20_lnl: add soc definitions for LNL platform.
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-03 15:17:21 +02:00
Declan Snyder
8adc90dfbc soc: infineon_cat1: Fix failing boards
Fix some issues with builds related to ROM START offset

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-03-30 18:19:32 -04:00
Anisetti Avinash Krishna
acef57e350 dts: x86: intel: raptor_lake: Added UART instances
Added UART instances and changes to enabled
support for PCIe UART instances.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-30 09:43:29 -04:00
Adrian Warecki
ea405eb49e drivers: wdt: Add wdt_intel_adsp driver
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.

The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:

1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.

2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.

3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-03-29 09:45:49 -04:00
Manuel Argüelles
83613baf4a soc: fvp_aemv8r_aarch32: enable caches at init
Enable at SoC boot time when enabled through Kconfig. Cache management
API is not used since it could be built without its support enabled.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-03-29 09:03:37 +02:00
Manuel Argüelles
35e1f3564d soc: fvp_aemv8r_aarch32: fix MPU region gap for nocache
When CONFIG_NOCACHE_MEMORY=y, the .nocache section is placed in between
__rodata_region_end and _app_smem_start/__kernel_ram_start. Make sure
this region is covered by the MPU background region so that the static
region for nocache is configured correctly.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-03-29 09:03:37 +02:00