Adds support for settings/getting RTC time and using alarm/update feature.
The alarm option needs all fields to be set due to a hardware limitation.
RTC shares the same interrupt with the watchdog. Thus shared
interrupts must be enabled when WDT and RTC both need to trigger the ISR.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Prevent `warning: orphan section `.note.GNU-stack'` when building using
`west build -b xt-sim samples/hello_world`
Signed-off-by: William Tambe <williamt@cadence.com>
The ringbuffer availability check is subject to race with regards to
update of BF (Buffer Full) and BNE (Buffer Not Empty) bits in DGCS
register, and status of RP (Read Position) and WP (Write Position).
Following sequence is observed without this patch when
calling dma_get_status() on multiple Intel ADSP platforms:
iter 154 pending 1536 RP 768 WP 768, BNE 1, BF 1
-> dma_reload for 384
iter 155 pending 1536 RP 1152 WP 1152, BNE 1, BF 1
-> dma_reload for 384
iter 156 pending 0 RP 0 WP 0, BNE 1, BF 0
Value of pending is not expected to go from 1536 to zero if only 384
bytes have been consumed via dma_reload() since last call to
dma_get_status().
Change the logic to read DGCS register later, after the WP and RP have
been already read, and only check the BNE bit if Read and Write
Positions are equal.
Link: https://github.com/thesofproject/sof/issues/9418
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Co-developed-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Xtensa toolchains also contain a profile for sample_controller.
So if compiling for it, skip the Xtensa HAL module in Zephyr
tree so the toolchain can use the one included in the toolchain.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
So far 10 kHz tick rate was used but it has 2 drawbacks:
- kernel timer precision is limited to 100 us which is worse compared
to 30 us on platforms which use RTC (which had 32768 Hz tick rate)
- GRTC has 1 MHz frequency so tick rate requires dividing by 100 during
timeout calculation. When 31250 Hz is used (which is 1000000 / 32)
then dividing can be done with bit shifting and it is faster (> 2 times
faster on Cortex-M33 and >8 times faster on VPR - RISCV).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
With ACE2/3 the HDA DMA includes registers to read the Linear Link
Position.
Previous platforms (CAVS, ACE1) was able to report the LLP for GPDMA. Since
ACE2 all links are handled with HD-DMA, hence the new register has been
added for the firmware to report the LLP to the host.
Set the total_copied to 0 for older ACE1/CAVS platforms and in case of
host DMA on ACE2/3 since the informatiojn is not available.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add nrf5x binding header, as NRF5X_REG_MODE_DCDC is used in a macro
comparison. Missing header prevented evaluation to become true and so
enable DC/DC module.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The way ESP32 XIP works (with MMU and cache) does no fit the way Zephyr XIP
is implemented, causing issues related to included Zephyr linker files.
Flash code still resides in flash for execution, but MMU/Cache handles it
in such way that XIP might not (or should not) be used with current Zephyr
approach. To address this problem, XIP configuration option is being
removed from Espressif targets.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
RT1011 expects it's flash configuration block at a different offset than
the rest of the RT10xx series. Add default to fix the platform not
booting.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add clock config for Flexcomm peripherals functioning as I2S interfaces.
Add MCLK clock config for the WM8904 codec located on the mimxrt595_evk
and mimxrt685_evk boards.
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Enable DMIC clock in soc.c - attach to chip's audio PLL. Add pinmux
definitions for the DMIC peripheral. Add nodes to SoC's device tree for
the DMIC peripheral and its audio channels. Configure the DMIC
peripheral in board's device tree to enable audio capture.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Currently, if the user wants to allocate heap on external RAM
he needs to enable CONFIG_ESP_SPIRAM and set a threshold defined
with CONFIG_ESP_HEAP_MIN_EXTRAM_THRESHOLD.
This approach requires that we re-implement `k_malloc` and allocate
the memory on the proper region based on the block size.
By using the shared multi heap feature the proccess of allocating
memory from external memory becomes more fluent and simple.
The attribute SMH_REG_ATTR_EXTERNAL was added to reference the
external memory.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Follow ARM architecture recommendations:
* Use Data Synchronization Barrier (DSB) instruction before WFI,
to ensure that pending memory transactions complete before
changing state.
* To guarantee pend interrupts are recognized before subsequent
operation, use ISB after CPSIE (__irq_enable)
This prevents sporadicy delayed ISRs due to continous MEC172x
entering/exiting deep sleep.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
dts: arm: nxp: mimxrt1180_evk: add GPT1/2 instance into devicetree
Enable GPT1/2 clock
Add GPT1/GPT2 instances
Set GPT2 as a counter, the default frequency is 240000000
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This is the bare minimum and includes the SoC, pinctrl, flash and
devicetree.
I had to include the flash driver that early because I couldn't make
Zephyr compile without flash driver nodes in the device tree.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set()
for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate
support for the smclicshv extenion and riscv_clic_irq_vector_set().
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
FCB was being relocated to the wrong location, and the flexspi clock
setup was not being relocated.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add slot type for debug-stream transport over a debug window slot. For
details see src/debug/debug_stream/debug_stream_slot.h under SOF
sources [1].
[1] https://github.com/thesofproject/sof
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
ESP32 SoC has multiple revisions, some of which are not supported
by the current implementation, as such as REV0 and REV1. This PR
adds an option to indicate user that this is not recommended and not
supported.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
IMXRT11XX secondary core should not deinit ENET PLL
as it could be configured by primary core.
Signed-off-by: Anders Bjørn Nedergaard <abn@polytech.com>
The nRF9280 is a SiP (System-in-Package) consisting of the nRF9230 SoC
and additional components such as PMIC and others. Additionally,
the nRF9230 contains several CPUs, similarly to the nRF54h20 SoC.
Update nrfx glue, and add necessary Kconfig and initialization code
to allow building for nRF9280 targets: CPU, Radio and PPR cores.
The nRF9280 is used for all user build targets and Kconfigs,
whereas the nRF9230 is used as the build target for the MDK.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
Move mpu_region.c to common folder, to re-use with nRF92.
Rename it to nrf54hx_nrf92x_mpu_regions.c to indicate
which product series it applies to.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
