MCXL25x cpu1 (cm0) core build is not supported.
Move aon_peripherals to separate dtsi file to allow loading it
independently from main domain peripherals. Move cpu1 definition
to cm0 specific files. Add aon_sram range for cm33 core.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add DTS support for the two mikroBUS connectors on the sama7g54-ek board.
This adds:
- mikroBUS 1 and mikroBUS 2 header mappings
- board wiring for the shared mikroBUS I2C and SPI interfaces
- board aliases for mikroBUS header, I2C, and SPI use
Tested with:
- MIKROE ETH Click
- MIKROE Weather Click
- MIKROE Ambient 2 Click
Signed-off-by: Balaji Vasudevan <balaji.vasudevan@microchip.com>
Add supports for XIAO ESP32C5, a compact development board based on the
ESP32-C5 SoC.
Assisted-by: Cursor:composer-2
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
- Add header for clock defintions used by the devicetree.
- Add clock node.
- In soc.c, parse clock node config from the devicetree and apply them.
Signed-off-by: Scott Laboe <scottyl2.718@gmail.com>
- Initial implementation for the numaker watchdog timer peripheral.
- Add binding to the m48x series soc.
Signed-off-by: Scott Laboe <scottyl2.718@gmail.com>
Add a die temperature sensor driver for Bouffalo Lab SoCs using
the internal TSEN peripheral integrated into the GPADC.
The driver uses the ADC subsystem for hardware initialization and
raw sample acquisition via adc_bflb_tsen_read_phase(). Temperature
is computed from two ADC measurement phases (TSVBE_LOW toggle)
using the formula: temp = (|v0 - v1| - tsen_offset) / 7.753
The TSEN calibration offset is read from efuse when available,
falling back to the default value of 2042.
Includes:
- Sensor driver at drivers/sensor/bflb/bflb_tsen/
- DT binding for compatible "bflb,tsen"
- TSEN nodes (disabled) in bl60x, bl61x, bl70x, bl70xl dtsi files
Tested on BL602, BL616, BL706, and BL704L hardware.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add soc-nv-flash child nodes to the six NXP FlexSPI boards
not yet converted: mimxrt595_evk, mimxrt685_evk, vmu_rt1170
(mx25um51345g), and mimxrt1050_evk, mimxrt1060_evk,
mimxrt1062_fmurt6 (hyperflash).
Update FlexSPI NOR and HyperFlash drivers to read
write_block_size from the soc-nv-flash node. Remove
soc-nv-flash.yaml from hyperflash and mx25um51345g
bindings.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Add QDEC driver support for Realtek Bee series SoCs,
including RTL87x2G (AON QDEC) and RTL8752H (Basic QDEC).
This driver supports:
- X, Y, and Z axis count reading
- Hardware interrupt-based event trigger
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
The SAM0 SPI driver previously supported DMA only for asynchronous
operations, which required higher-level drivers needing blocking DMA
transfers to implement workarounds. This patch extends DMA support
to the synchronous transfer path, enabling efficient blocking SPI
transactions without driver-specific hacks.
With this change, both synchronous and asynchronous SPI operations
can leverage DMA for improved performance and reduced CPU overhead.
Signed-off-by: Ramya T <ramya.t@microchip.com>
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Add usbhs instance to kit_pse84_eval dtsi files. This
device has one usb block, but due to it being a multi-core
trustzone-capable device we have a couple addresses (s & ns)
and two sets of interrupts (cm33 & cm55).
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
This commit adds a new binding for using Infineon USB. This builds
off the existing Synopsys Designware USB 2.0 binding
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Add devicetree node support for AES ( Advanced Encryption Standard )
node for TI MSPM0.
Signed-off-by: Girinandha Manivelpandiyan <girinandha@linumiz.com>
Align node unit addresses with the first cell of their reg property
per devicetree spec:
- imx943 m7_0/m7_1 irqsteer_master10..12: reg values 10/11/12 are
decimal master indices (0xa/0xb/0xc), so unit addresses become
@a/@b/@c.
- imx94x i2s2/i2s3/i2s4: reg base is 0x4265_0000/0x4266_0000/
0x4267_0000; unit addresses were missing a digit.
- rt5xx smartdma: reg base is 0x27000; unit address was @27020.
Reported by the unit address check from issue #107642.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
SAI3 uses 2 sdma channels for TX and RX and expects
clocking to already be enabled by the AP side (Linux).
On the FW side we inform the SAI driver about the MCLK
rate via a fixed-clock which must match the rate set
by the Linux kernel.
In the future clocking must be handled by Zephyr and
decouple it from Linux.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Switch all Espressif partition layouts from the deprecated
fixed-partitions binding to the new zephyr,mapped-partition
binding introduced in the Zephyr 4.4 migration. Update the
flash-controller and flash0 nodes to declare the ranges and
address/size cells required by the new binding so partition
offsets resolve correctly through the node hierarchy.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The TM1637 support up to 6 digits display hardware, the driver needs to
read the digits count from device tree in order to function correct.
Hence, this adding a new property mark as required with enum [1 to 6].
Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk>
Co-authored-by: Marcin Niestroj <m.niestroj@emb.dev>
--
Apply suggestion from @mniestroj
Update tests/drivers/build_all/auxdisplay/gpio_devices.overlay
to fix twister tests.
This property configures the Network Processor (NWP) QSPI clock
to 80 MHz instead of 40 MHz. While this is intended to enhance
performance, it introduces instability. Therefore, it is being
removed until the NWP firmware can properly support it.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Add board definition for the Sipeed M0Sense, a compact development
board based on the BL702SA0Q2I (QFN32) with USB-C, RGB LED, user
button, and castellated pads. Console is via USB CDC-ACM.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add devicetree support for AMD ACP 7.0 audio DSP:
- SoC dtsi with host DMA, SoundWire DMA, and 12 SDW DAI nodes
- Board-level DTS for acp_7_0_adsp
- YAML bindings for amd,acp-host-dma, amd,acp-sdw-dma,
and amd,acp-sdw-dai compatible strings
Signed-off-by: Siva Subramanian Ravi Saravanan <sravisar@amd.com>
Add support for configuring the LPTMR as a wakeup source by integrating
with the WUC (Wakeup Controller) subsystem.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The mec5 symcr and rom_api nodes were mistakenly placed under
the espi node. Both represent SoC-level register blocks and
are not part of the eSPI peripheral. Move them under the soc
node to reflect the correct hardware hierarchy.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add devicetree binding for software-defined PWM
using a hardware timer interrupt time base.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: Stefan Gloor <stefan.gloor@siemens.com>
Add a comprehensive driver for the Microchip PAC194x/195x family of
multi-channel power monitors. This driver supports VBUS, VSENSE,
and power accumulation measurements.
Key features and implementation details:
- Support for PAC1941/42/43/44 (9V FSR) and PAC1951/52/53/54 (32V FSR).
- Efficient I2C handling: uses per-channel burst reads to optimize
bus bandwidth based on enabled channels.
- Flexible Refresh Modes: introduced SENSOR_ATTR_REFRESH_MODE to
allow users to choose between AUTO_WAIT (synchronous),
AUTO_NOWAIT (asynchronous/latched), and MANUAL modes.
- Broadcast Support: added a force refresh command using I2C
General Call (0x00) to synchronize snapshots across multiple
sensors (up to 16 instances) simultaneously.
- Configurable range: support for Unipolar, Bipolar, and Bipolar
Half FSR modes via Devicetree.
Tested on RISC-V (ESP32-C3) with 16 PAC1944 instances.
Signed-off-by: Wojciech Macek <wmacek@google.com>
Rename BL61x GPIO and pinctrl drivers to bl61x_808 variants since
BL808 shares identical register layouts. Update compatible strings,
Kconfig, CMakeLists, and BL61x device tree accordingly. Extend the
DMA and IR receiver drivers' BL61x guards to also cover BL808.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add device tree source for Bouffalo Labs BL808 SoC with T-Head E907
core, including peripherals (UART, SPI, I2C, GPIO, PWM, WDT, timer,
RTC, DMA, ADC, sec_eng), clock tree, flash controller, and memory
regions (ITCM, OCRAM, WRAM, MM DRAM/VRAM).
Also adds the BL808 clock controller DT binding and clock ID header.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add RTC node to MCX L SoC dtsi. On frdm_mcxl255, initialize the
32 kHz ROSC clock, enable the RTC node.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Add driver for the NXP RTC analog module found on MCX L series
SoCs. This RTC supports BCD time/date mode with hundredths-of-second
resolution and 3 independent alarms.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
A kernel clock is required for ADCs on STM32H5 SoCs. Add a default
kernel clock for ADCs and remove the clock configuration from boards
that use the default clock.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add ranges, #address-cells and #size-cells properties to internal
flash device nodes in ST SoCs DTSI files to ease boards to move to
zephyr,mapped-partition compatible description since use of
fixed-partition compatible description is being deprecated in Zephyr.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add st,stm32-qdec child nodes (disabled) under TIM1-TIM3 for
STM32U0. This is DT coverage only so boards can opt in via overlays.
No functional change.
Fixes#88902
Signed-off-by: Akansh Sinha <akansh.sinha.dev@gmail.com>
