The clock-reference property is marked as required in the bindings file.
Without these changes creating new boards based on stm32u5 either requires
explicitly disabling otghs_phy or setting the clock-reference -property.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
This commit adds eSPI support for npck3, including support for the
maximum frequency of 66MHz. The method to read the level of eSPI reset
pin differs on npck3, so the definition of eSPI_RST has been updated
accordingly.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds new device tree properties and Kconfig options to
distinguish the support in different chip.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
This commit only adds documentation. It will help a user to translate
pinout from the reference manual to a device tree gpio (HP and ULP).
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Update compatibility from "silabs,gecko-iadc" to "silabs,iadc". It
allows to use the new driver which are more custom to series 2 boards.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Warning:
unit address and first address in 'reg' (0x4cce0000) don't match
for /soc/netc-blk-ctrl@4cde0000/ethernet/mdio@4cb00000
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The `ok` state is deprecated and very few files are using this.
The DTS spec also does not have this value.
This PR removes this value once and for all.
Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
This change introduces stm32l5xx clock definitions and separates
it from L4xx series. This change comes because of CCIPR missmatch
of SAI between L4xx and L5xx series.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add Clock Control nodes to Renesas RZ/A3UL, V2L devicetree
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add Clock Control driver support for Renesas RZ/A3UL, V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Extract common DTS bindings to zephyr,cellular-modem-device.yaml
as these are referred in the modem_cellular.c in the
MODEM_CELLULAR_DEFINE_INSTANCE() macro.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Add support for the UltraChip UC8151D e-paper display (EPD) controller.
The UC8151D is part of the UC81xx family of display controllers commonly
used in e-ink displays.
This implementation extends the existing UC81xx driver infrastructure by
adding device tree bindings, Kconfig options, and the necessary driver
code to support the UC8151D variant.
Signed-off-by: Marc Espuña <mespuna@cactusiot.com>
Add HCI info and BLE interrupt.
Lower peripheral interrupt prio to make sure
LL irq have the highest one.
This is a prerequisite of the system.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
This is a SOC based on AE350. In addition to the core, some
modifications have been made to the peripheral functions,
including the integration of built-in USB.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32U5
DTSI files. Nodes are disabled by default; boards can enable encoder
mode via overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32L5
DTSI files. Nodes are disabled by default so boards can enable encoder
mode via overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32L4
DTSI files. Boards can enable them in overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32L1
DTSI files. Boards can enable them in overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child node (disabled) under TIM nodes in STM32L0
DTSI files. Boards can enable it in overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32H7
DTSI files. Nodes are disabled by default; boards may enable them via
overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32G4
DTSI files. Nodes are disabled by default; boards may enable them via
overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32G0
DTSI files. Boards can enable them in overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in STM32F7
DTSI files. Nodes are disabled by default; boards may enable them via
overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child node (disabled) under TIM nodes in STM32F3
DTSI files. Boards can enable the node via overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Add st,stm32-qdec child nodes (disabled) under TIM nodes in the
STM32F1 DTSI files. Boards can enable encoder/decoder functionality
using overlays. No functional change.
Signed-off-by: Ritesh Kudkelwar <ritesh.kumar0793@gmail.com>
Added driver and bindings for the coresight nrf submodule.
add integrated it for the nrf54h20.
The coresight subsystem is a combination of ARM Coresight peripherals
that get configured together to achieve a simplified configuration based
on a desired operating mode.
This also replaces the previous handling in the nrf54h20 soc.c which was
powering the subsystem up but not configuring it.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Moved the nrf_etr driver from the drive/misc folder into the recently
established driver/debug folder where it is a better fit. Moved the
associated files such as bindings and headers accordingly as well.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Add a devicetree binding and corresponding dt-bindings header for
the ArduCam FFC-40 pin GPIO connector used by camera shields.
- Add dts binding schema for arducam,ffc-40pin-connector
- Add dt-bindings header with GPIO pin definitions
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
This commit introduces shared QSPI partition configurations for Arduino
STM32H7 boards, using the factory partitioning scheme that is compatible
with the Arduino IoT Cloud services.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
