Add SoC and devicetree support for the R-Car Gen4 R8A779G0 A76.
Co-authored-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add the freqme node to the MCXA15x, MCXA34x, MCXA5x, MCXAxx6, MCXN23x,
MCXNx4x and MCXL SoC devicetrees and to the RT700 cm33_cpu0 devicetree, and
enable it on frdm_mcxa153, frdm_mcxa156, frdm_mcxa266, frdm_mcxa344,
frdm_mcxa366, frdm_mcxa577, frdm_mcxn236, mcx_n5xx_evk (MCXN547),
mcx_n9xx_evk (MCXN947), frdm_mcxl255 and mimxrt700_evk (MIMXRT798S) boards.
Each freqme node lists its selectable clocks as "reference-sources" and
"target-sources" child nodes, pairing an INPUTMUX cookie with a frequency
provider: "clocks" for rates clock_control can report (FRO_HF, FRO_12M,
FRO_HF_DIV, CPU_AHB, EXT), or a fixed "clock-frequency" for fixed
oscillators (32 kHz, 16 kHz, FRO1_DIV8, FRO2). External or variable sources
(CLK_IN*, SLOW_CLK, LPOSC, FRO0, GPIO clocks) are listed as target-only
(MEASURE) with no frequency provider. The child marked "default-source" is
the power-on selection.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a clock_monitor back-end for the NXP FREQME (Frequency Measurement)
peripheral, wrapping the MCUX lpc_freqme HAL. It supports MEASURE
(one-shot) and WINDOW (continuous MIN/MAX threshold) modes, queries the
reference rate from clock_control, and enables the peripheral gate through
clock_control. It does not enable the reference or target source clocks -
the application must ensure they are running before configure()/start();
the driver only routes and measures them.
Reference and target clocks are selected from devicetree-declared source
lists ("reference-sources" / "target-sources"); each source pairs an
INPUTMUX route with a frequency provider (a "clocks" phandle or a fixed
"clock-frequency"). clock_monitor_set_source() switches the reference and
the target between the declared sources at runtime and drops the device
back to unconfigured state, so the next configure() re-derives REF_SCALE
and the WINDOW thresholds. Reference sources must resolve a frequency;
target sources may omit one, since the target rate is measured, not
predicted.
This includes the devicetree binding, the INPUTMUX connection-cookie header
with per-family cookies (MCXA, MCXC, MCXN, MCXL, MCXW and RT700) plus the
NXP_FREQME_SOURCE_UNCHANGED sentinel, and the syscon clock identifiers used
to query the FRO / CPU-AHB / external clock rates and to gate FREQME.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a node for the VREFBUF peripheral in the STM32G0. The VREFBUF is
available only on stm32g0X1 variants.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
ke1xz core clock source is lpfll which is 72MHz instead of 48MHz.
ke17z512 core clock is 96MHz with an override in nxp_ke17z512.dtsi.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
Add ext1-pwren-gpios binding to nxp,wifi.yaml for M.2 module VPCIe_3V3
power control. On imx91 (AArch64), GPC is not available so read
WL_WAKE_HOST GPIO directly via wakeup_gpios DT property instead.
Use CONFIG_PM_MCUX_GPC to guard fsl_gpc.h include, which is more
precise than excluding by SoC series.
Signed-off-by: Li Long <li.long@nxp.com>
Add uSDHC3 (Wi-Fi SDIO) and LPUART5 (BLE UART) peripheral nodes to
nxp_mimx9131.dtsi. Add M.2 shield aliases m2_wifi_sdio and m2_hci_bt_uart.
Add IMX_CCM_USDHC3_CLK clock definition for uSDHC3 peripheral.
Signed-off-by: Li Long <li.long@nxp.com>
Add the RTC device tree node for the Xilinx Zynq Ultrascale+ MPSoC. The
RTC is at 0xffa60000 with alarm (SPI 26) and seconds (SPI 27)
interrupts. The node is disabled by default.
Signed-off-by: Harini T <harini.t@amd.com>
This reverts commit f9bed91088.
build error:
Build failure - error: static assertion failed: "cpu0 clock-frequency
does not match HSE * mul"
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds a new DT control `hsi-prediv` for `wch,ch32v20x_30x`
devices and compile-time checks to ensure the clock configuration is valid.
This allows control of the internal clock divisor to be able to reach the
full 144MHz when using the internal clock source (`HSI`).
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
Define the standard `ranges` property in the `base.yaml` binding so that
other bindings can easily set it as `required: true`. The property
follows the pattern of `interrupts-extended`: type `compound` is used to
disable type-checking at DTLib level but the type is validated at EDTLib
level.
Update all bindings which explicitly assigned a type to the property
(and include `base.yaml` - which is all of them) to remove the type
assignment as it would cause build failures.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Include spi-device.yaml in the andestech,qspi-nor binding. The Egis
ET171 QSPI controller acts as an SPI bus, and its flash children must
have a reg property specifying the chip select. Adding this include
declares the reg property and avoids avoid_unnecessary_addr_size and
spi_bus_reg DTC warnings.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Remove unnecessary #address-cells and #size-cells properties from the
kbd and kscan nodes in all mec SoCs. These properties are not needed
because the keyboard controller does not have any memory-mapped child
nodes with reg properties, and their presence triggers an
avoid_unnecessary_addr_size DTC warning.
Also update the microchip,xec-kbd binding to no longer require these
properties.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Remove unnecessary #address-cells and #size-cells properties from the
ite,it8xxx2-pinctrl node. These properties are not needed because the
pin-controller node does not have any memory-mapped child nodes with
reg properties, and their presence triggers an
avoid_unnecessary_addr_size DTC warning.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
This adds support for ARM Corstone System Architecture Specification Ma2
(ARM CRSAS-MA2) System Counter and System Timer.
The HW consists of one 64-byt System Counter, and any number
of System Timers that have match registers to generate interrupts
based on the value of the System Counter.
The timers don't have any counter/timer of their own, meaning that
System Counter can't be started or stopped independently if there is an
enabled System Timer.
Add the crsas-ma2 timer to the test for counters.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Signed-off-by: Krystian Hebel <khebel@antmicro.com>
Add the PCNT signal-map entries for the esp32p4 and the PCNT
pinmux macros in the pinctrl header so PCNT pins can be selected
from devicetree.
Assisted-by: Claude Code:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Some STM32 SAI nodes may expose a shared kernel clock for both sub-blocks,
while others may provide different kernel clocks for sub-block A and
sub-block B.
These changes allow the driver to handle SAI nodes with different kernel
clock layouts. Nodes with sai_ker_ck use a shared kernel clock for both
sub-blocks, while nodes with sai_a_ker_ck and sai_b_ker_ck use
separate kernel clocks for each sub-block.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Modified the Microchip XEC eSPI TAF V2 driver adding support for
MEC174x/5x/165x. We agree with code quality tool analysis the eSPI
TAF register structure is too larger and not maintainable. The driver
now uses Zephyr's system memory mapped register access routines.
quality check tools find the structure too large.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
CK48 is now moved to separate mode.
It is shared by RNG and USB peripherals. This avoids
collision and also allows checking in RNG driver.
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
Convert the BCM2711 auxiliary UART devicetree description to use the
generic NS16550 binding and driver.
Replace the SoC-specific compatible with the new BCM283x auxiliary UART
compatible, add the generic "ns16550" compatible, set the required
reg-shift and clock-frequency properties, and remove the dedicated
binding in favor of including the generic ns16550 binding.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Apply the same pattern used for RP2350's core-supply-regulator to
RP2040: disable vreg by default in rp2040.dtsi and require boards to opt
in explicitly with status = "okay", rather than inheriting an always-on
default.
Every RP2040 board already set regulator-always-on and
regulator-allowed-modes = <REGULATOR_RPI_PICO_MODE_NORMAL> on this node
identically, since it supplies the core logic currently executing the
code and must never be disabled or switched to high-impedance mode. Move
these two properties into the shared vreg node definition in rp2040.dtsi
instead of duplicating them across all 33 boards, leaving each board
override to just enable the node.
Assisted-by: Claude:claude-sonnet5-(1m)
Signed-off-by: Andrew Fantino <fantino@qti.qualcomm.com>
The core-supply-regulator (vreg) node was enabled unconditionally in
the shared rp2350.dtsi, so every board inherited the "okay" status.
However, the core-supply-regulator hardware is shared between both cores
on the RP2350. If enabled unconditionally, it is ambiguous which CPU
initializes the core-supply-regulator in an AMP configuration.
Disable vreg by default in the rp2350.dtsi and have each board that
requires it set its status.
Assisted-by: Claude:claude-sonnet5-(1m)
Signed-off-by: Andrew Fantino <fantino@qti.qualcomm.com>
Add child nodes to the Wi-Fi ROM regions representing the default
entry points for LMAC and UMAC processors when no ROM patch is
applied. Reference these from the WICR node so the firmware patch
addresses are derivable from devicetree.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Having a standard name for this property means we can provide additional
macro helpers to write the boilerplate that comes with hwspinlock drivers.
Signed-off-by: Pierrick Guillaume <pguillaume@fymyte.com>
Add modem driver for Nordic nRF91 series running the
Serial Modem application v2.0.0 or later. This includes the nRF91M1 module.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
The ADXL367 has two independent interrupt output pins, INT1 and INT2.
Add an int2-gpios property so a board that routes only INT2 to the host
can describe the connected pin. When only int1-gpios is present the
existing behavior is preserved; if both are defined, INT1 is prioritized.
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Enable the drivers.pwm.pwm_flexio test case for frdm_mcxa577 using
FlexIO0 D14 (P2_6) as the PWM output channel.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
Enable the full-speed USB device controller on STM32L1:
- Assert PLL VCO = 96 MHz at build time (USB clock = VCO / 2).
- Skip the runtime 48 MHz clock check; the clock is deterministic.
- Drive the DP pull-up via SYSCFG_PMC USB_PU (no disconnect GPIO).
- Add the usb controller node and a nop USB PHY in devicetree.
Signed-off-by: Florian Moesch <florian.moesch@draeger.com>
The provided `ranges` property was performing using an identity mapping,
so it's wiser to replace it with an empty `ranges;` instead.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The PSoC6 flash controller (psoc6_01/02/03/04) declared two enabled
soc-nv-flash children: the main code flash (flash0 @0x10000000) and a
work flash (flash1 @0x14000000). The Infineon flash driver is
single-instance and derives its target from SOC_NV_FLASH_CHILD_NODE(0),
which expands DT_INST_FOREACH_CHILD_STATUS_OKAY over every enabled
soc-nv-flash child. With two enabled children the macro concatenates
both node identifiers and the driver fails to build (invalid token
pasting on the second node's properties).
The work flash has no Zephyr flash-driver consumer, so keep it disabled
by default. This restores a single enabled soc-nv-flash child under the
controller and lets boards that need the work flash enable it explicitly
alongside the required driver support.
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Add support for uc8253 e-paper display driver. This chip shares most
registers layout with uc8151, hence the extension of the uc81xx driver
to also support the uc82xx without changing the filename.
Tested with Waveshare sku22698 e-paper HAT connected to Nucleo f446re
via SPI.
Signed-off-by: Grabowski Łukasz <lukasz.grabowski@pcosa.com.pl>
The VREFBUF output voltage is factory-calibrated by ST. On series such
as STM32H5 or STM32U5, the VREFBUF loads trimming data automatically
when changing voltage scale. However, on series such as STM32WB, the
software is responsible for loading the correct trimming data from OTP.
Implement reading of trimming data from OTP and manual application of
the proper trimming data by software, gated behind a new Kconfig option
for the driver, CONFIG_REGULATOR_STM32_SOFTWARE_TRIM, enabled by default
on series without automatic loading by hardware (these series' DTSI are
updated to provide the `nvmem-cells` property which gates the option).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add NVMEM cells corresponding to VREFBUF trimming values in the DTSI for
STM32WB series to enable consumption through the NVMEM API.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
make the part that is needed for the esp32 to
change the offsets for the mac and base registers
more generic and use the devicetree for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add an I2C driver for the Analog Devices ADXL313 3-axis accelerometer
with classic sensor API support for range and ODR configuration.
Use i2c_reg_update_byte_dt for register read-modify-write, reconfigure
range/ODR in standby, and add build_all coverage plus a release-notes
entry.
Signed-off-by: Leo Li <leo.li@rakwireless.com>
Describe the EMAC PTP reference clock as a second clock on the
esp32p4 Ethernet node so it can be enabled and queried through
the clock control driver.
The rate is resolved from the PTP reference clock source, so
Ethernet PTP support does not need to assume a fixed frequency.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add disabled-by-default ana_cmpr nodes for the SoCs that have this
peripheral: two units on ESP32-P4 (sharing GPIO_PAD_COMP_INTR_SOURCE)
and one unit each on ESP32-C5 (GPIO_EXT_SOURCE) and ESP32-H2
(GPIO_INTR_SOURCE, shared with the GPIO peripheral's own interrupt).
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
Add the devicetree binding for Espressif's analog comparator
(ana_cmpr), present on the ESP32-P4, ESP32-C5, and ESP32-H2 SoCs.
It compares a fixed analog source GPIO pad against either an
internal (VDD-divider) or external GPIO reference voltage, and
reports the crossing as edge events via the generic comparator API.
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
Convert the RV3028 driver from an RTC-only driver into a
multi-function device driver.
The RV3028 provides multiple functional blocks including RTC,
EEPROM, RAM and timestamp functionality. Split the existing
driver into an MFD parent and RTC child driver to allow the
additional features to be supported through their respective
Zephyr subsystems.
The existing RTC functionality remains unchanged.
Signed-off-by: Janez Ugovsek <janez@ugovsek.info>
