The STM32G4 variants g473, g474, g483, g484, g491 and g4a1 do support QSPI
interface. All mentioned variants include the stm32g491.dtsi.
Signed-off-by: Andreas Schmidt <andreas.schmidt@dormakaba.com>
It is now possible to enable CONFIG_UART_INTERRUPT_DRIVEN for mspm0
uart driver.
Signed-off-by: Jackson Farley <j-farley@ti.com>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
The definition of the EM3 energy mode is that software switches
off the LFRCO and LFXO before entering deep sleep. On Series 2,
oscillators are clocked on-demand based on peripheral requests
from hardware. Requesting EM3 will result in EM2 if any active
peripheral uses one of the oscillators, and requesting EM2
will result in EM3 if no peripherals use the oscillators.
In version 2025.6 of the HAL, this was reflected in the API
of the power manager by making EM3 an alias of EM2. Reflect
this in Zephyr by removing the separate EM3 power state.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The current driver has a few limitations:
1. The `ngpios` DT property is fixed at eight.
Since the SN74HC595 and kin are designed to be
easily daisychain-able, the upper bound on `ngpios`
should be limited only by the maximum number of pins
that Zephyr supports per GPIO port, which is 32.
2. In the case of having no control over the shift register's
reset input, the device tree node should accept a default
value to shift into the register(s) during init.
3. There seems to be an assumption that the serial clock
and load clock are tied together. While this is often the
case, the device tree node should be more flexible in
allowing the specification of a separate load clock GPIO pin.
4. The device tree node should also be able to accept a GPIO pin
to drive the enable input pin of the shift register(s).
This commit addresses all of these issues.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
1. Renamed MCXA276 to MCXA266
2. NXP frdm_mcxa276 is renamed to frdm_mcxa266,
add this information to migration-guide-4.3.rst.
Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
1. Renamed MCXA166 to MCXA346.
2. NXP frdm_mcxa166 is renamed to frdm_mcxa346,
add this information to migration-guide-4.3.rst.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The stm32n6 features an RNG block. The RNG is a true NIST SP800-90B
compliant entropy source according to the stm32n657x0 reference manual[1].
Per Table 3 in the reference manual, the RNG peripheral register boundary
address (secure) is 0x54020000 to 0x540203FF. That is, base address
0x54020000 and size 0x400.
Per Table 73 in the reference manual, the RNG peripheral has only a single
rng_clk option (hsis_osc_ck).
Per section 14.10.66 (and more) the RNG peripheral control is performed
through AHB3 using bit 0.
As such, the `clocks` property contains a single phandle to the RCC AHB3
bit 0 entries.
Per Table 135 in the reference manual, the RNG peripheral interrupt is
located at position 40 in the NVIC.
[1] RM0486 Rev 2: https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf
Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
Add support for the SDMMC clock bypass feature for those SoCs that have
it. This provides a SDMMC bus speed double that of `clk-div = <0>`.
Updated the `clk-div` documentation at the same time to be clearer on
how the bus clock speed is determined.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Define SAI1 node for STM32H7xx series.
Add STM32H7xx related DMA configs.
Enable samples/drivers/i2s/output for nucleo_h745zi_q/m7
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add external interrupt support for Renesas RZ/A3UL, V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Change the adc node's compatible of RZ/G3S to renesas,rz-adc-c
Fix ADC node register size for Renesas RZ/G3S
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This patch introduces a new board definition for embedsky’s
TQ‑H503A development board, based on the STM32H503CBT6 SoC.
Tested: successfully built, ran and debug
`hello_world` and `blinky` samples.
Signed-off-by: MA Junyi <mjysci@live.com>
The Egis ET171 SPI controller was based on Andes ATCSPI200,
but has since been modified. In particular, the WrTranCnt and RdTranCnt
fields from the SPI Transfer Control Register have been moved to dedicated
Wr_Tran_Cnt and Rd_Tran_Cnt registers.
Signed-off-by: jacob kung <jacob.kung@egistec.com>
Enable optional storage of sensor attribute values in EEPROM. On reset, the
device goes through a POR sequence that loads the values programmed in the
EEPROM into the respective register map locations.
The driver stores sample frequency, offset, oversampling, lower threshold,
upper threshold, alert pin polarity, alert mode and conversion mode if the
value is continuous or shutdown.
The functionality has been tested with sensor shell and power cycling
sensor:
Test (undocumented) temperature offset is stored:
```shell
uart:~$ sensor attr_set ti_tmp11x@48 ambient_temp offset 0
ti_tmp11x@48 channel=ambient_temp, attr=offset set to value=0
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (25.523436)
uart:~$ sensor attr_set ti_tmp11x@48 ambient_temp offset 50
ti_tmp11x@48 channel=ambient_temp, attr=offset set to value=50
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.617186)
uart:~$
[15:12:20.088] Disconnected
[15:12:36.106] Connected
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.554686)
uart:~$ sensor attr_get ti_tmp11x@48 ambient_temp offset
ti_tmp11x@48(channel=ambient_temp, attr=offset) value=50.000000
```
Test one-shot mode is not stored:
```shell
uart:~$ sensor attr_set ti_tmp11x@48 ambient_temp 18 1
ti_tmp11x@48 channel=ambient_temp, attr=accel_x set to value=1
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.562499)
uart:~$ sensor get ti_tmp11x@48 ambient_temp
Read failed
[00:00:21.332,000] <wrn> sensor_compat: Failed to fetch samples
uart:~$
[15:16:24.529] Disconnected
[15:16:33.540] Connected
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.406249)
uart:~$ sensor get ti_tmp11x@48 ambient_temp
[...] (75.351561)
```
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add PWM driver support for Renesas RZ/A3UL
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
