Add initial support for TI MSPM0 UART with basic poll-in and poll-out
functionality.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Add a GPIO driver support for TI MSPM0 SoC family.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Added a pinctrl driver support for MSPM0 Family.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Remove the closed loop mode implementation for the fll16m clock.
Closed loop causes a hardware bug resulting in increased current
consumption if SoC experiences high, but within spec, temperatures.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add config and overlay to samples for testing stop/standby modes:
- samples/boards/st/power_mgmt/blinky
- samples/boards/st/power_mgmt/wkup_pins
I've measured consumption for each low-power mode:
- stop (regulator in run mode) ~217 uA
- stop (regulator in low-power mode) ~206 uA
- standby mode ~3.5 uA
Low-power mode wakeup timings from the datasheet,
but it barely meets these in reality:
- stop (regulator in run mode) 3.6 us
- stop (regulator in low-power mode) 5.4 us
- standby 50 us
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
The pinctrl register bits need to be restored to GPIO mode
after we exit from certain low power modes. We cannot rely
on the pin function to default to GPIO.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Make the vbus-limit-microamp property of npm1300-charger required and
change its range to reflect the one actually supported by the device.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
This makes SSD1327 use the new L8 display format.
It also fixes all displays that didnt support the undocumented
monochrome mode.
It also adds i2c and revamps the entire driver.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Add support for the RPU, real-time processing unit on Versal Gen 2 SoC.
It is based on Cortext-R52 processor.
The patch contains initial wiring and configuration for generic board
with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global
timer and UART.
versal2.dtsi contains common peripherals integrated into Versal Gen 2
SoC, and versal2_r52.dtsi has peripherals which are private to
Cortex-R52 processor.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
This patch adds support for the STM32L431XB SoC, which is the
128 KB flash / 64 KB SRAM variant of the STM32L4X1 SoC family.
Co-authored-by: Alexander Apostolu <apostolu240@gmail.com>
Signed-off-by: Alexander Apostolu <apostolu240@gmail.com>
Signed-off-by: Mirai SHINJO <oss@mshinjo.com>
Added io-channel-cells to the binding as is standard for
the ads1x1x binding. Additionally, this prevents an issue where
you cannot compile due to the length of this property being
longer than expected.
Signed-off-by: Connor Weekes <cweek24@gmail.com>
This adds a proper, concise, title property to a bunch of bindings for
which the first sentence of their description (which used to be a
makeshift title) was really long
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
A binding documentation shouldn't be referring to "driver", so this
commit reworks the description accordingly, and sets a title now that
binding files can have one.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add wsen_itds_2533020201601 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
SPI driver for Microchip MEC5 HAL based QSPI controller. QSPI
hardware supports full duplex, dual, and quad operation. MEC5
QSPI controller also includes three local DMA channels per
direction to off load firmware. The driver API supports full
or half-duplex. Due to QSPI hardware not supporting one wire
half-duplex, this driver supports full-duplex only. QSPI hardware
design requires it to control chip select and current hardware
supports up to two chip selects. Zephyr's SPI DT macros store the
child SPI device's reg properity as the "slave" member of the SPI
configuration structure. The driver uses the "slave" value as the
chip select. Additional timing settings specific to SPI flash devices
are in a new SPI device YAM file: "microchip,mec5-qspi-device.yaml"
which includes the standard "spi-device.yaml". If the new YAML is not
used, the QSPI controller will use default timing values for chip
select and I/O line taps.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Using pre-defined values displayed on datasheet's table 5-4 for
CMM Update Rates.
Please note that datasheet specifies these Update-Rates may have
up to 7% standard deviation, which may be significant for certain
applications.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
This patch introduces rm3100 magnetometer sensor, with basic
support (only read-decode).
This driver has bus support for I2C.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Align xg29 directory with other Series 2 families, introducing
separate .dtsi files per device family inheriting the common
xg29.dtsi file.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This supports nuvoton numaker m55m1x series soc. Besides, it also
has relevant modifications, including:
1. Fix failure to enable HICR48M, which is to clock usbd and phy
2. Support HWINFO for USB device serial number
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Allow for users to define the fifo-watermark on a per-instance basis
through device-tree properties. This setting is validated at build
time, so missing it when required, or setting an invalid value should
not end up in a run-time errror (as in: it runs but nothing happens).
Signed-off-by: Luis Ubieda <luisf@croxel.com>
This patch fixes previous overriding of ODR setting through DTS (it
would always be 25-Hz, irrespective of what the DTS property said).
While doing so, create dt-binding enum to improve settings clarity.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
The new ace30 files structure is organized as follows:
intel_adsp_ace30.dtsi - main file for all variants
intel_adsp_ace30_ptl.dtsi - additional file for PTL variant
intel_adsp_ace30_wcl.dtsi - additional file for WCL variant
The main ace30.dtsi file contains most of the fields,
with only the differences specified in the ace30_ptl.dtsi
and ace30_wcl.dtsi files.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
