Add a MUX controller backend for the Analog Devices ADGM3121 DPDT MEMS
switch (DC-24GHz). The four switches are modeled as a single control line
whose state is a 4-bit switch bitmask (bit i = SW(i+1), 1 = closed):
mux_control_set() drives all four at once, mux_control_disconnect() opens
them all, and mux_state_get() reads the mask back. Both SPI (adi,adgm3121)
and parallel GPIO (adi,adgm3121-gpio) control modes are supported.
Co-authored-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a generic GPIO-backed mux controller: the selected state value is
binary-encoded LSB-first across the GPIO lines listed in the mux-gpios
property (bit N -> mux-gpios[N]). Useful for board-level analog/digital
muxes that are simply wired to MCU GPIOs.
Single-channel by design, so the binding pins #mux-control-cells = 0
and #mux-state-cells = 1. The driver plugs into the existing mux
subsystem (set / get_state ops) and reuses CONFIG_MUX_INIT_PRIORITY, so
consumers reference it through the generic mux-controls / mux-states
model.
Co-authored-by: Felix Wang <fei.wang_3@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The mux subsystem redefines the "nxp,inputmux" binding as a mux
controller (#mux-control-cells / #mux-state-cells). The SCTimer PWM
capture path still programmed the INPUTMUX directly through the
fsl_inputmux HAL using two parallel "input-channels" /
"inputmux-connections" arrays, so on SoCs that expose the mux
controller node the two models conflicted. Move SCTimer capture onto
the generic mux model:
- nxp,lpc55S3x: add the INPUTMUX mux controller node (disabled by
default) so capture consumers can reference it; enabled per board.
- nxp,sctimer-pwm.yaml: drop the input-channels / inputmux-connections
arrays and include mux-consumer.yaml; the capture routing is now a
single "mux-states" phandle-array carrying <&inputmuxN index
connection>.
- pwm_mcux_sctimer: drop the direct fsl_inputmux HAL calls and apply
the routing through mux_state_apply(), guarded by device_is_ready().
The mux controllers init at priority 40, before PWM at 50, so they
are ready at SCTimer init time.
- Migrate the lpcxpresso55s36 pwm_loopback overlay to the mux-states
syntax and enable the INPUTMUX node.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The mux subsystem redefines the "nxp,inputmux" binding as a mux
controller (#mux-control-cells / #mux-state-cells), which collided with
the EQDC driver's use of the same compatible through a
"specifier-space: inputmux" phandle-array. Reconcile the two by moving
the EQDC PHASEA/PHASEB input routing onto the generic mux model:
- nxp,mcxa156 / nxp,mcxa344 / nxp,mcxaxx6: switch the inputmux node
from #inputmux-cells to #mux-control-cells / #mux-state-cells so it
validates against the new binding (nxp,mcxa153 was already done).
- nxp,mcux-eqdc.yaml: drop the local inputmux-connections property and
include mux-consumer.yaml; routing is now described with "mux-states".
- eqdc_mcux: drop the direct fsl_inputmux HAL calls and apply the
routing through mux_state_apply(), guarded by device_is_ready(). The
mux controllers init at priority 40, before the sensor at 90, so they
are ready at EQDC init time.
- Migrate the frdm_mcxa153/156/266/344/346/366 QDEC sample overlays to
the mux-states syntax.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a controller-agnostic ztest suite that configures a route with
mux_control_set() / mux_state_apply() and verifies it by reading the
state back with mux_state_get().
Per-controller wiring lives in board overlays and Kconfig, so the same
suite exercises different backends:
- mimxrt1050_evk (XBAR): real SEL-register read-back.
- frdm_mcxe247 (TRGMUX): TRGCFG read-back. The SoC dtsi describes no
trgmux node, so the board overlay adds one.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The mux subsystem redefines the "nxp,inputmux" binding as a mux
controller (#mux-control-cells / #mux-state-cells), which collided with
the previous ctimer PWM-capture use of the same compatible through a
"specifier-space: inputmux" phandle-array. Reconcile the two by moving
ctimer PWM capture onto the generic mux model:
- nxp,mcxa153: switch the inputmux node from #inputmux-cells to
#mux-control-cells / #mux-state-cells.
- nxp,ctimer-pwm.yaml: drop the local inputmux-connections property and
include mux-consumer.yaml; routing is now described with "mux-states".
- pwm_mcux_ctimer: drop the direct fsl_inputmux HAL calls and apply the
routing through mux_state_apply() guarded by device_is_ready(). The
route is applied when capture is configured, where all devices are
ready. Update the test overlay to the mux-states syntax.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Drop the direct MCUX_XBARA HAL coupling in the QDEC driver in
favour of the new generic mux subsystem: the driver now selects
CONFIG_MUX, defines mux states from a "mux-states" devicetree
property and applies them at init time via mux_state_apply(),
which makes it agnostic to the underlying mux hardware.
Update the nxp,mcux-qdec binding to include mux-consumer.yaml,
augment the i.MX RT10xx XBAR nodes with CCM clock phandles plus
the new #mux-control-cells / #mux-state-cells declarations, and
migrate the MIMXRT1050-EVK QDEC overlay to the mux-states syntax.
Add the matching XBAR clock support to the i.MX CCM clock driver
(IMX_CCM_XBAR1_CLK / IMX_CCM_XBAR2_CLK gate/ungate, guarded by
CONFIG_MUX_NXP_XBAR) so the XBAR controllers referenced by those
nodes can be clocked.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Drop the direct INPUTMUX_AttachSignal() coupling in the QDC driver
in favour of the new generic mux subsystem: the driver now selects
CONFIG_MUX, defines mux states from a "mux-states" devicetree
property, and applies them at init time via mux_state_apply().
This makes the driver mux-hardware-agnostic.
Update the nxp,mcux-qdc binding to use mux-consumer.yaml, expose
the inputmux0 node on the MCXNx4x family DTSI, and migrate the
FRDM-MCXN947 / MCXN5xx-EVK QDC overlays to the new mux-states
syntax.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a mux controller driver for the NXP MCUX XBAR (Crossbar
Switch) peripheral, supporting both 16-bit and 32-bit SEL register
layouts via DEVICE_MMIO. Update the nxp,mcux-xbar binding to also
declare the mux-controller interface (#mux-control-cells and
documenting the legacy xbar-maps property for as-yet-unmigrated
consumers (e.g. qdec_mcux).
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a mux controller driver for the NXP TRGMUX peripheral, used to
multiplex trigger signals between on-chip peripherals. The
controller exposes two address cells (trgmux instance / output id)
and supports register-level lock so that an applied routing can be
frozen for the lifetime of the system.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a mux controller driver for the NXP INPUTMUX peripheral.
Wraps the HAL INPUTMUX_AttachSignal() routine to route a
peripheral input signal onto a destination channel through the
unified mux_state_apply() API.
Co-Authored-By: Declan Snyder <declan.snyder@nxp.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Introduce a new generic multiplexer (MUX) controller subsystem
modeled on the Linux mux framework. Provides a unified API for
software- and hardware-level signal routers via mux_control_set()
and mux_state_apply(), with userspace syscall handlers and common
devicetree bindings (mux-controller / mux-consumer) for downstream
consumers.
Co-Authored-By: Felix Wang <fei.wang_3@nxp.com>
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add UART driver support for the CH5xx.
This enables the hello_world and the drivers/uart/echo_bot samples.
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
Add a pin controller driver for the WCH CH570 SoC.
Implements `pinctrl_configure_pins` to enable GPIO initialization and
alternate function configuration.
Update hal_wch revision in west.yml and hal_ch32fun.h to sync with
changes merged in zephyrproject-rtos/hal_wch#6
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
This commit introduces the following changes:
- Add device tree definitions for the Qingke V3C cpu
- Add device tree definitions for the CH570 SoC
- Add bindings for UART, GPIO and pin control
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
Rework the esp32 pcnt driver to expose every counting unit of a
single device. The read-and-decode api threads the unit index
through sensor_chan_spec.chan_idx so sensor_read returns an
encoded buffer that the driver's decoder unpacks per unit. The
legacy sensor_channel_get path is kept on unit 0 for backward
compatibility.
The new sensor_chan_pcnt_esp32_unit(n) helper (in a public
header) packs the unit index into the legacy sensor_channel
field so sensor_attr_set and sensor_trigger_set can target a
specific unit. A new sensor_attr_pcnt_esp32_reset attribute
clears the hardware counter.
Dt binding gains counts-per-revolution (enables degrees output
on sensor_chan_rotation), high-limit and low-limit watchpoints
(counter auto-resets on reach and raises the trigger), and
zero-cross-event. Filter is documented in apb cycles with the
correct 1023 clamp.
Threshold trigger demultiplexes per unit in the isr and fixes
the old behaviour that silently re-allocated the isr on every
trigger_set. Interrupt alloc moves to init.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The driver supports up to nine SMBus controllers and implements the
standard SMBus protocols, except for Block Process Call.
It also supports an optional FIFO mode that uses the controller's
dedicated 32-byte FIFOs to reduce the interval between transferred
bytes and improve clock stretching during SMBus transactions.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Boards that gate the nRF70 VBAT/BUCKVBAT/AFEVBAT rail themselves had no
way to describe it, so the rail could not be raised and settled before
BUCKEN was asserted as the datasheet requires.
Include power.yaml in the nRF70 binding so the nodes accept the standard
supply-gpios and vin-supply properties, and add supply-power-up-delay-ms
for the settling time. Its 6 ms default is the minimum stated in the
nRF7002 datasheet, section 14.3.5, supply sequencing requirements. The
SPI bindings already inherited both properties through spi-device.yaml
while the QSPI ones did not, so in practice only QSPI gains them.
rpu_pwron() raises the supply and waits before touching BUCKEN, and
rpu_pwroff() releases it once IOVDD and BUCKEN are down. The two
properties are handled independently rather than as an either/or, so a
board with a shared regulator feeding a per-device load switch works:
power.yaml requires the regulator to be requested before the supply GPIO
goes active and the GPIO to go inactive before the regulator is
released, which is the order implemented here.
The supply spec and the regulator device are declared unconditionally,
using GPIO_DT_SPEC_GET_OR() and DEVICE_DT_GET_OR_NULL() so both are
present but empty when the properties are absent. That lets the call
sites use IS_ENABLED() instead of #ifdef, so every configuration
compiles the code and build errors are caught without adding twister
combinations. A vin-supply phandle to a node that is not okay yields
NULL, so rpu_gpio_config() checks device_is_ready(vin_supply) alongside
the GPIO ports.
If rpu_pwron() fails, rpu_init() only removes the GPIOs, which leaves a
switched rail undriven rather than off. It now releases the supply
first: the GPIO is driven inactive, and the regulator is released only
when this driver holds a reference on it, tracked in vin_supply_enabled.
regulator_is_enabled() cannot answer that question, as it is also true
when another consumer enabled a shared regulator.
Three Kconfig symbols are derived from the devicetree, one per property,
and NRF70_SUPPLY combines the two supply ones so the settling delay sits
behind a single condition. NRF70_VIN_SUPPLY and NRF70_IOVDD_REGULATOR
select REGULATOR, since the driver calls regulator_enable() and
regulator_disable(). Without that select such a configuration failed to
link with undefined references to those symbols. The iovdd-regulator
path has had this gap since 57baf7cf72 ("modules: nrf_wifi: Allow using
a regulator for IOVDD"); no in-tree board uses it, which is why it went
unnoticed.
Tested on an out-of-tree nRF5340 + nRF7002 board with
samples/net/wifi/shell in three configurations: the supply on a GPIO
only, behind a regulator-fixed node only, and both at once with the
regulator feeding the switch. All three power the RPU up and return
results from wifi scan.
Signed-off-by: Buster Bøgild Nielsen <busterbbn@gmail.com>
Add support for the Texas Instruments ADS7828 12-bit and ADS7830
8-bit 8-channel I2C ADCs. The two parts share one command byte and
channel permutation and differ only in resolution, so one source file
covers both. ADS7828-Q1 reuses the ADS7828 compatible.
Signed-off-by: JaeHwan Jin <jaehwan.jin@rakwireless.com>
With the SysTick minimum timeout now derived from the cycle rate, the
32 kHz Bee SoCs get a ~1-cycle floor automatically, well under the
32-cycle tick, so the hand-set zephyr,min-timeout-cycles override is no
longer needed. Removing it also lets the driver program sub-tick LOAD
values, which drains the small per-ISR cycle surplus and avoids the
dticks=2 double-fire that a 32-cycle floor produced.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Move tsi0 DTS from nxp_mcxn94x_common.dtsi to nxp_mcxnx4x_common.dtsi.
Both MCXN94x and MCXN54x variants can use it.
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
Switch max32657evkit and max32658evkit boards from fixed-partitions to
zephyr,mapped-partition.
Enable USE_DT_CODE_PARTITION for these boards to avoid manually
calculating flash load offset.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add support for the AE822FA0E5597BS0 SoC from the Ensemble
E8 series. The SoC contains two Cortex-M55 CPU clusters:
RTSS-HP (Real Time SubSystem - High performance), RTSS-HE
(Real Time SubSystem - High Efficiency) and a Cortex-A32
CPU cluster: APSS (Application Processor SubSystem). Support
for all three clusters has been added.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The nxp_ke17z.dtsi, nxp_ke17z512.dtsi, and nxp_ke1xz64.dtsi overlays
each remove the parent nxp_ke1xz.dtsi's flash-controller node with
`/delete-node/ ftfe;` inside the soc {} scope. A `/delete-node/`
directive inside a node body can only reference a child by its node
name (name[@address]); the label form is silently ignored, so the
parent's flash-controller@40020000 was never actually removed.
Replace `/delete-node/ ftfe;` with the full-form
`/delete-node/ flash-controller@40020000;` in all three overlays so
the parent node is actually removed before the replacement is added.
Signed-off-by: Wei Feng <wei.feng_5@nxp.com>
Add AES and SHA-256 crypto drivers for Realtek Bee SoCs. The AES
supports 128-bit and 256-bit keys with ECB, CBC, CFB, OFB, and CTR
modes.
The SHA-256 driver supports one-shot hash operations. Add devicetree
bindings and disabled nodes for RTL8752H and RTL87x2G, so boards can
enable the accelerators explicitly.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add a native_sim driver to read a Linux host temperature using the
Zephyr sensor API.
Signed-off-by: Bayrem Gharsellaoui <bayrem.gharsellaoui@gmail.com>
Enable CONFIG_SMP with support for up to 4 CPUs, and select
CONFIG_PM_CPU_OPS to bring up secondary cores.
Add per-CPU nodes for cpu1-cpu3 in the bcm2711 devicetree, and
mark all four CPUs with enable-method = "spin-table" and their
respective cpu-release-addr values, matching the boot protocol
implemented by the new PM_CPU_OPS_SPIN_TABLE driver.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add a new pm_cpu_ops backend implementing the ARM64 spin-table
boot protocol for bringing up secondary CPUs, as an alternative
to PSCI on platforms that don't support it.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
The Solomon Systech SSD1683 is a Gen2 SSD16xx EPD controller (functionally
equivalent to the SSD1619A, 400 sources x 300 gates). It uses the same
command set as the already-supported SSD1680/SSD1681, and loads its refresh
waveforms from OTP, so support is a new devicetree binding plus a quirks
entry with the correct maximum resolution.
Used by e.g. the WeAct Studio 4.2" and GoodDisplay GDEY042T81 400x300
mono panels.
Signed-off-by: Marcus Voß <meav33@gmail.com>
- Adds the "zephyr,memory-region" compatible property
to the SRAMX node on LPC55S6x.
This exposes the RAM block as named memory region
so it can be referenced from linker sections and application code.
- Fixes the inability to relocate code to SRAMX on LPCXpresso55s69.
- Moves the SRAMX memory-region definition
from nxp_lpc55S0x_ns.dtsi to _common.
- It follows the memory-region approach used
by nxp_lpc55S1x/2x/3x_common.dtsi
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Replace the placeholder sai nodes, which carried a compatible with
no binding or driver, with real nxp,mcux-i2s nodes: MC_CGM clocks,
eDMA channels and requests (SAI0 on DMAMUX0, SAI1 on DMAMUX1), and
the bus clock as bit clock source since this SoC has no audio PLL
or MCLK routing. For the same reason, default I2S_HAS_PLL_SETTING
to n so the driver derives the bit clock from the module clock.
The nodes stay disabled; the existing delete-node entries of the
smaller derivatives are unaffected.
Verified with tests/drivers/i2s/i2s_speed on frdm_mcxe31b.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Deconfigure: i2s_configure() with frame_clk_freq == 0 is defined by the
API as a request to deconfigure the stream, but the driver rejected it
with -EINVAL. Release the queued buffers and move the stream to
NOT_READY. The state check is now made on the stream being configured
instead of on both directions at once, so one direction can be
configured while the other one is running, and config_get() returns
NULL for an unconfigured stream as the API requires.
Restart: reset the FIFO pointers via the FR bit before enabling DMA
requests, so words left over from a previous run are not replayed.
Bit clock source: the SAI_Get*Config helpers overwrite bclkSource with
the master clock divider, leaving SoCs without an internal divider or
MCLK routing with no bit clock at all. Add an nxp,bclk-source binding
property (TCR2/RCR2 MSEL value) applied after those calls; it defaults
to the master clock divider so existing users are unaffected.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add a driver for the Analog Devices MAX30009 bioimpedance analog
front-end. The device is supported over both SPI and I2C.
This base commit provides the core acquisition-path driver:
- Full BioZ acquisition-path configuration from devicetree (clock/PLL,
drive, receive channel, digital filters, thresholds, mux, DC leads and
lead bias), with a dt-bindings header of MAX30009_DT_* constants for
the enumerated properties.
- Runtime attribute access (attr_set / attr_get) for the meaningful BioZ
parameters via a descriptor table, cycling the PLL where the datasheet
requires the acquisition path to be quiesced.
- Power management (suspend / resume) following the datasheet's
bandgap / PLL / channel enable sequence.
Trigger and RTIO streaming support are added in follow-up commits; the
full Kconfig describing those options is included here so the driver's
configuration surface is complete.
Signed-off-by: Francis Roi Manabat <francisroi.manabat@analog.com>
The echo-timeout defines the maximum range of the ultrasonic sensor and
was hardcoded to 10ms (~1.5m).
This commit creates a dts property for the timeout,
so users can configure the maximum range per sensor instance.
The default setting of the property is 10ms for compatibility.
Signed-off-by: Nils Harder <harder@metratec.com>
remove st,stm32-ethernet-common.yaml and put the
common properties into st,stm32-ethernet.yaml, as
every other binding for the stm32 ethernet driver
also requires that "st,stm32-ethernet" is also used as
compatible, so the common properties can be put into
that binding.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The binding files in mmc directory were nothing specifc but
for SDHC host controllers. Let's move them to sdhc directory.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Add a devicetree property to configure the WM8904 input PGA
source channel.
The selected channel is used when configuring the analog input path.
For the 32-pin QFN package, only input channels 1 and 2 are valid
because the IN3L/IN3R pins are not exposed. The driver currently
supports single-ended input mode only
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
We update the PCR hardware nodes for all XEC parts with new
properties of the updated clock control driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We updated the XEC clock control driver to support MEC174x/5x
and move away from hard to maintain CMSIS register structures.
Addition device tree properties were added for tuning the driver's
XTAL configuration sequence. Note: MEC15xx does not have the
clock monitor hardware for checking XTAL health and no way to
fallback if the XTAL fails.
Many MEC15xx/MEC172x legacy Zephyr drivers are using XEC specific
clock control driver PCR sleep and reset APIs. Until all old
drivers are converted to use the same functionality from the MEC SoC
layer we must keep these APIs. We converted them to call the SoC
layer. Once all drivers have been converted we can removed these
custom APIs from the clock control driver.
The domain clock-cells parameter was renamed to clkid matching usage
in the DW I2C driver and many other clock control drivers.
We changed domain to clkid in the only two drivers remaining that
use it, interrupt-controller and crypto.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
