Enables using the whole flash on CH32V208
This also involves limiting frequency of the CPU to 120Mhz
from 144Mhz to meet recommendations.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Move backlight i2c controller address into DTS configuration
to be able to use jhd1313 driver for dfrobot's LCD1602.
Signed-off-by: Leon Mariotto <leon2mariotto@gmail.com>
This commit introduces a new driver for a common GPIO-driven 7-segment
display. supporting both common anode and common cathode configurations.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Add CAN driver support for Renesas RZ/G3S
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
it8xxx2 pwm driver does not handle "pwm-output-frequency" property,
so setting the property in borad.dts is useless.
About PWM output frequency, it can be set by pwm-cells "period",
"pwm-output-frequency" is really redundant.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The CH32V006 is part of the CH32V00x series of 32 bit RISC-V
microcontrollers. This series is an evolution of the CH32V003 which
was used as a basis for this Devicetree definition.
Compared to the CH32V003, thie CH32V006 has an extra GPIO port (PB),
an extra UART (UART2), 8 KiB of RAM, 62 KiB of flash, and uses the
QingKe V2C core.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The CH32V006 and others in the CH32V00x series are an evolution of the
CH32V003 and use different remap offsets for the various peripherals.
In the same way as the CH32V20x, fork the CH32V003 driver and add
CH32V00x support.
Signed-off-by: Michael Hope <michaelh@juju.nz>
This commits follows the prior commit to update all the base
register which uses the Davinci driver as thier GPIO driver
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
1. rework IOM cmdq buffer instantiation
2. rework spi and i2c cache handling as it is incorrect.
3. buffers need to be aligned with DCACHE on
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The Microchip CAP12xx series has a configurable sensitivity and
can drive an optional guard signal to reduce noise sensitivity.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
Add TI OMAP interprocessor mailbox node for J722s MCU R5,
the user ID assignment is as per the corresponding mailbox
interrupt assignment for the core.
Signed-off-by: Andrew Davis <afd@ti.com>
Add TI OMAP interprocessor mailbox node for J722s MAIN R5,
the user ID assignment is as per the corresponding mailbox
interrupt assignment for the core.
Signed-off-by: Andrew Davis <afd@ti.com>
Add TI OMAP interprocessor mailbox node for J721e MAIN R5,
the user ID assignment is as per the corresponding mailbox
interrupt assignment for the core.
Signed-off-by: Andrew Davis <afd@ti.com>
Add "zephyr,displays" compatible for passing available display
controllers nodes to graphical libraries that have multi-display support
like LVGL
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add the 20-pin camera connector used by at least Arducam, Waveshare,
Olimex, Arduino, NXP, ST, Adafruit that connects image sensor module
boards and devkits.
Signed-off-by: Josuah Demangeon <me@josuah.net>
This patch modifies the DTS files for Intel ADSP ACE 3.0 platforms,
ensuring the power-states node is a child of the cpus node. This change
aligns with Linux conventions and mirrors the adjustments made in commit
e4c43e4cc9 for other platforms.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This diag0-gpios property allows configuring the diag0 diagnostic pin,
which can be used to indicate position reached, stall detection, and
other status information from the controller.
Signed-off-by: Dipak Shetty <shetty.dipak@gmx.com>
Change the base address of GPIO and pinctrl voltage selection
The new base address enables more pins to support voltage selection.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The tx-en-settle-time-us is set to 26 to take into account
the time needed for the RF output power rise time of the nRF5 SoC.
Signed-off-by: Andrzej Kuros <andrzej.kuros@nordicsemi.no>
Remove the boolean flag "promiscuous-mode" from the GEM's
DT binding, as promiscuous mode control is being switched
over the the Ethernet device driver's get_config/set_config
API functions.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Add a parameter to define the maximum PSRAM frequency for the STM32 XSPI
driver. It will be useful to automatically calculate a prescaler.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
As the code noted, the RGMII RX and TX clock delay values may need to
change depending on the MAC configuration or the PCB layout. Add
properties to allow configuring these in the device tree, defaulting to
the previous hard-coded values if not present.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
The GPTM is a general purpose module with a 16 bit prescaler, 16 bit
counter, and 4 compare units that can be used for PWM generation.
Use the same style as gd32 where the timer is a counter and the PWM
mode is a child node.
Signed-off-by: Michael Hope <michaelh@juju.nz>
