dts: bindings: stm32: add div-q and div-r on stm32mp13 plls
Depending on the PLL, all DIV-P / DIV-Q and DIV-R are available on STM32MP13 PLLs. Adjust valid range in order to be able to set for all 4 PLLs. Clarify DT properties description. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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@ -28,6 +28,14 @@ description: |
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than 1000 MHz or program the mpuss_ck mux to use the MPUDIV
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(refer to the stm32mp13 reference manual for details)
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div-m (aka DIVM1 + 1), div-p (aka DIVP + 1), div-q (aka DIVQ + 1),
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div-r (aka DIVR + 1) have identical valid ranges for all 4 PLLs.
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mul-n (aka DIVN + 1) valid range depends on the PLL
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PLL1: 31 - 125
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PLL2: 25 - 100
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PLL3: 25 - 200
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PLL4: 25 - 200
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compatible: "st,stm32mp13-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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@ -44,21 +52,32 @@ properties:
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type: int
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required: true
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description: |
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Prescaler for PLLx
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input clock
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PLLx division factor (aka DIVM1 + 1) of the input clock divider
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Valid range: 1 - 64
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mul-n:
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type: int
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required: true
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description: |
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PLLx multiplication factor for VCO
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Valid range: 31 - 125
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PLLx multiplication factor (aka DIVN + 1) for VCO
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Valid range: 25 - 200
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div-p:
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type: int
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description: |
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PLLx DIVP division factor
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PLLx_P division factor (aka DIVP + 1)
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Valid range: 1 - 128
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div-q:
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type: int
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description: |
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PLLx_Q division factor (aka DIVQ + 1)
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Valid range: 1 - 128
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div-r:
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type: int
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description: |
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PLLx_R division factor (aka DIVR + 1)
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Valid range: 1 - 128
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frac-v:
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