RTS5912 supports the SWJ interface,
which configures related GPIOs during EC initialization.
Disable the SWJ interface to ensure the GPIOs
remain in the state defined in the device tree.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
OTP address was wrong (bad copy/paste from another series). This commit
sets it to the correct value.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Extends ADP5360 Regulator API support to the existing
ADP5360 Buck and Buck Boost Regulator.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Implements fuel gauge subsystem for ADP5360 MFD driver.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Adds Charger subsystem support for the ADP5360 MFD device.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Implements I2C communication used by drivers under this parent device,
interrupt support, supervisory data configuration,
and power management subsystem API.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Updated PCR and GIRQ properties to use new macros.
Updated symcr and romapi node for mec174x/5x/165xb
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
RM0481 Rev 4 documents the Ethernet PTP timestamp clock as a dedicated
reference clock (`clk_ptp_ref_i`), not the `eth_hclk` bus clock.
Table 115 ("Kernel clock distribution overview", p. 470/3154) lists
`ETH (ptp)` on `pll1_q_ck`, and the IEEE 1588 section states that the
64-bit PTP time is updated from `clk_ptp_ref_i`.
Add an explicit `mac-clk-ptp` clock for STM32H5 sourced from
`STM32_SRC_PLL1_Q`, use that clock rate for PTP addend programming.
Because this change introduces source-clock configuration for STM32
Ethernet clocks, update the STM32H7 DWMAC path as well: use
`clock_control_configure()` for source clocks such as `eth-ker`, while
keeping `clock_control_on()` for gated clocks.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
Configure the NWP clock to 80 MHz by default, as this is
the default frequency used by the HAL.
Remove description of frequency options in the binding, since
these are tied to the software implementation and don't
neutrally describe the hardware.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add FDCAN node for STM32C5 dtsi files.
FDCAN1 can be found on all STM32C5 except the STM32C5x1, and FDCAN2 is
present on STM32C532/42 and STM32C593/A3.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add input driver support for CRSF (Crossfire) receivers, originally
developed by Team BlackSheep (TBS) and used by ExpressLRS (ELRS) and
others.
The driver allows mapping up to 16 CRSF channels to Zephyr input events,
supporting both absolute axes (joysticks) and key events (switches), and
operates over a standard non-inverted UART interface.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Add devicetree binding for the TE Connectivity (Measurement Specialties)
HTU21D humidity and temperature sensor. The HTU21D is register-compatible
with the Sensirion SHT21, so this binding simply includes sensirion,sht21.
Signed-off-by: William Markezana <william.markezana@gmail.com>
When present, configure the pin as input and use GPIO for card presence
instead of SDIF_DetectCardInsert(). Useful if the board uses a pin other
than SD0_CARD_DET_N for card detection.
On the LPC55S28 we needed it to work around an issue where configuring
PIO1_13 as SD0_CARD_DET_N stalled Flexcomm6 I2C transfers. The same pin
works when muxed as GPIO.
Signed-off-by: Fabian Otto <fabian.otto@rohde-schwarz.com>
- Added autanalog MFD support in PSE84 DTS files
- Refactored autanalog ADC in PSE84 to use a common
MFD for handling the global AC configuration
- Constructed AC to use phandle in the overlay
for a better the user experience.
- Added support for a basic and advanced mode
with custom AC
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add GPIO controller nodes and LPD/PMC banks for Versal.
There are a total of 174 channels in two controllers:
- PMC GPIO controller:
- Two banks (26 channels each) to PMC MIO
- Two banks (32 channels each) to PL EMIO
- LPD GPIO controller:
- One bank (26 channels) to LPD MIO
- One bank (32 channels) to PL EMIO
ref: https://docs.amd.com/r/en-US/am011-versal-acap-trm/GPIO-Controller
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Add counter RTC driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Basic counter operations
- Alarm configuration and callbacks
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
This change adds missing reset binding on lan9250.
Reset gpio was implemented in the driver but not defined in the
binding.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
The STM32F777 is a variant of the STM32F767 that adds a hardware
crypto accelerator (CRYP). Add SoC support by including the
stm32f767.dtsi and extending with the CRYP peripheral node.
Fixes: #105976
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
QSPI peripheral is now called MSPI in the MDK. To align
with this change, peripheral has been renamed in the
devicetree to MSPI.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
The driver provides basic RTC functionality including time read and
write, alarm configuration(alarm1 and alarm2), and daylight saving
time (DST) support.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Updated the KSCAN node with the default and sleep pin control
configuration for the 18×8 matrix keyboard on MEC174x/5x/165xB devices
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add an RT118x ARM PLL binding wrapper that reuses the shared
loop-div/post-div schema and derive CLOCK_InitArmPll() directly
from devicetree.
RT118x keeps the new loop-div/post-div properties only and removes
the hard-coded loop and post divider values from the SoC init path
while retaining the HAL loop divider range check.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace the fixed-factor-clock compatible with an RT11xx ARM PLL
binding that shares the loop-div/post-div schema through a common
include.
The RT11xx wrapper keeps the deprecated clock-mult/clock-div
properties and the SoC code falls back per property so existing
definitions keep working while new overlays can switch to
loop-div/post-div.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Region size defined for lp_uart and lp_gpio on c5/c6 does not match TRM.
Reduce to 1kB per TRM.
Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
Add I3C_CONTROLLER_FLAG_DISABLE_HJ_AT_INIT as BIT(1) in the
controller config flags. When set via the devicetree boolean property
"disable-hj-at-init" on the I3C controller node, Hot-Join ACKs will
not be enabled at the end of bus initialization. Hot-Join events will
be NACKed until the application explicitly enables them.
Guard the ENEC HJ broadcast in i3c_bus_init() (i3c_common.c), the
cdns-specific HJ ACK register write, the dw HJ NACK clear, and the
stm32 LL_I3C_EnableHJAck() call with this flag.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add a flags field (uint8_t) to struct i3c_driver_config and define
I3C_CONTROLLER_FLAG_DISABLE_BUS_INIT as BIT(0). When set via the
devicetree boolean property "disable-bus-init" on the I3C controller
node, i3c_bus_init() will not be called during driver initialization,
allowing the application to perform bus initialization at a later time.
Add I3C_CONTROLLER_CONFIG_FLAGS_DT_INST() macro in devicetree.h to
read the flag from the devicetree, following the same FIELD_PREP
pattern used for per-device flags in I3C_DEVICE_DESC_DT.
Update cdns, dw, max32, it51xxx, mcux, npcx, renesas_ra, and stm32
drivers to populate the new flags field and check it before calling
i3c_bus_init().
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
These partitions are for the secure (TF-M) image and are not
updateable images, align naming with the same name as other
platforms for this purpose
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add UICR binding for nRF71 series to allow 1.8v supply to be
configured from devicetree.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
The need to monitor battery voltage on nordic devices and nRF7120
in particular is required among other metrics such as die temperature.
Creating a sensor to measure battery voltage allows to easily monitoring
of all required metrics in a consistent way.
This commit adds a new sensor driver to monitor battery.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Implement post-merge review remarks:
- check return values correctly
- fix bad function naming
- fix binding no title
- use function instead of macro as is possible
Signed-off-by: Camille BAUD <mail@massdriver.space>
Enable the GPIO peripheral for the nRF54H20 FLPR core.
Add the corresponding test overlays so that the
tests run correctly under Twister for the FLPR core.
Signed-off-by: Paweł Pelikan <pawel.pelikan@nordicsemi.no>
