Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Introduce the NRF GPIO Pad Group device driver and binding. The
pad group device represents the GPIO pads (pins), contrary to a
GPIO controller, which is one of the many devices which can be
muxed to pads in the pad group.
The pad group belong to a power domain, which is not neccesarily the
same power domain as devices being muxed to the pads, like GPIO or
UART. If no ACTIVE device is using any of the pads in the pad
group, the pad groups power domain may be SUSPENDED. Before the pad
groups power domain is SUSPENDED, pad config retention must be
enabled to prevent the pads from loosing their state. That's what
this device driver manages. Once retained, the pad configs and
outputs are locked, even when their power domain is SUSPENDED.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible for netc driver.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added "nxp,imx-netc" compatible.
2. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update NETC device nodes according to NETC driver update:
1. Added NETC block control device node to handle block control
initialization in netc block driver.
2. Added "nxp,imx-netc" compatible for netc driver.
3. Added all memory region in MMIO reg propertiy to let driver to handle
MMIO mapping for all memory region.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
As reg property is not used by the driver and there is no proper address
could be assigned to it, so remove it.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add NETC block driver, it could do some block memory region MMIO mapping
and also so dome block initialization, moved some netc related
configuration form board_init() to block driver so that it could be reused
between different platforms, although some configuration is different for
different platform, but put all NETC related code in the same driver to
make it easier to be maintained.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update the driver to support DMA operations on L4 series devices, with
a shared DMA channel. Split channels do not work on these chips, since
there is no dedicated TX and RX channels on the DMA, so configuring two
channels with SDMMC as the peripheral results in a non-functional
configuration.
Fixes#91216.
Signed-off-by: Jordan Yates <jordan@embeint.com>
1. Update nxp irtc driver to fix issue in init and alarm function.
2. Update RTC device tree binding to support "share-counter".
3. Update RT700 dtsi to support rtc0 for cpu0 and rtc1 for cpu1.
4. Update readme.
5. Update unit test project conf for RT700.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The driver gets FMC bank address using
`FMC_BANK1_<parent_register_value>` define.
This approach has some flaws:
- The parent (bank) register's value might not correspond
sequentially to the expected bank number.
For example: `STM32_FMC_NOSRAM_BANK3` maps to `FMC_BANK1_4`,
instead of `FMC_BANK1_3`.
- Some families don't even define the necessary `FMC_BANK1_x` macros.
To address this, the commit adds an optional `bank-address` property,
providing a direct way to define the FMC bank address for the driver.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
This files can be used by the 32-bit as well as 64-bit ARM
architectures. Move them into the dts/vendor/ti directory to
make the ISA independant.
All nodes located in the AM64x MAIN domain should have the main_
prefix. This makes it more clear where those pins are actually
located in the chip.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add missing ranges to nrf54h20.dtsi reserved-memory. No translation
is required so ranges is set to <empty>.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add missing ranges to global_peripherals to explicitly translate
child addresses of global_peripherals in ram (0x2f000000).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The Raspberry Pi Pico 2 uses a QMI flash controller, which differs from the
SSI controller used in the original Pico. Zephyr already has support for
the SSI controller, but lacked support for QMI.
This change adds the QMI flash controller implementation in the
flash_rpi_pico.c driver file. Additionally, the RP2350 SoC devicetree file
(rp2350.dtsi) has been updated to enable and describe the flash controller
for Pico 2.
Signed-off-by: Hanan Arshad <hananarshad619@gmail.com>
As a first step to enable the similar variants (e.g: ICM42686),
refactor common functionality into icm4268x files. As a result,
applications using the icm42688 will need to have both compatible
properties: "invensense,icm42688" and "invensense,icm4268x" defined.
In-tree boards have been modified to comply with this pattern.
This patch does not contain functional changes. The driver should
work the same as before.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
SPI(M/S)20 and SPIM(M/S)21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
UARTE20 and UARTE21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
update exti num-lines to depict total number of lines
add clocks entry to exti nodes of certain series
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
add num-gpio-lines with default value of 16 to
st,stm32-exti.yaml
Co-authored-by: Mathieu CHOPLAIN <mathieu.choplain@st.com>
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
As i.MX 95 19x19 and i.MX 95 15x15 have different pinmux definitions,
keep common part in nxp_mimx95_a55.dtsi, and define separate dts file
for each variants. These include the common part and their respective
pinmux definitions.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
The GPIO block instance is based on the instance number during the
device driver initialization. This is not correct as instance numbers
in now way reflect any numbering scheme. Therefore, a DTS property
is introduced so that the block instance numbering is indicated
explicitly.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add dts support for the STM32C091 and STM32C092 SoCs,
that are part of the STM32C0 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fix interrupt level for acmp0 in the dts for xg21 device.
Only radio interrupts are critical and should have priority 0.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
The icm45686-xxx example nodes have incorrect node labels.
The current node labels are for the icm42688.
Signed-off-by: Alden Haase <aldenhaase@gmail.com>
The Network Coprocessor on SiWx91x owns a large part of the flash. Zephyr
is not expected to access to theses areas.
However, it is still technically possible to access these. In addition, we
prefer the DTS contains a comprehensive and transparent description of the
hardware. So update the DTS with the real partitioning of the SoC.
Reference documentation is available here[1].
[1]: https://www.silabs.com/documents/public/application-notes/
an1416-siwx917-soc-memory-map.pdf
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
With commit d280d89 the gpiof port got moved from file stm32u5.dtsi to
file stm32u5_extra.dtsi. stm32u5_extra.dtsi is not included for
STM32U535/545. In same file stm32u5.dtsi still node wkup-pin@8 references
non-existent port gpiof.
Fixes#93445
Signed-off-by: Andreas Schmidt <andreas.schmidt@dormakaba.com>
Remove unused DMA clock property from device tree. Clock will
be managed by DMA driver for devices with GDMA peripheral.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
With IronSide SE there is only one defined UICR which is at
the location of the APPLICATION UICR. Update the devicetree
definition accordingly, and use the "nordic,nrf-uicr" compatible
on the node since the domain distinction added by the v2 compatible
is no longer relevant.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Refactor the default RAM memory map on nrf54h20dk:
Removes use of "nordic,owned-memory" which is no longer needed on
nrf54h20. Reserved memory nodes that were under "nordic,owned-memory"
have been moved directly under reserved-memory.
The memory shared between cpuapp-cpusec and cpurad-cpusec in RAM0x
is no longer used with IronSide, since IPC buffers toward the secure
domain are at new fixed locations. The cpuapp_data region
has been expanded to fill the available space in RAM0x when removing
these shared memory regions.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This replaces the legacy SDFW compatible board configuration with the
IronSide SE compatible one, thus removing support for running samples
and tests on nRF54H20 devices with the old firmware.
All applications are expected to work on `nrf54h20dk/nrf54h20/cpuapp`
out of the box. For other board targets, all applications are expected
to boot, but may require additional peripheral configuration in UICR.
Build system support for the new UICR format is to be added separately.
Co-authored-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
