We added some new properties to the clock control driver to parameterize
the configuration process for external XTAL. There are delays and
timeouts during when powering up a crystal. The newer chips have
a clock monitor to check the health of the crystal which also requires
many parameters.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We add a YAML binding for Micrcohip XEC hibernation timer to
define the GIRQ and PCR properties of the hardware. The clock
control driver requires using a hibernation timer during its
intialization. We are updated clock control to use a phandle
to the hibernation timer. This requires the hibernation timer
have YAML bindings for non-standard properities.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This commit seperates pinctrl blocks for mdio node and ethernet node,
also add clock source for ethernet node.
Signed-off-by: Nhat Ta <nhat-minh.ta.yn@bp.renesas.com>
Correct the reg properties of nodes sai1_a and sai1_b that should define
the full address value since the empty ranges property in their parent
node.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Adds a hwinfo driver for the NXP LPC55xx Power Management
Controller (PMC).
Instantiates the pmc node on the LPC55S0x/S1x/S2x/S3x/S6x SoCs.
The driver implements hwinfo_get_reset_cause(),
hwinfo_clear_reset_cause() and hwinfo_get_supported_reset_cause().
Tested on LPCXpresso55S06/16/28/36/69
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Use decimal values instead of hexadecimal values in quadspi node
interrupts properties for consistency in the DTSI file where all other
NVIC interrupts IDs are defined using decimal values.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Make interrupts DT properties for DMA nodes more consistent in ST
SoCs DTSI files using diamond delimiters instead of a space char
separated single list. This better reflects to fact the related
drivers rely on NVIC #interrupt-cells property to retrieve the
interrupt references.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add DT definitions for tachometer channels (tach1, tach2, and tach3)
on RTS5912 to support fan speed measurement.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
LPTMR0 is routed to the WUU on the MCXN and MCXA parts (it already
carries a wakeup-ctrls entry) but was never declared a wakeup source.
wakeup-source is the intrinsic declaration that a device is a wakeup
source; the counter driver reads it to decide whether an alarm may arm
the WUU, so an LPTMR that wakes the SoC must carry it.
Add wakeup-source to lptmr0 on every MCXN/MCXA SoC that routes it
through the WUU (MCXA153, MCXA156, MCXA344, MCXA5x, MCXAxx6, MCXN23x
and MCXNx4x).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add a power domain driver for the BCM283X SoC family, enabling VideoCore
firmware-based power management via the mailbox property channel.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add the disabled can@2000aa00 controller node for the BL61x SoC, to be
enabled per-board. The node uses the bflb,bl61x-can binding and CLIC
interrupt 46.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add a classic CAN 2.0 controller driver for the Bouffalo Lab BL61x
(BL616/BL618) SoCs. The ISO11898 peripheral is an NXP SJA1000 compatible
PeliCAN core with 8-bit registers on a 32-bit word stride, so it is
implemented as a thin front-end over the shared CAN_SJA1000 driver.
The controller is clocked from the UART peripheral clock domain (halved
for the SJA1000 internal bit-timing divider) and its TX/RX signals reach
GPIO pads through the UART signal multiplexer, configured via pinctrl.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add Ethernet driver for the Broadcom GENET MAC controller
found on the BCM2711 SoC, targeting the rpi_4b board.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add MDIO driver for the Broadcom GENET MDIO controller,
used to access the PHY attached to the BCM2711 GENET MAC.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add support for the GNSS receiver integrated in the
Ericsson F5521gw (HP HS2340) WWAN module.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
add support for the esp32 in the generic
dwc_mac driver.
esp32 specific code is based
the init of the original esp32 eth driver in zephyr.
The esp32 uses HW version 3.70.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The XEC SMB-I2C block samples SCL/SDA asynchronously even when its PCR
SLEEP_EN is asserted and auto clock-stretches SCL on a START until the
clocks recover.
Add an opt-in wakeup-source boolean to the binding and arm the block's
START-bit wake (WAKE_STATUS bit 0 / WAKE_ENABLE bit 0 at offsets 0x60
and 0x64) plus the GIRQ22 source bit during PM_DEVICE_ACTION_SUSPEND
when the property is set and a target is attached.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Extend generic is31fl319x driver to support is31fl3193 variant.
Similar to 3194 but with slight differences on register and
features.
Reword error message.
Update example in binding of is31fl3194 as well for required
current-limit attribute.
Assisted-by: Claude:claude-sonnet-4.6 Claude-Code
Signed-off-by: Nathan Olff <nathan@kickmaker.net>
Add CAN driver support for Realtek Bee series SoCs,
including RTL87x2G.
This driver supports:
- Classic CAN 2.0A/B
- Standard and Extended identifiers
- Remote and data frames
- Transmission and Reception
Unsupport features:
- CAN FD mode
- Manual recovery
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Rename the EM32 UART compatible to "elan,em32-uart" for consistency with
other EM32 drivers and add the corresponding devicetree binding. The
binding documents required properties under the 'properties' section,
following the Zephyr binding schema.
Changes:
- dts: switch serial@40002000 to compatible = "elan,em32-uart"
(kept disabled)
- bindings: add dts/bindings/serial/elan,em32-uart.yaml
(reg, clocks with gate_id, current-speed, pinctrl-0/-names)
Note: interrupts are not included in this initial binding; IRQ/FIFO can be
added in follow-ups if needed.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add the initial pinctrl driver support for the ELAN EM32 SoC family.
This driver provides basic pin multiplexing and electrical configuration
support. Device tree bindings are included for pin function definitions.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add clock control drivers for the Elan EM32 AHB and APB domains along with
DT bindings and clock gate IDs.
Model peripheral clock gating with #clock-cells = <1>, where the clock
specifier carries a gate-id. Introduce EM32_GATE_NONE for nodes that only
need a parent clock reference without a hardware gate.
Update the EM32 SoC/board devicetree to pass gate-ids in `clocks`
properties and integrate the drivers into Kconfig/CMake.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add the infoctrl syscon register block to the EM32Fxxx SoC DTSI.
The block contains oscillator trim and device information registers.
Add register offsets and field masks in soc_infoctrl.h for driver use.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add a SIP-level dtsi for ESP32-P4 variants combining 16 MB of
external NOR flash with 32 MB of in-package PSRAM, mirroring the
existing esp32p4_n16r8.dtsi. Used by the Waveshare
ESP32-P4-WIFI6-Dev-Kit board.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Add gpioa/gpiob/gpioc and their pin-controller parent to mspm33c.dtsi.
Addresses (0x400f0000/0x400f2000/0x400f4000), IRQs (6/7/8), and the
pin-controller's combined address range are taken from the MSPM33C321A
TRM memory map and NVIC interrupt vector tables
GPIO0/1/2's DOUT/DOE/DIN/POLARITY/CPU_INT register layout is identical
to MSPM0's GPIO_Regs (same GPIO IP block), so the existing
"ti,mspm0-gpio" and "ti,mspm0-pinctrl" compatibles are reused as-is
instead of introducing new bindings.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
STM32MP13 offers different groups of timers similar to what we
can find on some other MCUs like STM32H7xx or STM32F7xx.
- TIM1/8: Advanced-control timers.
- TIM2/3/4/5: 16/32 bits general-purpose timers.
- TIM12/13/14: 16 bits general-purpose timers.
- TIM15/16/17: 16 bits general-purpose timers with break input.
- TIM6/7: Basic timers.
Signed-off-by: Erwan SZYMANSKI <erwan.szymanski@st.com>
Add devicetree bindings for the Analog Devices / Trinamic TMC6460
Field-Oriented Control (FOC) BLDC/PMSM gate driver. The TMC6460 can be
attached over either SPI or UART, so two compatible bindings are
provided:
- adi,tmc6460-spi: the device as a SPI child node
- adi,tmc6460-uart: the device as a UART child node, with an optional
uart-crc property to enable the TMC6460 CRC8 framing
Both bindings expose the physical motor/encoder traits (pole-pairs,
hall-mapping, abn-ppr) so that hardware description lives in devicetree
rather than in the sample sources.
Signed-off-by: Cherrence Sarip <cherrence.sarip@analog.com>
- Adds the eic node to the common dtsi file
- The pin related data in the node is inferred from datasheet
- Updates the binding yaml with new properties
Signed-off-by: Muhammed Asif <asifp3104@gmail.com>
Add SoC-level dts files for the RT118x derivative parts so that each
board can include a single, part-specific dtsi.
Per-core composer files are introduced for every part, in secure and
non-secure (_ns) CM33 flavors:
- RT1189: composer only (uses the series base directly)
- RT1187: composer only (same package and peripheral set as RT1189,
minus the EtherCAT block, which has no DTS node yet)
- RT1186: composer + nxp_rt1186.dtsi for the smaller-package GPIO subset
- RT1185: composer aliasing to RT1186 (same package and peripherals,
minus EtherCAT)
- RT118C: composer aliasing to RT1186 (same package, no NETC)
- RT1182: composer + nxp_rt1182.dtsi for the small-package GPIO subset
(single-core part, only CM33)
- RT1181: composer aliasing to RT1182 (same package and peripherals,
minus EtherCAT, single-core)
This matches the convention used by the RT1160/RT1170 series and lets
boards include only nxp_rt118<part>_cm<core>.dtsi instead of the
series base plus a separate package overlay.
The part overlays use /delete-node/ to reflect the peripheral count
differences of the smaller parts, so the device tree matches the
physical silicon and boards cannot accidentally enable peripherals
that do not exist.
Surviving instances per part, taken from the MCUX SDK device headers
(MIMXRT118x*_COMMON.h), parts only listed where they differ from
RT1189/RT1187:
RT1186/RT1185/RT118C RT1182/RT1181
LPUART 1-8 1-8
LPI2C 1/2/3/6 1/2/3
FLEXCAN 1/3 1/3
TPM 1-4 1-3
LPTMR 1-3 1
QTMR 1-8 1-4
FLEXPWM 1-4 3/4
SAI 1/2/4 1
ACMP 3 3
USDHC 2 2
USB/USBPHY 1 none
NETC none on RT118C present
On the single-core RT1182/RT1181 the CM33<->CM7 MU mailbox nodes are
deleted as there is no second core to talk to, and the GPIO6 pinmux
property is dropped because the package exposes no GPIO6 pins (the
referenced pads do not exist in the RT1182 package pinctrl files).
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The RT118x family is about to grow per-part composer dtsi files for
seven derivative parts in secure and non-secure flavors. Keeping all
of them directly under dts/arm/nxp/imxrt/ next to the other RT series
would make the directory hard to navigate.
Move the existing RT118x family files into an imxrt/rt118x/
subdirectory first, following the series-subdirectory layout already
used by other vendors (st/<series>/, renesas/ra/ra<n>/, gd/<series>/,
infineon/<family>/), and update the board includes accordingly.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Updated spi_xec_qmspi_ldma driver with low power support.
Add a pm_action handler that clears MODE.ACTV and applies the
pinctrl sleep state on suspend, and reverses both on resume.
Hold a PM_STATE_SUSPEND_TO_IDLE policy lock for the duration of
each transfer (sync and async) so suspend cannot enter mid-
transaction.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Correction to sram0_ns sram01, 02, 03 address offset. As RAM01 starts at
0x2008_0000, RAM02 starts at 0x200C_0000, RAM03 starts at 0x200E_0000.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
Describe the STM32N6 8 KiB backup SRAM and enable the driver with
STM32_BACKUP_PROTECTION selected. Extract the retention logic into a
dedicated helper, use the correct device-tree SRAM address, and wait
for standby retention acknowledgement on STM32N6.
Assisted-by: opencode:openai/gpt-5.6
Signed-off-by: Tobias Meyer <tobias.meyer@hula.earth>
Add the snps,dwmac-ptp-clock to all
st,stm32-ethernet, that have a ptp-clock,
independent of current driver support.
Signed-off-by: Fin Maaß <info@finmaass.de>
The current bindings are prepared for the SAM4 which has a
8-bit interface only. This commit adds optional properties
to support also 16-bit interfaces for the SAME7 family.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Extend the WCH RCC clock driver for the CH32H41X series. Add the H41X
PLL binding and SoC clock node, handle the H41X clock-enable register
names and FPRE prescaler, and implement the 480 MHz SYSCLK and
120 MHz HCLK bring-up sequence.
Select the H41X-specific path from the RCC source compatible in
devicetree. Existing CH32V00X, CH32V20X, and CH32V30X configurations
remain unaffected.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Add the CH32H41X SoC series under the ch32v family. The CH32H417 is
an asymmetric dual-core (AMP) RISC-V part with a QingKe V3F boot
core and a QingKe V5F application core.
Model the two cores as cpuclusters with separate CPU descriptions,
runtime-idle power states, interrupt entry, vector handling, and
non-overlapping memory. Keep the external HSE frequency
board-specific.
The optional SOC_CH32H417_BOOT_V5F setting lets the V3F early-init
hook wake the V5F image at its real flash address, 0x08010000, while
allowing standalone V3F applications to disable that behavior.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Add the device-tree bindings needed for the WCH CH32H417 dual-core SoC:
- wch,qingke-v3f and wch,qingke-v5f CPU bindings for the two QingKe RISC-V
cores (V3F boot core and V5F application core).
- wch,h41x-afio pinctrl binding. Unlike the CH32V20x/30x AFIO remap (PCFR)
model, the CH32H41x uses an STM32-style per-pin 4-bit alternate-function
mux in the AFIO GPIOx_AFLR/AFHR registers.
- ch32h41x-pinctrl.h dt-bindings header with the pinmux encoding macros.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
