Commit graph

8801 commits

Author SHA1 Message Date
Kyle Micallef Bonnici
ee940cb6dc dts: arm: nordic: nrf5340: cpuapp: peripheral: add missing reg
Add missing reg property to nrf5340_cpuapp.dts peripheral
node.

Signed-off-by: Kyle Micallef Bonnici <kylebonnici@hotmail.com>
2025-05-05 12:21:17 +02:00
Henrik Brix Andersen
bd409ab231 dts: riscv: neorv32: add GPTMR devicetree node
Add NEORV32 General Purpose Timer (GPTMR) devicetree node.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2025-05-05 12:20:50 +02:00
Henrik Brix Andersen
fc72eafe01 dts: bindings: counter: add NEORV32 GPTMR devicetree binding
Add devicetree binding for the NEORV32 General Purpose Timer (GPTMR).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2025-05-05 12:20:50 +02:00
Marcin Lyda
f7280fac32 drivers: counter: Add MCP7940N property to enable VBAT backup
This PR adds a new devicetree property
that allows enabling external battery
backup functionality.

Signed-off-by: Marcin Lyda <elektromarcin@gmail.com>
2025-05-05 10:57:28 +02:00
Jeppe Odgaard
b3c0be05c4 dts: arm: st: u0: fix msi clock
`msi-range` value 4 sets MSI clock frequency to 1 MHz and not 4 MHz as
intended.

Change value to 6 to increase clock to 4 MHz which matches comment.

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2025-05-03 17:47:58 +02:00
Jeppe Odgaard
6b98f2e99f dts: bindings: clock: stm32-msi: fix whitespace
Change "1M Hz" to "1 MHz".

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2025-05-03 17:47:58 +02:00
Camille BAUD
e5819f7a6c drivers: display: Introduce SH1122
Introduces Sinowealth SH1122 Greyscale 256x64 OLED controller

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-05-02 16:09:08 +01:00
Pete Johanson
99171c39d6 dts: common: adi: Corrected HPB alt func
Correctly use AF3 for HPB on P1.12 for MAX32690.

Signed-off-by: Pete Johanson <pete.johanson@analog.com>
2025-05-02 15:20:55 +02:00
Pete Johanson
f4b52a43d9 drivers: memc: Add MAX32 HyperBus driver
Add memc driver for the MAX32 HyperBus peripheral, supporting HyperRAM
and Xccela PSRAM memory devices.

Signed-off-by: Pete Johanson <pete.johanson@analog.com>
2025-05-02 15:20:55 +02:00
aa469e05fe drivers: pinctrl: enable the AFIO clock on the CH32V003/20x/30x
The Alternate Function IO (AFIO) block must have the clock enabled
before configuring. Some remappings seem to work without, but some
like EXTI do not. Fix.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2025-05-02 10:38:54 +02:00
Raffael Rostagno
8167fe381d drivers: can: esp32c6: Add support
Add TWAI support to ESP32-C6.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-05-02 10:38:39 +02:00
Camille BAUD
73dae9e910 drivers: display: Introduce SSD1320
Introduce a driver for SSD1320 displays

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-05-02 10:37:56 +02:00
Duy Nguyen
7e0d006851 driver: serial: Add support for uart interface for qemu_rx
Support uart driver for qemu_rx environment base on the SCI0
HW on RX MCU

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
84c4c6fa77 drivers: serial: Initial support for Renesas RX serial driver
Intial serial driver support for RX MCU, this driver utilize
the SCI HWIP for uart communication
Current support include polling API and Interrupt driven API,
some of the code is using Renesas RX Driver Package (RDP) as
hal layer

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Sang Tran <sang.tran.jc@renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
86024ffebb drivers: gpio: Support GPIO driver for Renesas RX MCU
Initial commit for GPIO driver support on board using RX130 MCUs
* drivers: GPIO: implementation for GPIO driver on RSK_RX130_512KB
* dts: rx: add device node for GPIO of RSK_RX130_512KB

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
2aa071c7ad drivers: pinctrl: Support pinctrl driver for Renesas RX
Intial support of pinctrl driver for Renesas RX MCU
family.
This support base on using Renesas RX driver package in
hal_renesas layer

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
ad42e4d87d driver: timer: Support for RX system timer
This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
  time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
  for  high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
2f0715262d drivers: clock: Support clock control driver RX MCU
Initial support of clock control driver for RX MCU

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
d4d2b09cac soc: renesas: Add support for RX62N MCU
The qemu-system-rx is based on RX62N, this commit added
support for the RX62N SOC layer. MCU is using RXv1 core and
system timer running at 6MHz

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
dc470f782a goc: renesas: rx: Initial support for RX130 SOC
Minimal SOC layer support for Renesas RX SOC
This SOC is using Renesas RXv1 core

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-05-02 09:18:16 +02:00
Duy Nguyen
fb7bdf0df4 arch: Initial support for RX architecture support
This commit add require code for supporting RX architecture
to Zephyr, it include:
- Add require config and CMakelists for RX arch
- Intialization startup code for RX
- Interrupt and exception handling
- Thread creation adn thread context switch
- irq offload using SW interrupt

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
2025-05-02 09:18:16 +02:00
Amaan Singh
7a74842f95 dts: stm32: Add st,stm32-qdec support to TIM1-TIM5 & TIM8 for STM32F2
Add disabled qdec subnodes to timers TIM1 through TIM5 and TIM8
for STM32F2 series MCUs. This enables Zephyr to provide consistent
QDEC support across all supported encoder-capable STM32 timers.

Signed-off-by: Amaan Singh <amaansingh160@gmail.com>
2025-05-02 09:16:54 +02:00
Aksel Skauge Mellbye
4b4d40017a dts: bindings: silabs: Clean up descriptions, add titles
Clean up dt binding descriptions and introduce titles where
needed to make board documentation pages look nice. The supported
hardware table on board documentation pages sources its data
from dt bindings, and needs succinct titles.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-05-02 09:15:50 +02:00
IBEN EL HADJ MESSAOUD Marwa
1a8f5ba0da dts: arm: st: c0: Add USB device node
Added USB device node with compatible "st,stm32-usb".
Added usb_fs_phy node with compatible "usb-nop-xceiv".

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
2025-05-02 09:15:41 +02:00
cyliang tw
082a3a0878 dts: arm: nuvoton: add adc node of numaker m55m1x
Update m55m1x.dtsi, to add adc node for adc driver support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2025-05-02 07:20:34 +02:00
Alvis Sun
488526190f dts: arm: npcx: Add dts files for NPCK3 series
K3 series is a Nuvoton embedded controller based on NPCX series.
Add npck3m8k dtsi

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2025-05-02 07:19:55 +02:00
Khoa Nguyen
6026d339b3 dts: arm: renesas: Add support Flash-HP for Renesas RA4L1
Add support Flash-HP for Renesas RA4L1 SoC

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-05-02 07:19:46 +02:00
Khoa Nguyen
c0048f1beb dts: arm: renesas: Update Flash-HP node for Renesas SoC
Update Flash-HP node for all Renesas SoCs that enabled support

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-05-02 07:19:46 +02:00
Khoa Nguyen
d9032f03f2 drivers: flash: Update driver flash to support Flash-HP for RA4L1
Update source flash driver to support Flash-HP for RA4L1

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
2025-05-02 07:19:46 +02:00
Martin Jäger
d65149e210 dts: arm: stm32g0: add pwr node and wkup-pins
WKUP3 is only available for g0b0/1 and g0c1 variants.

WKUP5 is only available in larger packages. However, package sizes
are currently not considered in the devicetree file schema for STM32.

Signed-off-by: Martin Jäger <martin@libre.solar>
2025-05-02 01:17:02 +02:00
Armando Visconti
4c34b5d725 drivers/sensor: lis2dux12: add high performance mode
Add driver capability to properly set high performance mode
while setting data rate (thru lis2duxxx_mode_set() API)
based on how power-mode is set into DTS: if it is set to
LIS2DUX12_OPER_MODE_HIGH_PERFORMANCE then configure HP mode,
LP/ULP mode otherwise.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2025-05-01 18:17:05 +02:00
Thomas Lang
999b8f85c6 drivers: sensor: Removed apds9960 interrupt pin
Made interrupt pin on apds9960 optional

Signed-off-by: Thomas Lang <thomaslang2003@me.com>
2025-05-01 18:16:05 +02:00
Martin Meyer
5d39cc1eea drivers: pinctrl: rp2040: extend pin override config
Add a device-tree property to configure the override
functionalities of RP2040 GPIO pins.

Signed-off-by: Martin Meyer <meyer.m90@gmail.com>
2025-05-01 13:42:17 +02:00
Camille BAUD
a97508cd9c dts: bindings: Add Zbit Semiconductor
Add zb prefix

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-05-01 07:15:25 +02:00
Alain Volmat
7481187b95 dts: arm: st: mp13: add ltdc node in stm32mp135.dtsi
Add the node describing the LTDC available in the stm32mp135.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-04-30 23:03:17 +02:00
Alain Volmat
b538ba71ba dts: arm: st: mp13: add description of all i2c instances
Add description of all 5 instances (i2c1 to i2c5) available
on the stm32mp13 soc.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-04-30 23:03:17 +02:00
Francois Ramu
a76b784ee2 dts: arm: stm32H5 reg definition for the st,stm32-xspi compatible
The st,stm32-xspi compatible is defining the reg property
with the register address and size at first index
followed by the external memory base address and max allocated
xspi1 is addressing max 256 MBytes from 0x90000000

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-04-30 18:44:24 +02:00
Francois Ramu
a6d652e158 dts: arm: stm32N6 reg definition for the st,stm32-xspi compatible
The st,stm32-xspi compatible is defining the reg property
with the register address and size at first index
followed by the external memory base address and max allocated
size. For the stm32N6 serie,
xspi1 is addressing max 256 MBytes from 0x90000000
xspi2 is addressing max 256 MBytes from 0x70000000

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-04-30 18:44:24 +02:00
Francois Ramu
ef2268fea9 dts: bindings: memory controller size of the stm32 xspi psram
This PR adds the size in Bits of the PSRAM  memory
for the st,stm32-xspi-psram compatible

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-04-30 18:44:24 +02:00
Francois Ramu
ae748d08fa dts: bindings: flash controller size of the stm32 xspi nor
This PR adds the size in Bits of the flash nor memory
for the st,stm32-xspi-nor compatible

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-04-30 18:44:24 +02:00
Sai Santhosh Malae
c22cf4943b drivers: spi: siwx91x: DTS changes for siwx91x SPI driver
1. Create a YAML file for SPI node
2. Add SPI node in the siwx917.dtsi

Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
2025-04-30 18:44:11 +02:00
Jamie McCrae
320e654e99 dts: common: nordic: nrf5340: Use sub-paritions for TF-M areas
Uses sub-partitions to allow having a dedicated secure and
non-secure partition area in flash partitions, which also allows
the main application slot to be extended when TF-M is not in use

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-04-30 18:44:06 +02:00
Jamie McCrae
f85d017e61 dts: bindings: mtd: Add fixed-subpartitions binding
Adds a new binding which allows for sub-partitioning defined flash
areas

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2025-04-30 18:44:06 +02:00
Francois Ramu
f9e5eeb053 dts: bindings: mmc stm32 sdmmc has a mandatory disk-name
This PR makes the property disk-name required
for the st,stm32-sdmmc compatible

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-04-30 10:55:04 +01:00
Camille BAUD
772b9afc97 drivers: display: Introduce ST75256
Introduces a driver for ST75256 Display Controller that
supports mono and greyscale but not i2c mode.

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-04-30 07:51:57 +02:00
Fin Maaß
94b00090f5 dts: bindings: ethernet:phy: move into own dir
move ethernet phy bindings into their own directory.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2025-04-29 20:07:02 -04:00
Bastien JAUNY
d5365ba513 drivers: input: vs1838b: Add support for VS1838B
The VS1838B is one of the most found infrared receiver
found in electronic kits and is easy to setup with only
a single GPIO used for signal transmission (apart from
VCC and GND).
This new driver let applications use the VS1838B as an
input with events relayed as 0x0000<address><command>.

Only the NEC protocol is supported in this version but
more can be added later.
Link: https://github-wiki-see.page/m/CoreELEC/remotes/wiki/08.-NEC-IR-Protocol-Datasheet

This has been tested using the input_dump sample.

Signed-off-by: Bastien JAUNY <bastien.jauny@smile.fr>
2025-04-29 19:06:37 +02:00
Grzegorz Swiderski
47df9ec981 drivers: firmware: Add support for IRONside calls
IRONside calls are remote procedure calls which comprise the runtime
interface of Nordic IRONside SE. They are realized using a simple IPC
mechanism.

A local domain (client) issues requests to the server by exchanging data
in shared memory, which is divided into evenly sized buffers. The client
selects a buffer, writes a request into it, and sends it to the server.
The server processes that request and writes a response into the same
buffer before returning it to the client.

This patch adds the initial client-side implementation on top of MBOX.
It features cache management and a blocking alloc/dispatch/release API
for synchronous, zero-copy transfers.

A new devicetree binding is added to support this implementation. It is
patterned after the `zephyr,ipc-*` bindings, where each node associates
a pair of mailboxes and a shared memory region.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
2025-04-29 17:54:41 +02:00
Peter Wang
de7c508e58 boards: frdm_mcxa166, frdm_mcxa276: add lptmr and ctimer support
1. enable lptmr and ctimer support
2. verified tests/drivers/count/counter_basic_api

Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
2025-04-29 17:54:30 +02:00
cyliang tw
f6f61100c7 dts: arm: nuvoton: add i2c nodes of numaker m55m1x
Update m55m1x.dtsi, to add i2c nodes for i2c driver support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2025-04-29 16:48:19 +02:00