drivers: clock: stm32mp13: rename frac-v binding into fracn
Rename the frac-v PLL binding into fracn in order to make it consistent with other STM32 PLL bindings. This commit also correct the range which should be 0 - 8191. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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d95b7c4e64
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3 changed files with 6 additions and 6 deletions
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@ -85,7 +85,7 @@
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div-m = <2>;
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mul-n = <83>;
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div-p = <1>;
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frac-v = <2730>;
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fracn = <2730>;
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status = "okay";
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};
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@ -173,7 +173,7 @@ static int stm32_clock_control_init(const struct device *dev)
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uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n);
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uint32_t pll1_m = DT_PROP(DT_NODELABEL(pll1), div_m);
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uint32_t pll1_p = DT_PROP(DT_NODELABEL(pll1), div_p);
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uint32_t pll1_v = DT_PROP(DT_NODELABEL(pll1), frac_v);
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uint32_t pll1_fracn = DT_PROP(DT_NODELABEL(pll1), fracn);
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LL_RCC_PLL1_SetN(pll1_n);
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while (LL_RCC_PLL1_GetN() != pll1_n) {
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@ -184,8 +184,8 @@ static int stm32_clock_control_init(const struct device *dev)
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LL_RCC_PLL1_SetP(pll1_p);
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while (LL_RCC_PLL1_GetP() != pll1_p) {
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}
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LL_RCC_PLL1_SetFRACV(pll1_v);
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while (LL_RCC_PLL1_GetFRACV() != pll1_v) {
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LL_RCC_PLL1_SetFRACV(pll1_fracn);
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while (LL_RCC_PLL1_GetFRACV() != pll1_fracn) {
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}
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LL_RCC_PLL1_Enable();
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@ -80,8 +80,8 @@ properties:
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PLLx_R division factor (aka DIVR + 1)
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Valid range: 1 - 128
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frac-v:
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fracn:
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type: int
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description: |
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PLLx FRACV fractional latch
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Valid range: 1 - 8192
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Valid range: 0 - 8191
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