michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: clock: stm32mp13: rename frac-v binding into fracn

Browse source 
Rename the frac-v PLL binding into fracn in order to make it
consistent with other STM32 PLL bindings.
This commit also correct the range which should be 0 - 8191.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This commit is contained in:
Alain Volmat 2025-05-12 12:21:57 +02:00 • committed by Fabio Baltieri
commit 983d891829
3 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
boards/st/stm32mp135f_dk/stm32mp135f_dk.dts
View file

@ -85,7 +85,7 @@
div-m = <2>;
mul-n = <83>;
div-p = <1>;
frac-v = <2730>;
fracn = <2730>;
status = "okay";
};

6
drivers/clock_control/clock_stm32_ll_mp13.c
View file

@ -173,7 +173,7 @@ static int stm32_clock_control_init(const struct device *dev)
uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n);
uint32_t pll1_m = DT_PROP(DT_NODELABEL(pll1), div_m);
uint32_t pll1_p = DT_PROP(DT_NODELABEL(pll1), div_p);
uint32_t pll1_v = DT_PROP(DT_NODELABEL(pll1), frac_v);
uint32_t pll1_fracn = DT_PROP(DT_NODELABEL(pll1), fracn);
LL_RCC_PLL1_SetN(pll1_n);
while (LL_RCC_PLL1_GetN() != pll1_n) {
@ -184,8 +184,8 @@ static int stm32_clock_control_init(const struct device *dev)
LL_RCC_PLL1_SetP(pll1_p);
while (LL_RCC_PLL1_GetP() != pll1_p) {
}
LL_RCC_PLL1_SetFRACV(pll1_v);
while (LL_RCC_PLL1_GetFRACV() != pll1_v) {
LL_RCC_PLL1_SetFRACV(pll1_fracn);
while (LL_RCC_PLL1_GetFRACV() != pll1_fracn) {
}
LL_RCC_PLL1_Enable();

4
dts/bindings/clock/st,stm32mp13-pll-clock.yaml
View file

@ -80,8 +80,8 @@ properties:
PLLx_R division factor (aka DIVR + 1)
Valid range: 1 - 128
frac-v:
fracn:
type: int
description: |
PLLx FRACV fractional latch
Valid range: 1 - 8192
Valid range: 0 - 8191