dts: arm: adi: max32650: Add more peripheral nodes
This commit adds following updates to MAX32650 SoC: - Divide SRAM to sections according to UG. - Add DMA and SPI nodes - Add WDT nodes without adding clock property - Include dma binding to SoC dts file. Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com> Signed-off-by: Burak Babaoglu <burak.babaoglu@analog.com>
This commit is contained in:
Furkan Akkiz
Fabio Baltieri
parent
9de258c50f
commit
40a60a6ac2
2 changed files with 154 additions and 4 deletions
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@ -6,10 +6,7 @@
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#include <arm/armv7-m.dtsi>
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#include <adi/max32/max32xxx.dtsi>
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&sram0 {
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reg = <0x20000000 DT_SIZE_M(1)>;
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};
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#include <zephyr/dt-bindings/dma/max32650_dma.h>
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&flash0 {
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reg = <0x10000000 DT_SIZE_M(3)>;
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@ -30,6 +27,8 @@
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/delete-node/ &trng;
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/delete-node/ &wdt0;
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&pinctrl {
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reg = <0x40008000 0x4000>;
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@ -57,6 +56,36 @@
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/* MAX32650 extra peripherals. */
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/ {
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soc {
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sram1: memory@20008000 {
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compatible = "mmio-sram";
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reg = <0x20008000 DT_SIZE_K(64)>;
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};
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sram2: memory@20018000 {
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compatible = "mmio-sram";
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reg = <0x20018000 DT_SIZE_K(32)>;
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};
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sram3: memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(128)>;
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};
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sram4: memory@20040000 {
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compatible = "mmio-sram";
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reg = <0x20040000 DT_SIZE_K(256)>;
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};
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sram5: memory@20080000 {
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compatible = "mmio-sram";
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reg = <0x20080000 DT_SIZE_K(256)>;
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};
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sram6: memory@200c0000 {
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compatible = "mmio-sram";
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reg = <0x200c0000 DT_SIZE_K(256)>;
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};
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trng: trng@400b5000 {
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compatible = "adi,max32-trng";
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reg = <0x400b5000 0x1000>;
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@ -105,5 +134,72 @@
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#pwm-cells = <3>;
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};
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};
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spi0: spi@40046000 {
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compatible = "adi,max32-spi";
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reg = <0x40046000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
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interrupts = <16 0>;
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status = "disabled";
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};
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spi1: spi@40047000 {
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compatible = "adi,max32-spi";
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reg = <0x40047000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
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interrupts = <17 0>;
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status = "disabled";
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};
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spi2: spi@40048000 {
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compatible = "adi,max32-spi";
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reg = <0x40048000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
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interrupts = <18 0>;
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status = "disabled";
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};
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spi3: spi@400be000 {
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compatible = "adi,max32-spi";
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reg = <0x400be000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 14>;
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interrupts = <56 0>;
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status = "disabled";
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};
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wdt0: watchdog@40003000 {
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compatible = "adi,max32-watchdog";
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reg = <0x40003000 0x400>;
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interrupts = <1 0>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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status = "disabled";
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};
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wdt1: watchdog@40003400 {
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compatible = "adi,max32-watchdog";
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reg = <0x40003400 0x400>;
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interrupts = <57 0>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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status = "disabled";
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};
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dma0: dma@40028000 {
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compatible = "adi,max32-dma";
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reg = <0x40028000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
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interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>,
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<72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>;
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dma-channels = <16>;
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status = "disabled";
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#dma-cells = <2>;
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};
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};
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};
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54
include/zephyr/dt-bindings/dma/max32650_dma.h
Normal file
54
include/zephyr/dt-bindings/dma/max32650_dma.h
Normal file
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@ -0,0 +1,54 @@
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/*
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* Copyright (c) 2025 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
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#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
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#define MAX32_DMA_SLOT_SPI0_RX 0x01U
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#define MAX32_DMA_SLOT_SPI1_RX 0x02U
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#define MAX32_DMA_SLOT_SPI2_RX 0x03U
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#define MAX32_DMA_SLOT_UART0_RX 0x04U
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#define MAX32_DMA_SLOT_UART1_RX 0x05U
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#define MAX32_DMA_SLOT_I2C0_RX 0x07U
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#define MAX32_DMA_SLOT_I2C1_RX 0x08U
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#define MAX32_DMA_SLOT_ADC 0x09U
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#define MAX32_DMA_SLOT_UART2_RX 0x0EU
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#define MAX32_DMA_SLOT_SPI3_RX 0x0FU
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#define MAX32_DMA_SLOT_SPI_MSS_RX 0x10U
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#define MAX32_DMA_SLOT_USB_RX1 0x11U
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#define MAX32_DMA_SLOT_USB_RX2 0x12U
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#define MAX32_DMA_SLOT_USB_RX3 0x13U
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#define MAX32_DMA_SLOT_USB_RX4 0x14U
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#define MAX32_DMA_SLOT_USB_RX5 0x15U
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#define MAX32_DMA_SLOT_USB_RX6 0x16U
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#define MAX32_DMA_SLOT_USB_RX7 0x17U
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#define MAX32_DMA_SLOT_USB_RX8 0x18U
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#define MAX32_DMA_SLOT_USB_RX9 0x19U
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#define MAX32_DMA_SLOT_USB_RX10 0x1AU
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#define MAX32_DMA_SLOT_USB_RX11 0x1BU
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#define MAX32_DMA_SLOT_SPI0_TX 0x21U
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#define MAX32_DMA_SLOT_SPI1_TX 0x22U
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#define MAX32_DMA_SLOT_SPI2_TX 0x23U
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#define MAX32_DMA_SLOT_UART0_TX 0x24U
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#define MAX32_DMA_SLOT_UART1_TX 0x25U
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#define MAX32_DMA_SLOT_I2C0_TX 0x27U
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#define MAX32_DMA_SLOT_I2C1_TX 0x28U
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#define MAX32_DMA_SLOT_UART2_TX 0x2EU
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#define MAX32_DMA_SLOT_SPI3_TX 0x2FU
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#define MAX32_DMA_SLOT_SPI_MSS_TX 0x30U
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#define MAX32_DMA_SLOT_USB_TX1 0x31U
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#define MAX32_DMA_SLOT_USB_TX2 0x32U
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#define MAX32_DMA_SLOT_USB_TX3 0x33U
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#define MAX32_DMA_SLOT_USB_TX4 0x34U
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#define MAX32_DMA_SLOT_USB_TX5 0x35U
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#define MAX32_DMA_SLOT_USB_TX6 0x36U
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#define MAX32_DMA_SLOT_USB_TX7 0x37U
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#define MAX32_DMA_SLOT_USB_TX8 0x38U
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#define MAX32_DMA_SLOT_USB_TX9 0x39U
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#define MAX32_DMA_SLOT_USB_TX10 0x3AU
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#define MAX32_DMA_SLOT_USB_TX11 0x3BU
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_ */
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