dts: arm: adi: max32650: Add more peripheral nodes

This commit adds following updates to MAX32650 SoC:
- Divide SRAM to sections according to UG.
- Add DMA and SPI nodes
- Add WDT nodes without adding clock property
- Include dma binding to SoC dts file.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Signed-off-by: Burak Babaoglu <burak.babaoglu@analog.com>
This commit is contained in:
Furkan Akkiz 2025-04-21 16:08:54 +03:00 committed by Fabio Baltieri
commit 40a60a6ac2
2 changed files with 154 additions and 4 deletions

View file

@ -6,10 +6,7 @@
#include <arm/armv7-m.dtsi>
#include <adi/max32/max32xxx.dtsi>
&sram0 {
reg = <0x20000000 DT_SIZE_M(1)>;
};
#include <zephyr/dt-bindings/dma/max32650_dma.h>
&flash0 {
reg = <0x10000000 DT_SIZE_M(3)>;
@ -30,6 +27,8 @@
/delete-node/ &trng;
/delete-node/ &wdt0;
&pinctrl {
reg = <0x40008000 0x4000>;
@ -57,6 +56,36 @@
/* MAX32650 extra peripherals. */
/ {
soc {
sram1: memory@20008000 {
compatible = "mmio-sram";
reg = <0x20008000 DT_SIZE_K(64)>;
};
sram2: memory@20018000 {
compatible = "mmio-sram";
reg = <0x20018000 DT_SIZE_K(32)>;
};
sram3: memory@20020000 {
compatible = "mmio-sram";
reg = <0x20020000 DT_SIZE_K(128)>;
};
sram4: memory@20040000 {
compatible = "mmio-sram";
reg = <0x20040000 DT_SIZE_K(256)>;
};
sram5: memory@20080000 {
compatible = "mmio-sram";
reg = <0x20080000 DT_SIZE_K(256)>;
};
sram6: memory@200c0000 {
compatible = "mmio-sram";
reg = <0x200c0000 DT_SIZE_K(256)>;
};
trng: trng@400b5000 {
compatible = "adi,max32-trng";
reg = <0x400b5000 0x1000>;
@ -105,5 +134,72 @@
#pwm-cells = <3>;
};
};
spi0: spi@40046000 {
compatible = "adi,max32-spi";
reg = <0x40046000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
interrupts = <16 0>;
status = "disabled";
};
spi1: spi@40047000 {
compatible = "adi,max32-spi";
reg = <0x40047000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
interrupts = <17 0>;
status = "disabled";
};
spi2: spi@40048000 {
compatible = "adi,max32-spi";
reg = <0x40048000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 8>;
interrupts = <18 0>;
status = "disabled";
};
spi3: spi@400be000 {
compatible = "adi,max32-spi";
reg = <0x400be000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS1 14>;
interrupts = <56 0>;
status = "disabled";
};
wdt0: watchdog@40003000 {
compatible = "adi,max32-watchdog";
reg = <0x40003000 0x400>;
interrupts = <1 0>;
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
status = "disabled";
};
wdt1: watchdog@40003400 {
compatible = "adi,max32-watchdog";
reg = <0x40003400 0x400>;
interrupts = <57 0>;
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
status = "disabled";
};
dma0: dma@40028000 {
compatible = "adi,max32-dma";
reg = <0x40028000 0x1000>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>,
<72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>;
dma-channels = <16>;
status = "disabled";
#dma-cells = <2>;
};
};
};

View file

@ -0,0 +1,54 @@
/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#define MAX32_DMA_SLOT_SPI0_RX 0x01U
#define MAX32_DMA_SLOT_SPI1_RX 0x02U
#define MAX32_DMA_SLOT_SPI2_RX 0x03U
#define MAX32_DMA_SLOT_UART0_RX 0x04U
#define MAX32_DMA_SLOT_UART1_RX 0x05U
#define MAX32_DMA_SLOT_I2C0_RX 0x07U
#define MAX32_DMA_SLOT_I2C1_RX 0x08U
#define MAX32_DMA_SLOT_ADC 0x09U
#define MAX32_DMA_SLOT_UART2_RX 0x0EU
#define MAX32_DMA_SLOT_SPI3_RX 0x0FU
#define MAX32_DMA_SLOT_SPI_MSS_RX 0x10U
#define MAX32_DMA_SLOT_USB_RX1 0x11U
#define MAX32_DMA_SLOT_USB_RX2 0x12U
#define MAX32_DMA_SLOT_USB_RX3 0x13U
#define MAX32_DMA_SLOT_USB_RX4 0x14U
#define MAX32_DMA_SLOT_USB_RX5 0x15U
#define MAX32_DMA_SLOT_USB_RX6 0x16U
#define MAX32_DMA_SLOT_USB_RX7 0x17U
#define MAX32_DMA_SLOT_USB_RX8 0x18U
#define MAX32_DMA_SLOT_USB_RX9 0x19U
#define MAX32_DMA_SLOT_USB_RX10 0x1AU
#define MAX32_DMA_SLOT_USB_RX11 0x1BU
#define MAX32_DMA_SLOT_SPI0_TX 0x21U
#define MAX32_DMA_SLOT_SPI1_TX 0x22U
#define MAX32_DMA_SLOT_SPI2_TX 0x23U
#define MAX32_DMA_SLOT_UART0_TX 0x24U
#define MAX32_DMA_SLOT_UART1_TX 0x25U
#define MAX32_DMA_SLOT_I2C0_TX 0x27U
#define MAX32_DMA_SLOT_I2C1_TX 0x28U
#define MAX32_DMA_SLOT_UART2_TX 0x2EU
#define MAX32_DMA_SLOT_SPI3_TX 0x2FU
#define MAX32_DMA_SLOT_SPI_MSS_TX 0x30U
#define MAX32_DMA_SLOT_USB_TX1 0x31U
#define MAX32_DMA_SLOT_USB_TX2 0x32U
#define MAX32_DMA_SLOT_USB_TX3 0x33U
#define MAX32_DMA_SLOT_USB_TX4 0x34U
#define MAX32_DMA_SLOT_USB_TX5 0x35U
#define MAX32_DMA_SLOT_USB_TX6 0x36U
#define MAX32_DMA_SLOT_USB_TX7 0x37U
#define MAX32_DMA_SLOT_USB_TX8 0x38U
#define MAX32_DMA_SLOT_USB_TX9 0x39U
#define MAX32_DMA_SLOT_USB_TX10 0x3AU
#define MAX32_DMA_SLOT_USB_TX11 0x3BU
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_ */