CC1200 is a sub-ghz chip supporting 6 ISM & SRD bands: 169, 433, 470,
868, 915 and 920 MHz, with features dedicated to IEEE 802.15.4(g).
Current driver enables CC1200 against actual IEEE 802.15.4 Soft-MAC. 'g'
version support in the Soft-MAC will follow later.
The chip itself is closer to a bare metal radio modem than to a usual
15.4 chip: up to the user to provide the right RF settings for the
carrier band. Such settings can be generaten through TI's SmartRF tool.
Hopefully, for channel selection, this driver will be clever enough to
compute the proper register change without any special input from the
user. This will work for all the bands supported by the chip.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Wrong buffer assigned for receiving the last 2 bytes in multi
byte reception of STM32F4 i2c driver. Change the buffer to
correct one.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This reverts commit 2a7efb7419.
"choice" section in board Kconfig.defconfig introduces a dependency
from the sensor to the board. As a consequence a warning was generated
whenever the sensor was used on another board.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This reverts commit 2e20f49167.
"choice" section in board Kconfig.default introduces a dependency
from the sensor to the board. Then a warning was generated
whenever the sensor is used on another board
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The SAM0 series has up to 6 SPI ports. Add Kconfig options to match.
Similar to the 9033fb2f01, this patch
only defines the fields that are currently used and skips ones like
GPIO and IRQ priority that aren't.
Signed-off-by: Michael Hope <mlhx@google.com>
It appears the STM32F411XE doesn't support RNG so remove enabling it
from the SoC defconfig and flag an error if attempting to build the
driver on that SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
According to STM32F4 reference manual, software should wait for BTF=1
before reading N-2 data byte.
Reference:
"For N >2 -byte reception, from N-2 data reception" section, page
853 of STM32F4 Reference manual.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The SAM0 has a 64 byte page (the programing unit) with 4 pages to a
row (the erase unit). This driver implements a read/modify/write to
emulate the byte level writes used by NFFS.
Signed-off-by: Michael Hope <mlhx@google.com>
In STM32 family, RNG IP is available only on F4 and L4 series.
Besides STM32F401 does not support is neither.
Get entropy driver available on STM32 devices supporting it and
generate a compilation issue on STM32 devices that do not own
the RNG IP.
Solves #5448
Signed-Off-By: Erwan Gouriou <erwan.gouriou@linaro.org>
On STM32L4 SoCs RNG is clocked by 48MHz domain.
Hence, besides clock activation, it requires 48M
domain to be enabled.
Tested on:
*nucleo_l476rg
*stm32l476g_disco
*disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SPI_MODE_GET() returns a bitfield. It is thus wrong to test if a bit is
set using the equality operator. The bit-wise AND operator must be used
instead.
This can be tested by setting the SPI in mode 3 (CPOL + CPHA). Currently
both tests will fail and the result is a SPI configured in mode 0. This
was confirmed using an oscilloscope. Applying the patch fixes the
polarity.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
We can have a spurious error while performing a transfer using IRQ. This
happens when the last message of the transfer is a read with a STOP
condition. We must disable the RX interrupt while waiting for the STOP
interrupt, otherwise we will get a spurious RX interrupt which will lead
to an error.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
STM32 UART driver uses a macro for clock initialization, that
is difficult to read and incompatible with needed changes to
fix STM32F0 series UART problems.
This change switches to using the full clock bus names in UART
init functions removing the macro-magic and increasing
readability.
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
The combination of
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL and
CONFIG_CLOCK_STM32_PLL_SRC_HSI
on SOCs with PREDIV1 support made use of the LL define
LL_RCC_PLLSOURCE_HSI_DIV_2, which is not defined for SOCs with
PREDIV1 support.
This exchanges LL_RCC_PLLSOURCE_HSI_DIV_2 with LL_RCC_PLLSOURCE_HSI
which is the appropiate source according to stm32f0xx_ll_rcc.h
line 473 and stm32f3xx_ll_rcc.h line 795.
Tested by compiling hello world for nucleo_f091rc board with HSI as
PLLSOURCE.
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
Instead of accessing the environment variable ZEPHYR_BASE every time we
require accessing the source code root, use an intermediate variable
that has OS path separators correctly set to '/' to avoid issues on
Windows.
Note: This removes the ZEPHYR_SOURCE_DIR CMake variable. External
applications using that will need to change to use the new ZEPHYR_BASE
variable.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Old reference on driver's specific raw mode was still lurking around.
Removing those.
Fixes#5270
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A very old reference to former net stack was still lurking around.
Removing it.
Taking the opportunity to clear up dependencies.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Amend stm32 ethernet driver with small changes:
*Provide HAL_ETH_Init return value in error message,
return on error and move it before thread creation
*Provide computed MAC address in debug message
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This was validated on the cc3220sf_launchxl board
using the Zephyr thermometer sample program
adapted to call the i2c driver directly, and fetching
samples from the on-board TMP006 temperature sensor.
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
This patch adds the driver for Panasonic AMG88xx
infrared array sensor.
The driver was developed within the framework of a student
internship in the development department. The task of the
student was to implement the trigger part of the driver,
transfer and visualization of the measured data.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Of these, only struct net_ipv6_nbr_data::send_ns is a descriptive
change:
send_ns is used for timing Neighbor Solicitations in general, not
just for DAD.
The rest are typo/grammar fixes.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The PIO cores on Altera Nios-II processors can be used
for GPIOs and each PIO core can be configured as Input only,
Output only or as Bidirectional port from the Qsys tool.
The present Nios-II softcpu image on the Zephyr only has the
support for Output only port and the PIOs[0:3] are wired to
LED[0:3] on the Altera MAX10 board.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
In ARC's SecureShield, a new secure mode (currently only em) is added.
The secure/normal mode is orthogonal to kernel/user mode. The
differences between secure mode and normal mode are following:
* different irq stack frame. so need to change the definition of
_irq_stack_frame, assembly code.
* new aux regs, e.g, secure status(SEC_STAT), secure vector base
(VECT_BASE_S)
* interrupts and exceptions, secure mode has its own vector base;
interrupt can be configured as secure or normal through the
interrupt priority aux reg.
* secure timers. Two secure timers (secure timer 0 and timer 1) are
added.Here, for simplicity and backwards compatibility original
internal timers (timer 0 and timer1) are used as sys clock of zephyr
* on reset, the processor is in secure mode and secure vector base is
used.
Note: the mix of secure and normal mode is not supported, i.e. it's
assumed that the processor is always in secure mode.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Some drivers doesn't implement flash API page layout extension
which is causing the application crash once the API was calling.
This patch introduce system termination for this in those drivers
which doesn't implement extension. This will help to discover this
problem early.
It is not done by preprocessor check because it is possible to have
enabled a driver which support and a driver which doesn't support
this API simultaneously.
Now FLASH_PAGE_LAYOUT configuration option is accessible only in case
that at last one driver which implements mentioned API is enabled.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
On stm32f3_disco pins PF0/PF1 are used for OSC_IN/OSC_OUT
signals. Use pins PA9/PA10 for I2C_2 port
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Add the STM32F0 Embedded Flash support in the flash_stm32 driver
interface.
The STM32F0 has a particularity or use the HSI as clock source
for the flash controller interface, so this clock must be
enabled directly in the case HSE or another clock is used by
the system clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
