We use the sector size rather than the page size as some
modules that consumes the flash page layout (such as FCB)
assume the page size is the minimal size they can erase.
Signed-off-by: Olivier Martin <olivier.martin@proglove.de>
This is a follow-up to commit b3ca789ef25627bcf7b02ec2aa7fa900fba37227.
Apparently, another driver needed to be updated but this was not caught
up in CI builds at that time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Modem driver for WNCM14A2A was erroneously leaving the
selection of UART_INTERRUPT_DRIVEN up to CONSOLE_HANDLER.
Now, with the move to the new SHELL backend, this is no
longer happening.
Let's select it from the modem driver, instead of depending
on it.
Let's also add a dependency on SERIAL_SUPPORT_INTERRUPT
which the serial drivers enable to let us know
UART_INTERRUPT_DRIVEN is available.
Signed-off-by: Michael Scott <mike@foundries.io>
When users are configuring applications they are given the option
to enable the DesignWare SPI driver. But they should not be given this
option on SoCs that don't have the DesignWare SPI HW.
This commit hides the driver by default by introducing the config
option HAS_SPI_DW.
Fixes: #10825
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds a flash driver for the Atmel SAM E70 SoC. The driver has
been kept simple by considering that the flash is only composed of 8-KiB
blocks. Indeed an area at the beginning of the flash might be erased
with a smaller granularity, and the other blocks can also be erased with
a higher granularity. It also only handles the global read/write
protection, not the 128-KiB lock regions. A write error is returned if
a region is locked.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Enables Networking hardware on i.MX-RT type drivers.
Reuses the same eth_mcux driver used by Kinetis family; initialization
sequence refactored to work with this board as well. Unlike Kinetis
family, i.MX has a single ENET interrupt and we need to discriminate
between interrupts using a status register.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The Zephyr console and shell interrupt processing assumes
a TX interrupt is evoked upon first enabling the TX
interrupt via uart_irq_tx_enable.
This was not the case with the cc32xx uart, coming out of
reset, with FIFO's disabled.
The only way found to achieve this behavior is to fill
the fifo with a non-printable character on initialization.
Also, the uart driver was explicitly clearing TX/RX interrupts in
its isr, which was unnecessary, as the act of reading/writing
did that implicitly.
These fixes allow the cc32xx uart to work with the
current Zephyr console/shell design.
Fixes: #11202
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
The commit 0c2ef4ea3d "drivers:
watchdog: Watchdog API redesign" introduced an API redesign for the
watchdog drivers compliant with Zephyr.
This patch updated the CMSDK Watchdog driver to be compliant with the
new API.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Convert the Atmel SAM0 watchdog driver to the new watchdog API and
enable DTS support.
This fixes#10914.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add driver for i.MX Messaging Unit peripheral which can be used for
i.MX6SoloX, i.MX7D and other i.MX socs.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
If the configuration is already installed, there will no need to
reconfigure the controller all over again.
This was missing for mcux_dspi, mcux_lspi, sam and sam0.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Now that the in tree user of cc2520 uses device tree to configure SPI
and GPIO params, we can remove and convert the driver to utilize DT
only. This means removing the Kconfig options that come from DT and
rename CONFIG_ to DT_ for those options.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
All drivers require DTS for their primary SPI settings.
Removing SPI_[0-9]_NAME config option added some more samples changes.
Usage of these options there was anyway not relevant.
Fixes#11064
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all SPI controllers support DTS we can remove the Kconfig
support for non-DTS options. We also cleanup some defines that should
have be DT_MCR20A_ instead of CONFIG_MCR20A_.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The majority of cases of CONFIG_I2C_x_IRQ_PRI should be
DT_I2C_x_IRQ_PRI. So go ahead and fix them up. Only the i2c_nios
driver still uses Kconfig for getting priority.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
1. There's an expectations that TX ready (i.e. TX buffer space
available) interrupt is a level interrupt, i.e. always active
while there's TX buffer space available. In particular, there's
an expectation that after uart_irq_tx_enable(), the TX interrupt
will immediately fire (assuming free TX buffer space is available).
But CMSDK UART interrupt appears to be edge interrupt, firing only
on buffer state change. So, after irq_tx_enable(), we need to
"bootstrap" interrupt processing by calling user-defined ISR
manually (the ISR will see that TX ready to accept a new char,
will write it there, then we'll get interrupt once TX buffer is
ready again).
2. Interrupts should be acknowledges only after user ISR is called,
because the ISR will check the status of interrupts.
3. Update stale comments.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The majority of bits where already in place, but some minor support
get the driver name from DTS was needed. Now we select HAS_DTS_WDT
for the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to avoid changing the signature of spi_context_cs_control
function, which is used in every driver, let's just make it an alias to
a new version.
Fixes#10344
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Avoid nested C++ comments inside the C comment block due to MISRA-C
rule 3.1. Add ellipsis around the explanatory text instead.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Now that k_mem_slabs are tracked as kernel objects,
even though they have no user facing API, we can now
accept a pointer to one in the configure API.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The API wants a pointer to the memory block pointer for
some reason (even though it's unnecessary to the
implementation).
Compiler won't warn if a void * is passed instead of a
void **.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If we just had the kernel's implementation, we could
just move this to lib/, but possible arch-specific
implementations dictate that we just make this a
syscall.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These changes modify the function of reading port/pin,
function return logical sum of input pin value and
output pin values for a given port. It is now possible
to read the status of pins set as output.
Signed-off-by: Kamil Gawor <Kamil.Gawor@nordicsemi.no>
Allow to set debug also for RAW_CHANNEL and set general debug template
instead of networking one.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Move to using Kconfig (like other Atmel SAM drivers do) to specify the
pinmux setting for SAMe70 SoCs. Updated the sam_e70_xplained board to
set the default in Kconfig.defconfig instead of via board.h
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converts the adxl362 sensor driver to get the device name and spi slave
properties from the device tree rather than Kconfig. Updates the
build_all test accordingly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
We still have one platform using (for now) the pre-asm2 integration
where the timer interrupt was handled via custom assembly. It calls a
function named "_timer_int_handler" always, not the one we register
with IRQ_CONNECT.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This driver is inspired from the w25qxxdv SPI NOR flash driver which was
already implementing the CFI (Common Flash Interface) for its purpose.
To handle other NOR flash a flash id table (as Linux do) which contains
the geometry for a few SPI NOR flash based on their JEDEC ID has been
introduced.
We currently support the following flash:
- W25Q80
- W25Q16
- W25Q32
- S25FL216K
- MX25UM512
The read and write functions are able to handle more then one page at a
time and return the number of bytes read or write.
Also because every NOR flash expect to disable the write protection
before writing or erasing, the write enable command is now part of the
write and erase functions.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Rewritten Xtensa CCOUNT driver along the lines of all the other new
drivers. The new API permits much smaller code.
Notably: The Xtensa counter is a 32 bit up-counter with a comparator
register. It's in some sense the archetype of this kind of timer as
it's the simplest of the bunch (everything else has quirks: NRF is
very slow and 24 bit, HPET has a runtime frequency detection, RISC-V
is 64 bit...). I should have written this one first.
Note also that this includes a blacklist of the xtensa architecture on
the tests/driver/ipm test. I'm getting spurious failures there where
a k_sem_take() call with a non-zero timeout is being made out of the
console output code in interrupt context. This seems to have nothing
to do with the timer; I suspect it's because the old timer drivers
would (incorrectly!) call z_clock_announce() in non-interrupt context
in some contexts (e.g. "expiring really soon"). Apparently this test
(or something in the IPM or Xtensa console code) was somehow relying
on that on Xtensa. But IPM is a Quark thing and there's no particular
reason to run this test there.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten driver along the lines of all the other new drivers,
implementing the new timer API. Structurally, the machine timer is an
up-counter with comparator, so it works broadly the same way HPET and
NRF do. The quirk here is that it's a 64 bit counter, which needs a
little more care.
Unlike the other timer reworks, this driver has grown by a few lines
as it used to be very simple. But in exchange, we get full tickless
support on the platform.
Fixes#10609 in the process (the 64 bit timer registers are unlatched
for sub-word transfers, so you have to use careful ordering).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reworked using the older hardware interface code, but with an
implementation of the new API only. Much smaller & simpler.
As yet, tested (manually) only on a nrf52_pca10056 board.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten along the lines of ARM SysTick. Implements only the new,
simplified API. MUCH smaller. Works with tickless pervasively. No
loss of functionality.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
