i2c: stm32_ll: add support for STM32F0 with combined irq
The STM32F0 has only a single IRQ line, add a combined IRQ handler. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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7e2fd68b1f
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59d33b5f27
4 changed files with 47 additions and 6 deletions
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@ -114,14 +114,14 @@ config I2C_STM32_V1
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driver also supports the F2 and L1 series.
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config I2C_STM32_V2
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bool "STM32 V2 Driver (F3/L4X)"
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bool "STM32 V2 Driver (F0/F3/L4X)"
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depends on SOC_FAMILY_STM32
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depends on SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X
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depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X
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select HAS_DTS_I2C
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default n
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help
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Enable I2C support on the STM32 F3 and L4X family of processors. This
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driver also supports the F0, F7 and L0 series.
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Enable I2C support on the STM32 F0, F3 and L4X family of processors.
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This driver also supports the F7 and L0 series.
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config I2C_STM32_INTERRUPT
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bool "STM32 MCU I2C Interrupt Support"
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@ -130,6 +130,11 @@ config I2C_STM32_INTERRUPT
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help
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Enable Interrupt support for the I2C Driver
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config I2C_STM32_COMBINED_INTERRUPT
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bool
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depends on I2C_STM32_INTERRUPT
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default y if SOC_SERIES_STM32F0X
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config I2C_BITBANG
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bool
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default n
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@ -142,6 +142,7 @@ static int i2c_stm32_init(struct device *dev)
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/*
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* STM32F0/3 I2C's independent clock source supports only
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* HSI and SYSCLK, not APB1. We force I2C clock source to SYSCLK.
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* I2C2 on STM32F0 uses APB1 clock as I2C clock source
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*/
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switch ((u32_t)cfg->i2c) {
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@ -151,11 +152,11 @@ static int i2c_stm32_init(struct device *dev)
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break;
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#endif /* CONFIG_I2C_1 */
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#ifdef CONFIG_I2C_2
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#if defined(CONFIG_SOC_SERIES_STM32F3X) && defined(CONFIG_I2C_2)
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case CONFIG_I2C_2_BASE_ADDRESS:
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LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_SYSCLK);
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break;
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#endif /* CONFIG_I2C_2 */
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#endif /* CONFIG_SOC_SERIES_STM32F3X && CONFIG_I2C_2 */
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#ifdef CONFIG_I2C_3
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case CONFIG_I2C_3_BASE_ADDRESS:
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@ -204,6 +205,11 @@ DEVICE_AND_API_INIT(i2c_stm32_1, CONFIG_I2C_1_NAME, &i2c_stm32_init,
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_1(struct device *dev)
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{
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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IRQ_CONNECT(CONFIG_I2C_1_COMBINED_IRQ, CONFIG_I2C_1_COMBINED_IRQ_PRI,
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stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(CONFIG_I2C_1_COMBINED_IRQ);
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#else
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IRQ_CONNECT(CONFIG_I2C_1_EVENT_IRQ, CONFIG_I2C_1_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(CONFIG_I2C_1_EVENT_IRQ);
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@ -211,6 +217,7 @@ static void i2c_stm32_irq_config_func_1(struct device *dev)
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IRQ_CONNECT(CONFIG_I2C_1_ERROR_IRQ, CONFIG_I2C_1_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_1), 0);
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irq_enable(CONFIG_I2C_1_ERROR_IRQ);
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#endif
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}
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#endif
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@ -244,6 +251,11 @@ DEVICE_AND_API_INIT(i2c_stm32_2, CONFIG_I2C_2_NAME, &i2c_stm32_init,
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static void i2c_stm32_irq_config_func_2(struct device *dev)
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{
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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IRQ_CONNECT(CONFIG_I2C_2_COMBINED_IRQ, CONFIG_I2C_2_COMBINED_IRQ_PRI,
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stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(CONFIG_I2C_2_COMBINED_IRQ);
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#else
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IRQ_CONNECT(CONFIG_I2C_2_EVENT_IRQ, CONFIG_I2C_2_EVENT_IRQ_PRI,
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stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(CONFIG_I2C_2_EVENT_IRQ);
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@ -251,6 +263,7 @@ static void i2c_stm32_irq_config_func_2(struct device *dev)
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IRQ_CONNECT(CONFIG_I2C_2_ERROR_IRQ, CONFIG_I2C_2_ERROR_IRQ_PRI,
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stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0);
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irq_enable(CONFIG_I2C_2_ERROR_IRQ);
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#endif
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}
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#endif
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@ -50,6 +50,9 @@ s32_t stm32_i2c_configure_timing(struct device *dev, u32_t clk);
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void stm32_i2c_event_isr(void *arg);
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void stm32_i2c_error_isr(void *arg);
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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void stm32_i2c_combined_isr(void *arg);
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#endif
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#define DEV_DATA(dev) ((struct i2c_stm32_data * const)(dev)->driver_data)
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#define DEV_CFG(dev) \
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@ -120,6 +120,7 @@ error:
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k_sem_give(&data->device_sync_sem);
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}
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#ifndef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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void stm32_i2c_error_isr(void *arg)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG((struct device *)arg);
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@ -135,6 +136,25 @@ void stm32_i2c_error_isr(void *arg)
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k_sem_give(&data->device_sync_sem);
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}
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#endif
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#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
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void stm32_i2c_combined_isr(void *arg)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG((struct device *)arg);
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struct i2c_stm32_data *data = DEV_DATA((struct device *)arg);
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I2C_TypeDef *i2c = cfg->i2c;
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if (LL_I2C_IsActiveFlag_NACK(i2c)) {
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LL_I2C_ClearFlag_NACK(i2c);
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data->current.is_nack = 1;
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k_sem_give(&data->device_sync_sem);
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} else {
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stm32_i2c_event_isr(arg);
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}
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}
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#endif
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int stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, uint16_t slave)
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