* Use if, endif to scope the configuration options.
* Add an option to use mbedtls_ct_memcmp instead of memcmp.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Adds AES GCM and CCM support to the STM32 crypto driver.
As the implementation has only been validated on a
limited number of STM32 SoCs, it is enabled only
for platforms that set the DT boolean property
`gcm_ccm_supported`.
Note: To use CCM with additional authenticated data (AD),
the heap memory pool size must be large enough to
accommodate the AD length, rounded up to the nearest
multiple of 16 bytes. For an AD length of 8 bytes,
the heap size must be at least 16 bytes. For an AD
length of 17 bytes, you'll need at least 32 bytes.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Device semaphore handling is being moved out of the do_aes function.
This is necessary to support upcoming GCM and CCM modes,
which require the semaphore to be held during tag generation.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Calling MXC_USB_Ackstat(0) immediately on SETUP receipt causes the
hardware to send the STATUS IN ZLP autonomously. The host then
issues the next SETUP before the Zephyr stack enqueues its own
STATUS IN.
Fix by deferring MXC_USB_Ackstat(0) to udc_event_xfer_in() when
the stack enqueues the STATUS IN ZLP. A nodata_setup flag tracks
whether the pending transfer is a no-data SETUP status stage.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Add standard Zephyr GPIO driver for Allwinner H618 SoC.
This driver supports pin configuration, reading/writing,
and basic external interrupt configuration.
Signed-off-by: Khai Do <dovankhai97@gmail.com>
- systick: split multi-statement lines into one per line (Zephyr style)
- ch32v103.dtsi: add missing reg property alongside ranges in flash0 node
Signed-off-by: Lucy Wong <mova845@outlook.com>
Extend the WCH RCC clock controller with CH32V10x flash wait-state
configuration. Update the systick driver to handle the V3A register
difference: CTLR.CNTIF is used instead of SR for interrupt clearing.
Signed-off-by: Lucy Wong <mova845@outlook.com>
Add initial clock controller driver support for the Microchip
SmartFusion2 platform.
This commit introduces a SmartFusion2-specific clock control
driver together with the required Devicetree binding definitions
for clock and interrupt integration. The implementation enables
basic clock management infrastructure required for SoC and future
peripheral support.
Signed-off-by: Anton Vynohradov <vynohradov.external@bavariamatic.com>
This works, because the API stayed the same between gecko_sdk and
simplicity_sdk.
This driver allows xg13 SoCs to use an RTCC based counter while the RTCC
peripheral is used for the silabs sleeptimer service.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
The sleeptimer service from the gecko_sdk is a generic API which supports
multiple hardware timer peripherals internally. The reason we want to use
this rather than a Zephyr native driver, is that sleeptimer is what's used
by the power_manager service from the SDK which in turn is used by librail.
Combined with other, future commits, this will allow reducing the power
consumption of gecko_sdk based SoCs while they are idle.
Since the APIs between gecko_sdk and simplicity_sdk are the same, all
that's needed is to adjust the Kconfig dependencies and compile the
relevant sdk code. For now, this supports the RTCC peripheral only, which
is used on efr32mg13p, which is what I test with.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
The NXP MCXE31x Wake-up Unit (WKPU) is register-compatible with the
S32K3 WKPU already supported by the intc_wkpu_nxp_s32 driver: same
register map, base address 0x402B4000, IRQ 83, and 64 wake-up
sources. Bind the MCXE31x WKPU node to that driver by switching its
compatible from the placeholder "nxp,wkpu" (which had no binding or
driver behind it) to "nxp,s32-wkpu".
Every SoC that instantiates this controller exposes 64 wake-up
sources, so generalise NXP_S32_WKPU_SOURCES_MAX to a plain
"default 64" instead of a per-SoC-series default; the range 32-64
still lets a future 32-source part override it.
The node lives in the shared nxp_mcxe31x_common.dtsi, so this enables
the WKPU on MCXE315/316/317/31B. The driver source itself is not
modified.
Verified on frdm_mcxe31b: the WKPU device binds and initializes, and
an RTC-timeout event (WKPU internal source 1) triggers the WKPU ISR.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
NXP's USDHC SDK driver knows how to do its own cache maintenance and
does so on platforms that set HAS_MCUX_CACHE[1]. Recently, a copy of
that cache maintenance logic was added on the Zephyr side because
certain cores, like the Cortex-M33 of the i.MX RT1180, use an external
cache controller and instead set HAS_MCUX_XCACHE.
However, the Zephyr-side cache logic is buggy: it clobbers the response
data in cases when the SDK can't use DMA (specifically, when the RX
buffer isn't 4-byte aligned[2]): in those cases, the SDK code writes to
the buffer, those writes go to cache, then Zephyr invalidates the cache
discarding the written data.
NXP's SDK abstracts over different cache drivers just like Zephyr does,
so it's fine to enable its cache control for platforms with any type of
cache. Do that instead of reimplementing cache maintenance in Zephyr.
This partially reverts commit 0b8babdcc3 ("drivers: sdhc: imx_usdhc:
add cache maintenance on DMA path"), leaving only the new default value
for CONFIG_SDHC_BUFFER_ALIGNMENT.
[1] 2d8b1b1133/modules/hal_nxp/mcux/CMakeLists.txt (L140-L142)
[2] cddb388583/mcux/mcux-sdk-ng/drivers/usdhc/fsl_usdhc.c (L1343-L1346)
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
airoc_mgmt_scan() sets data->scan_rslt_cb before calling whd_wifi_scan().
If whd_wifi_scan() fails, the function returnes -EAGAIN without clearing
scan_rslt_cb. The next scan request may return -EINPROGRESS even if no scan
was actually running.
Clear data->scan_rslt_cb in the whd_wifi_scan() error path so driver
state remains consistent.
Signed-off-by: Daniele Cloralio <d.cloralio@arduino.cc>
The ADTM is a superset of the GPTM and has the same core register
layout. See section 11.2.2 of the CH32V003RM for details on the
differences.
Use the same technique as the GD32 driver, i.e. use the same basic
driver with tweaks based on the features.
Add the common 3x GTPM and 1x ADTM Devicetree and pinctrl entries for
the 20x and 30x series and the extra 1x GPTM for the CH32V208 used in
linkw. I can follow up with the other chips in a separate PR.
Tested on the ch32v006evt and linkw by running
`samples/basic/blinky_pwm` and `tests/drivers/pwm/pwm_api` and
checking the output with a logic analyser.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Wire the gdma driver to the esp32p4 AXI and AHB DMA instances,
selecting the per-bus LL calls and 8-byte aligned descriptors so
both buses work through the common driver.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Right now, the SBI hard-codes the usage of ld/sd instructions, which are
not available on 32-bit platforms. This commit changes this to sr/lr from
`asm_macros.inc`, which automatically resolves them to proper load/store
instructions on 32-bit and 64-bit configurations. It also ensures proper
timer handling through 32-bit registers.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Co-authored-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Add counter capture support to the GP-Timer driver. A GPIO edge is
routed through the ETM to the timer capture task, latching the counter
value in hardware. Only available on ETM capable SoCs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a missing RTIO completion notification in STM32 I2C v1 RTIO driver
when a device acts in dual mod controller/target and switches to
target mode for data transfer.
Fixes: #112472
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Extend the VBAT driver to support VDDCORE channel on more STM32 series:
- STM32H7R/S
- STM32MP2
- STM32N6
- STM32U3
This is achieved by using different LL APIs which seem more portable
(with the exception of STM32H5 series on which they are not available!)
Adding actual DTSI nodes for the sensors will be done in other commits.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Implement a common function to validate a DAC channel ID (and translate
it to an "index" value, ultimately used to obtain the LL channel value).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The number of channels supported by an instance is a fixed value so it
can be saved in the instance configuration instead of the instance data.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The RTC API does not seem to disallow an alarm matching both a specific
day of the month **and** a specific day of the week at the same time.
However, the STM32 RTC hardware only supports ONE of these two criteria
at a time. Add a check in the STM32 RTC driver to reject attempts to
configure an alarm matching both criteria at the same time.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
This adds word alignment for the shell_out_buffer that may be used
in the log_output_func function that can use fast copying
for word alignment memory.
Signed-off-by: Kamil Jawański-Gawor <kjgawor@baylibre.com>
The low-speed channel update latches the preceding register writes and
can stall for milliseconds if an interrupt preempts the sequence. Lock
interrupts around the start and stop sequences to keep them atomic.
Signed-off-by: Sylvio Alves <sylviojalves@gmail.com>
Note: Control and Bulk transfers only
Add initial usb host driver for Synopsys DWC2 with vendor quirks.
Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
Get core revision:
Different core revisions require different handling.
To have an option to get the revision and apply different
logic add the possibility to read masked revision from
GSNPSID register.
Set PHY Low Power Clock Select:
For the HS UTMI+ PHY interface uses 48MHz for Low speed devices,
instead of 480 MHz. We need to configure this after port
completed a reset.
Frame number:
Add HFNUM register FRNUM field getter, to allow getting the frame
number for the USB host purposes.
Signed-off-by: Roman Leonov <jam_roma@yahoo.com>
In case of FSL_FEATURE_USDHC_HAS_NO_VS18 is definied,
kUSDHC_SupportV180Flag is not defined in fsl_usdhc.h, so it will has
compile issue, the fix is to make 1.8v support to be false in case of
FSL_FEATURE_USDHC_HAS_NO_VS18 is definied.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Update syscall validation handlers to only validate that API != NULL
if the API is required. Optional APIs have runtime NULL checks in
their implementations, so only permissions and subsystem type needs
to be validated.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
On ESP32-P4 the ROM selects XTAL as the console UART source, and XTAL
is independent of the CPU and PLL frequency. Keep the console on XTAL
across the CPU clock change instead of re-sourcing it to PLL_F80M: that
reference clock is later gated by esp_perip_clk_init(), which would
otherwise leave the console without a clock and stall the first
transmit.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the MCUX_EQDC_CLK, MCUX_EQDC0_CLK and MCUX_EQDC1_CLK clock ids and
handle them in the lpc-syscon clock controller so each EQDC instance's
peripheral clock can be enabled, disabled and have its rate queried.
EQDC is clocked from the AHB bus clock on MCXA, so get_rate returns
CLOCK_GetFreq(kCLOCK_BusClk). The handling is guarded by CONFIG_EQDC_MCUX
and is required by the EQDC sensor driver. Free clock ids (0x36 for the
single-instance id, 0x37 for the EQDC0/EQDC1 dual-instance parts) are
used to avoid colliding with the existing CRC clock id.
Co-authored-by: bnina-ayoub <ouba.bnina@gmail.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a sensor driver for the NXP MCUX Enhanced Quadrature Decoder (EQDC)
using the fsl_eqdc HAL. The PHASEA/PHASEB decoder inputs are routed
through the on-chip INPUTMUX, described by an "inputmux-connections"
phandle-array following the nxp,inputmux convention.
The driver exposes SENSOR_CHAN_ROTATION, SENSOR_CHAN_RPM,
SENSOR_CHAN_ENCODER_COUNT and SENSOR_CHAN_ENCODER_REVOLUTIONS; the last
channel is added to the sensor API. Velocity uses the EQDC period
measurement (POSDH/POSDPERH), so a prescaler keeps the 16-bit period
counter from saturating at the sample rate.
A single-phase-mode property selects single-phase decode (one count per
PHASEA pulse, with the direction taken from PHASEB) instead of the
default quadrature X4 decoding, with the counts-per-revolution scaling
adjusted accordingly.
Co-authored-by: bnina-ayoub <ouba.bnina@gmail.com>
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Use constants defined in hal_ti for decimation value. This is because
nromally, the value written to reg = decimation rate - 1. So the true
values of decimation rate are 1 to 8, while the value written to reg is
0-7.
The TRM for L series states the following:
```
A decimation rate of decimate-by-4 (DECIM_RATE=0x3) or greater is required
to obtain the minimum entropy which is required to pass the NIST SP800-22
statistical test suite. TI recommends using decimate-by-4 or greater when
using the TRNG in cryptographic applications.
```
This change also fixes the default value to be decimate-by-4 instead of
decimate-by-5 (since previously, it was denoting value written to reg,
not decimation rate).
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
The dt property `ti,clk-div` specifies the clock divider, which is used
to calibrate trng frequency as a fraction of MCLK. This should be used
to calculate true TRNG frequency.
DL_TRNG_CLOCK_DIVIDE_%i is the mapping to CLKDIV register, and thus is
clock divider - 1. So in case clock divider is set to 1 (i.e. use the
base MCLK frequency), TRNG_CLOCK_DIVIDE_RATIO is 0, and
TRNG_SAMPLE_GENERATE_TIME is either 0 or undefined depending on the
order things are parsed, which is incorrect either way.
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add an optional cellular_get_stats() returning a struct of cumulative
counters, gated on CONFIG_MODEM_CELLULAR_STATS.
Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
Based on the DS18B20 driver. Only the temperature sensor functionality is
exposed by this driver, not eeprom access nor parasite power configuration.
Signed-off-by: Tomas Groth Christensen <tgc@foss.dk>
Generalize the I2C/SPI interface for CS40L26/27 and CS40L5x drivers
and provide a common I2C/SPI implementation for all drivers to use.
Propagates changes to CS40L26/27 and CS40L5x drivers.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Add Hall-effect pulse-output flow meter driver. An ISR increments a
64-bit pulse counter implemented as two 32-bit atomics (low word and
high word) with wraparound detection.
Volume thresholds are stored as a snapshot of the low pulse counter at
arm time plus a delta in pulses. The ISR fires when the unsigned 32-bit
difference (current - snapshot) reaches the delta, which is inherently
wraparound-safe. Sub-pulse thresholds are clamped to one pulse. The
threshold trigger is one-shot: it disarms on firing or when a NULL
handler is registered. Work is deferred to the system workqueue to avoid
running the handler in ISR context.
SENSOR_CHAN_VOLUME reports accumulated volume in liters since boot.
SENSOR_CHAN_FLOW_RATE reports instantaneous flow in L/min, computed at
sample_fetch time from the delta pulse count and elapsed time since the
previous fetch. SENSOR_ATTR_CALIBRATION provides a runtime override for
the pulses-per-liter calibration value. An optional power GPIO can be
asserted at init to enable the sensor module.
Signed-off-by: Nicolas Belin <nbelin@baylibre.com>
Add a controller and PHY driver for the BL808 UHS PSRAM. The PHY read/write
eye is calibrated at boot by sweeping the DQS/DQ delay taps and latency, so
any supported rate works without per-rate constants. Add the devicetree
nodes and enable on the M1S Dock.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add the UHS PLL, a dedicated PLL that feeds only the UHS PSRAM PHY. It is
outside the system clock tree and brought up on demand; the output
frequency comes from the clk_uhspll devicetree node.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Register structs rely on the compiler emitting 32-bit volatile accesses
and on the struct layout staying in sync with the hardware. sys_read32
and sys_write32 make the access width explicit, work with DEVICE_MMIO
address mapping, and match the convention used by in-tree drivers.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Register structs rely on the compiler emitting 32-bit volatile accesses
and on the struct layout staying in sync with the hardware. sys_read32
and sys_write32 make the access width explicit, work with DEVICE_MMIO
address mapping, and match the convention used by in-tree drivers.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Register structs rely on the compiler emitting 32-bit volatile accesses
and on the struct layout staying in sync with the hardware. sys_read32
and sys_write32 make the access width explicit, work with DEVICE_MMIO
address mapping, and match the convention used by in-tree drivers.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
