Fixes the same issue addressed in #114981 but for CS40L26. For
CS40L26, this issue leads to malformed masks for the first
IRQ register and then IRQ storms. This is only a problem when
disabling runtime PM because otherwise the power sequencer
correctly writes IRQ masks when exiting hibernation.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
BT_USERCHAN is currently limited to BOARD_NATIVE_SIM, but the
driver is implemented for native simulator based targets that use
the native host environment rather than for that specific board.
Bluetooth host-only applications can be built separately from the
controller and communicate with an external controller over HCI.
Allow native simulator based targets to use the same userchan HCI
transport when the application devicetree selects a
zephyr,bt-hci-userchan device.
Relax the dependency from BOARD_NATIVE_SIM to NATIVE_LIBRARY so
host-only Bluetooth applications can use userchan on native simulator
based targets, including out-of-tree boards, when they run in real
time.
This enables split host/controller simulation setups where the
Bluetooth host runs as one native simulator process and connects
over userchan to an external HCI controller process.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
The expression 'drv_data->clk_dev' is invalid because the pointer
'drv_data' is not declared anywhere. Since 'nrf_clock_control_release()'
is the counterpart to 'nrf_clock_control_request()', the pointer part
'drv_data->' can be safely removed.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Move radio test and FICR programming shell commands into the nRF70
Wi-Fi driver. Register the command sets behind NRF70_RADIO_TEST_SHELL
and NRF70_RADIO_TEST_FICR_SHELL Kconfig options so radio test builds
can use the built-in shell or provide a custom integration.
Signed-off-by: Sachin D Kulkarni <Sachin.Kulkarni@nordicsemi.no>
Assisted-by: Cursor:cursor-agent
Instead of including the header containing the generic implementation of
certain arch services, include the top-level <zephyr/arch/cpu.h> header
which will provide the correct implementation for the target arch.
Notably important for `sys_io.h` which has memory barriers on Cortex-A.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Generic snps,dwc2 instances do not have the vendor quirk data/config
objects emitted by the vendor-specific quirk headers. The driver already
allowed the quirk table pointer to be NULL, but still initialized
quirk_data and quirk_config unconditionally. This causes generic-only
instances to fail to build because the corresponding vendor symbols do
not exist.
Use the same vendor-quirk condition for the table, data, and config
pointers so generic instances get NULL quirk pointers.
Fixes: 89a75416b7 ("drivers: usb: uhc_dwc2: add initial support")
Signed-off-by: Duc Viet Le <levietduc0712@gmail.com>
Advertise ETHERNET_HW_VLAN when CONFIG_NET_VLAN is enabled. The
capability is an acceptance gate that permits VLAN interfaces on the
iface. The L2 keeps inserting the tag in software, so the transmit
path needs no offload change.
Account for the four extra bytes a single VLAN tag adds to a frame in
the transmit size cap and the receive buffer capacity assert. The MAC
recognizes the VLAN type and extends its own receive length limit by
the same four bytes, so no length register needs adjusting.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Enable the receive checksum offload engine through the MAC_CONFIGURATION
IPC bit so the MAC verifies the IPv4 header and the TCP and UDP checksums
of incoming frames, and advertise ETHERNET_HW_RX_CHKSUM_OFFLOAD so the
stack does not repeat the check in software. Because the stack then trusts
the offload, drop any frame the engine flags with an IP header or payload
checksum error in the RDES1 write-back status, which is valid only when
the receive status word is present.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
The stack computes the IPv4 header and the TCP and UDP checksums in
software for every transmitted frame. On the MCXN947 Cortex-M33 that
per-packet cost is the largest single consumer of CPU on the transmit
path and it saturates the core well below the link rate.
The DesignWare Ethernet QoS MAC can insert these checksums in hardware.
Set the TDES3 checksum insertion control field to full insertion on the
first descriptor of every frame and advertise ETHERNET_HW_TX_CHKSUM_OFFLOAD
so the stack leaves the checksum fields cleared for the engine to fill.
The MAC only rewrites IP frames with a known protocol and leaves other
frames untouched, so the control field can be set unconditionally.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Query the frequency of the OTG_HS PHY and compute the appropriate CLKSEL
value at runtime if the `clock-reference` property is not specified.
This removes the user burden of providing the same value twice in DTS.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a clock_control driver for the CLKOUT feature of the Series
2/3 Clock Management Unit. The driver configures shared properties
such as exportclk and clkout dividers, and interprets the
subsys argument to clock management functions as the clock output
to enable or disable.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Instead of using a hardcoded FSEL for 24 MHz input, query the frequency
of the USBPHYC clock and determine the correct value automatically at
runtime.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The clock signal `hsi_div2_osc_ck` should be documented as a distinct
source because it is derived from the HSE clock with a configurable
prescaler.
Document the exact effect of `hse-div2` on st,stm32n6-hse-clock in the
binding: it enables the prescaler for `hse_div2_osc_ck` whose frequency
is `hse_osc_ck / 2` when enabled, and `hse_osc_ck` otherwise. Add new
clock source `STM32_SRC_HSE_DIV2_OSC` in stm32n6_clock.h, and update the
corresponding clock control driver to handle this new source.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Enable the esp32 Wi-Fi driver on the ESP32-C61: extend the FTM
and mesh Kconfig gates, add the wifi devicetree node and enable
it on the esp32c61_devkitc board.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When CONFIG_NET_TEST is enabled the PPP driver drops the packet in
ppp_send() because there is no UART to write it to. That leaves the
tests with no way of checking what the PPP stack actually sends.
Add an optional callback, registered with
ppp_driver_register_send_cb(), that is invoked with the outgoing packet
before it is dropped. The callback is only compiled in for
CONFIG_NET_TEST builds and nothing changes when it is not registered.
Assisted-by: Claude:claude-sonnet-5 Simantic
Signed-off-by: Ahnaf Shahriar <shahriarahnaf007@gmail.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This capability was deprecated in Zephyr 3.6 (see issue #63670): every
OT-capable driver implements transmission directly from a low-power
state, so the bit conveyed no information and only coupled the radio
API to OpenThread's capability and device model.
Drop it from the radio API and from the four drivers still advertising
it, and renumber the subsequent capability bits. The OpenThread
platform glue now behaves as if the capability were always present: it
unconditionally advertises OT_RADIO_CAPS_SLEEP_TO_TX and allows
transmitting from the sleep state.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
Remove enabling of the HW RNG and its interrupts from configure_rng()
local helper function. It is already done from acquire_rng() that
is always called when the RNG is used. For consistency, enable RNG
and its interrupts only once it's configured.
This is more consistent with the RNG disabling sequence that is
implemented in release_rng() local helper function.
A side effect it that the RNG is no more enabled at device initialization
which allowed it the accumulate entropy to serve quicker its first
consumer, at least on single-core MCUs.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add some assertion and inline comment to clarify when the HSEM shall be
taken and released to ease maintenance. HSEM acquisition/release
sequences must be consistent knowing that there are no reference
counting support in HSEM management.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Merge entropy_stm32_resume() into acquire_rng() and
entropy_stm32_suspend() into release_rng() to make the implementation
a bit more easy to read.
Remove semaphore acquisition from release_rng() (previously inside
entropy_stm32_suspend() sequence) since the function is only
called when the semaphore was already acquired.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Move configure_rng() local function definition in entropy_stm32.c
source file to ease factorization in other local helper functions.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove entropy_stm32_resume() return value as it is not used and
we don't expect enabling of the RNG clock to fail.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
On STM32WBAX series we must wait a few cycle before disabling the RNG
clock once it is switched off. Clarify the sequence implementation
so that RNG clock remains enable but semaphore is released. This change
addresses an issue where entropy_stm32_suspend() return value was
not used.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Allow project configuration to select use of either the Zephyr system
workqueue or a dedicated workqueue for fillings the random bytes pools.
By default, the driver uses the Zephyr system workqueue. Projects
can enable CONFIG_ENTROPY_STM32_WORKQUEUE and tune ENTROPY_STM32_WQ_PRIO
to use the dedicated wrokqueue.
Workqueue is configured only at POST_KERNEL initcall level, considering
that the driver init level depends on the STM32 SoC used (i.e. when
IRQLESS_TRNG local macro is enabled or not).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Split the initialization function in 2 and call only hardware
initialization on S2RAM resume to fix an issue where S2RAM resume
previously called entropy_stm32_rng_init() and corrupted some software
resource like the system workqueue by calling k_work_init() on an
existing and possibly submitted work.
Prevent entry in PM suspend state unless the ISR random sample pools
are filled so that any interrupt requesting random bytes at wakeup have
a chance to get random bytes. As a side effect, this change makes
entropy_stm32_rng_pm_action() much simpler.
Rename device driver initialization function for consistency.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
#112908 killed any other use-case besides openthread for the mcxw72 radio.
This patch fixes the dependency to only the vendor-specific radio use-case
of openthread.
Signed-off-by: Vincent van der Locht <vincent@synchronicit.nl>
Chain-loaded STM32N6 applications may execute from external XSPI NOR or
PSRAM whose controller depends on the bootloader clock tree. Add an opt-in
MCUboot configuration that preserves the retained RCC state while keeping
the SRAM gates required by the application.
Require the application devicetree to describe retained clock and external
memory hardware. Refresh SystemCoreClock without reinitializing the
application-domain oscillators, PLLs, interconnect, prescalers, ICs, or
SYSCLK.
Tests: git diff --check
Tests: python3 scripts/ci/check_compliance.py -c origin/main..HEAD
Assisted-by: OpenCode:gpt-5.6-sol
Signed-off-by: Tobias Meyer <tobias.meyer@hula.earth>
Connect every SERCOM interrupt line the devicetree node declares via
LISTIFY(DT_INST_NUM_IRQS), instead of a fixed index 0-3 subset
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Update comments, log messages, Kconfig prose, and driver-local
identifiers to use the controller/target terminology ratified by
coding guideline A.2 and already used by the Zephyr I2C API.
Identifiers mirroring the TI driverlib
(e.g. MAP_I2CMaster* / I2CMaster* driverlib functions, I2C_MASTER_CMD_*
driverlib command macros, I2C_MASTER_ERR_* driverlib error macros) are
kept unchanged.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
counter_ns_to_ticks(), counter_ticks_to_ns(), counter_get_frequency_64()
and the other _64 entry points are declared and implemented
unconditionally, but their verifiers were compiled only under
CONFIG_COUNTER_64BITS_TICKS or CONFIG_COUNTER_64BITS_FREQ, so in other
builds they had no handler at all.
Move those verifiers out of the Kconfig guards. counter_get_value_64()
and counter_set_value_64() use K_SYSCALL_OBJ() because their driver op
is optional and the implementation already returns -ENOSYS when it is
absent; set_top_value_64, set_channel_alarm_64 and get_top_value_64
keep the driver-op check where those ops are defined.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
esp_ieee802154_frame_info_t has no member named "time"; the field is
"timestamp". Broken since the code was added (seemingly an errant copy
paste from the nrf5 driver).
Fixes building with CONFIG_NET_PKT_TIMESTAMP=y.
Signed-off-by: Mark H. Spatz <mspatz@leaflabs.com>
The EG915U hardware design requires PWRKEY to be driven low for at
least 2 s to turn the module on and for at least 3 s to turn it off.
The driver applies power_pulse_duration_ms to both the power-on and
the power-off pulse, so the current 2000 ms only satisfies the turn-on
requirement: a power-off request releases PWRKEY after 2 s, the module
ignores the pulse and keeps running while the driver moves on to
AWAIT_POWER_OFF and reports the device as suspended.
Raise the pulse to 3100 ms, which meets both minimums with a small
margin, as already done for the Fibocom LE250 (3200 ms) and the Telit
xEx10x families (5050 ms).
Not built and not run on hardware.
Signed-off-by: Gabriel Germano <gabriel.germano@edge.ufal.br>
The driver defined, deactivated and dialled PDP context 1
unconditionally, hardcoded in the core APN script and in every vendor
dial script. A module whose own functions already own that context, such
as a host-facing network function that activates context 1 by itself,
refuses a dial for the same context and answers NO CARRIER, and the
leading AT+CGACT=0,<cid> tears that other session down on the way.
Add CONFIG_MODEM_CELLULAR_PDP_CONTEXT_ID and thread it through
AT+CGDCONT, AT+CGACT, ATD and the Sierra Wireless AT+KCNXCFG connection
profile, which uses the same identifier. Vendors that dial without a
context or deactivate every context are left alone. The default of 1
keeps the emitted commands byte-identical.
Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
Hold the Ethernet MAC in reset while the pins, the PHY interface mode
and the clocks are configured and release it once the setup is done.
The PHY interface mode must be selected while the MAC is under reset.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
There is only a single BSEC instance, so the upper fuse limit does not
have to be carried around in the driver config. Read it straight from
devicetree and drop the now unused config argument of the accessibility
check.
Assisted-by: Claude:claude-opus-5[1m]
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The STM32MP13 HAL exposes a different BSEC API than the N6 and MP2
ones: the SAFMEM fuse array has to be powered up before a fuse can be
read from it or programmed, and reading a fuse loads it into its
shadow register on the way.
The upper fuses can be accessed from the secure world only, which is
where Zephyr runs as the first stage boot loader, whatever the life
cycle state of the device, so only an invalid state is rejected.
The BSEC clock is enabled through the clock control API, and its rate
is used to select the SAFMEM frequency range on power up.
Assisted-by: Claude:claude-fable-5-1
Assisted-by: Claude:claude-opus-5[1m]
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The BSEC is clocked by pclk5, which can be sourced from HSI, HSE or
PLL2_P and may be prescaled, so its frequency has to be looked up
rather than assumed. Report it through the clock control API so that
the BSEC driver can pick the matching SAFMEM frequency range.
Assisted-by: Claude:claude-opus-5[1m]
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Tickless GRTC skipped the first compare and waited for
sys_clock_set_timeout(). The kernel only calls that when insert
reports a new soon-list head. Wheel timeouts past the later window
never do, so announce never starts and k_sleep latches.
The !TICKLESS guard was the old split, a tickful driver must fire
from boot because set_timeout is a no-op, while tickless assumed the
kernel would program the first real deadline. That first call never
comes if soon stays empty, so drop the guard and always arm one tick
at init, matching SysTick and timer_core_init(). The ISR still only
re-arms itself when TICKLESS=n.
Signed-off-by: Dhruv Menon <dhruvmenon1104@gmail.com>
The ERI ISR only cleared the SCI error flags and the pending IELSR.IR
inside the user_cb!=NULL branch. When an RX error (overrun/framing/
parity) occurs while no interrupt callback is registered yet - e.g. the
window during uart_configure()/R_SCI_UART_Open() before the Zephyr
callback is set - nothing is acknowledged, so the error stays pending
and the ISR re-triggers forever, starving the CPU (uart_configure hangs,
USB never enumerates). Always run err_check() and clear IELSR.IR.
Signed-off-by: Mattia Pennasilico <m.pennasilico@arduino.cc>
Assisted-by: Claude:claude-opus-4.8
The ONFI parameter page stores all fields in little endian byte order.
The driver read them directly from the packed struct, which only yields
the correct values on a little-endian host and would return byte-swapped
geometry and CRC values on a big-endian target.
Convert every multi-byte field on access with sys_le16_to_cpu() and
sys_le32_to_cpu().
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The previous parameter page definition described only ONFI revision 5.2
and folded every field that does not exist in 5.2 into opaque reserved
gaps and an electrical_parameters blob. Many NAND flashes in the field
still implement ONFI 1.0, whose parameter page places different
information at those offsets, so those bytes could not be interpreted.
Cover the full range from ONFI 1.0 to 6.0. Replace the opaque reserved
and blob members of struct spi_nand_onfi_parameter_page with the
individual fields defined across all revisions, such as the partial page
geometry and timing parameters. Annotate each field with the ONFI
revision range in which it is valid so that users can tell which
members a device of a given revision actually populates.
The field offsets and the overall 256 byte layout are unchanged, so the
existing BUILD_ASSERT still holds and no reader is affected.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The accel and gyro full-scale setters passed the raw field encoding
(0-3 / 0-7) as the value to a register update whose mask is the
FS_SEL field at bits 7:5, so the masked value was always 0 and the
part stayed at +/-16 g and +/-2000 dps while software scaled for the
requested range. Wrap the value in FIELD_PREP and widen the masks to
the 3-bit field the datasheet defines.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The accelerometer sensitivity shift was hardcoded to 10, which matches
neither the selected full-scale range nor the part's 16-bit output
(2048 LSB/g at +/-16 g, i.e. a shift of 11), making every reading twice
too large. Derive the shift from the selected range and write the
full-scale selection into the correct bit field so the two agree.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The fractional part was computed with an unsigned modulo while the
integer part used signed division, so for negative raw values the two
halves used different quotients and the result was one full unit too
high. Compute the value in signed micro-units and let
sensor_value_from_micro() split it consistently.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The pressure trigger setup passed ~int_mask to
inv_icp201xx_set_press_notification_config(), whose argument bits are
cleared from the whole INT_MASK register, so the stray bits set by the
bitwise NOT also un-masked the FIFO watermark, overflow and underflow
sources. Restrict the inverted mask to the two pressure bits.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
