renesas_ra_eth_tx() used k_sem_take(&ctx->tx_sem, K_NO_WAIT), so once
the TX descriptor ring filled up under sustained bulk traffic, every
subsequent send() returned -ENOBUFS immediately. Zephyr's net_if_tx()
only logs a rate-limited warning on a negative send() status and
drops the packet, with no retry or backoff. TCP was left to detect
and recover the loss itself via duplicate-ACK fast retransmit or,
when a burst overran the ring by more than one frame, a full RTO
timeout - both cap achievable throughput well below link rate.
Use K_MSEC(ETHER_TX_TIMEOUT_MS), a pre-existing but previously-unused
timeout constant, so the driver blocks briefly for a descriptor to
free up instead of dropping immediately. This gives real backpressure
so TCP's sending rate gets throttled to the actual link drain rate.
Signed-off-by: Henrik Maier <hwmaier@gmail.com>
renesas_ra_eth_tx() called R_ETHER_Write() twice for every packet:
once unconditionally, and again after taking the TX semaphore. The
first call bypassed the semaphore gate entirely, transmitting from
the buffer before the descriptor slot was actually reserved. Move
the semaphore take before the single R_ETHER_Write() call.
Signed-off-by: Henrik Maier <hwmaier@gmail.com>
Fix two error-path bugs in the Agilex FPGA bridge driver:
1. smc_callback() used the result of k_malloc() without checking it.
On heap exhaustion the copy loop dereferences a NULL pointer, and
fpga_config_ready_check() would pass the NULL response buffer to
fpga_reconfig_status_validate(). Return -ENOMEM instead, after
releasing the semaphore so the waiting caller does not block
forever.
2. smc_send() leaked the command and response buffers when
sip_svc_send() failed. Free them before returning -EBUSY.
Signed-off-by: Arbab Haider <arbabhaider649@gmail.com>
Update the existing UART PDL driver to work with the CYT4DN SoC in
the TRAVEO family. This adds CYT4DN-specific clock, interrupt, and
DMA handling using the INFINEON_TRAVEO_FAMILY Kconfig option.
Signed-off-by: Alexpandi Muniyandi <alexpandi@linumiz.com>
Extend the gpio_ports[] table from prt21 up to prt30 for the wider
port range on newer CAT1C SoCs, and generate it with LISTIFY()
instead of a copy-pasted GPIO_PORT_OR_NULL() list. Absent ports
still resolve to NULL, so behaviour is unchanged.
Signed-off-by: Alexpandi Muniyandi <alexpandi@linumiz.com>
Add interrupt controller driver for the Infineon CAT1 CPUSS system
interrupt multiplexer found on TRAVEO T2G series SoCs. The driver
implements the MULTI_LEVEL_INTERRUPTS interface, mapping
system interrupts to NvicMux lines.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
added support for infineon peripheral clock group driver where
driver is enabled for peripheral group instead of peripheral
dividers. so this makes easy to control the clock configuration
and driver also supports to method to define the peripheral clock
divider settings:
- use clock-div dts property for define divider value for static
frequency meaning it is not changing at runtime. divider value is
set at peripheral clock driver init time.
- second method is runtime clock frequency setting for that absence
of clock-div property in the respective peripheral divider is fall
into this method
Peripheral will define clock property with peripheral divider node
along with the peripheral clk/peripheral mux id.
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
added clock driver support for Infineon Traveo series MCU
this driver handles oscillators, pll configuration and
high frequency clocks.
Traveo series MCU has 3-cores,1 Cortex-M0P and 2 Cortex-M7/M4.
Cortex-M0P is main CPU which is going to set clock for M7/M4
cpus, enable M7/M4 cpus. So driver is designed that the clock
configuration part is handled by Cortex-M0P, only other cpus
are just consumer of the configured clock. Currently this driver
supports ECO oscillator configuration, other oscillators will be
supported in future.
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
eeprom_range_is_valid() tested only (offset + len) <= size. off_t is
signed and len unsigned, so a negative offset with a compensating len
wrapped the sum into range while the subsequent memcpy() addressed
memory before mock_eeprom, letting an unprivileged thread read or write
kernel SRAM. Reject negative offsets and bound-check without overflow.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
When enumerating BARs, a 64-bit BAR occupies two consecutive BAR
register slots (low 32-bit in slot N, high 32-bit in slot N+1).
The loop increments `reg` to skip the high-word slot, but it did
not increment `bar` accordingly. As a result, the loop consumed
two register slots while only counting one BAR, causing subsequent
iterations to read the wrong register (e.g. BAR2 was treated as a
second independent BAR on a Type 1 bridge that only has two slots).
This produced an incorrect size value and a spurious
"Failed memory allocation" error for the phantom BAR..
Fix it by incrementing `bar` alongside `reg` in both early-continue
and normal-exit paths when a 64-bit BAR is detected.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Init left each channel's timer in dual 8-bit PWM mode with
timerCompare = 0, always enabled and its output routed to the pin.
Since a FlexIO timer has no start bit, the pin free-ran at
flexio_clk / prescaler / 2 until the first pwm_set_cycles().
Park it disabled with output zero so the pin stays driven low;
pwm_set_cycles() reprograms it anyway.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The verifiers for uart_poll_out_u16(), uart_tx_u16() and
uart_rx_enable_u16() checked for the 8-bit driver op rather than the
16-bit one the implementation calls, so the check passed for drivers
that provide only the 8-bit op.
Check the matching _u16 op instead. Those ops only exist under
CONFIG_UART_WIDE_DATA, so uart_poll_out_u16() falls back to a plain
object check when it is disabled. uart_poll_in_u16() uses the object
check unconditionally because its implementation already tests the op
for NULL.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
The networking stack splits TCP transmit packets into separate
net_buf fragments for protocol headers and payload.
no memcopy TX in xilinx_axienet requires one DMA SG entry per fragment,
so the maximum fragment count must reflect how the stack actually
builds packets.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
Clock source selection for the 32 kHz clock is now handled by the clock
control driver. Remove the redundant clock source configuration from the
WUT timer driver and rely on the clock control subsystem to provide the
selected source.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Clock source selection for the 32 kHz clock is now handled by the clock
control driver. Remove the redundant clock source configuration from the
WUT driver and rely on the clock control subsystem to provide the
selected source.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Clock source selection for the 32 kHz clock is now handled by the clock
control driver. Remove the redundant clock source configuration from the
RTC driver and rely on the clock control subsystem to provide the
selected source.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Move 32 kHz clock source selection into the clock control driver.
This centralizes clock configuration management and allows peripherals
such as the RTC to rely on the clock control subsystem for 32 kHz
clock source configuration.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
- Fixes building of NXP SRC rev2 hwinfo driver for frdm-imxrt1152.
- The NXP SRC rev2 hwinfo driver unconditionally referenced
SRC_SRSR_WDOG4_RST_B_M7_MASK. But not every RT11xx SoC exposes
a fourth watchdog.
- Guards the WDOG4 reset bit.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
On the C6, UART_SCLK_DEFAULT is PLL_F80M, and programming the UART
clock mux/divider while the PLL is still settling after a cold boot
intermittently latches a wrong effective clock: the port then corrupts
essentially every frame (CRC failures at the frame rate, occasional
merged frames when a delimiter byte is hit) for the entire session.
Warm resets never reproduce it - the PLL is already settled - and
re-running uart_configure() with identical values once the clock tree
is stable heals the port instantly, which pins the fault to the latch,
not the programmed values. Observed on ~50% of cold boots on affected
hardware; bench-validated 2026-08-26.
Source the UART from the always-stable XTAL instead, following the
same reasoning as the existing P4 handling (keep a settle-independent
source) and IDF practice under DFS. The fractional divider keeps
standard rates within ~0.02% from the 40 MHz XTAL.
Signed-off-by: Linus Ruettimann <linus@noxblanc.com>
Add a counter child driver for the Micro Crystal RV-3028 RTC.
The driver provides access to the RV-3028 counter functionality through
the Zephyr counter API and uses the RV3028 MFD parent driver for
register access.
Signed-off-by: Janez Ugovsek <janez@ugovsek.info>
pin_interrupt_configure() cleared the configured pin's stale edge with
WRITE_BIT(base->ISR, pin, 1), which expands to base->ISR |= BIT(pin).
ISR is write-1-to-clear, so that read returns every latched flag on the
port and writing the value back clears them all, discarding the pending
interrupts of every other pin on the same port.
Clear the single flag with a plain write.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Mirror the arch_mem_map() change and give arch_mem_unmap() the same
treatment: change the prototype to return int instead of void, so
architecture code has a consistent way to report unmapping failures.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Previously arch_mem_map() was a void function, so architecture
code had no consistent way to report mapping failures to callers
other than panicking or asserting. Change arch_mem_map() to
return int.
Note that this mostly maintains the k_panic() calls unless
the error is easy to handle (like invalid arguments). Each
architecture will need to be amended in the future to properly
handle the error conditions. Also some of the users are
converted to do k_panic() after failure. This is to keep
the signature change commit easier to review.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rename CONFIG_FLASH_INFINEON_PSOC4 to CONFIG_FLASH_INFINEON_PDL to
support both PSoC4 and PSC3 families. Replace SoC-series ifdefs with
devicetree properties (infineon,explicit-erase, infineon,
cache-invalidate, erase-value) to describe hardware capabilities.
Add explicit erase support for PSC3, per-instance mutex for thread safety,
and cache invalidation after flash operations. Update Kconfig to select
appropriate erase flags. PSoC4 hardware auto-erases on write, while PSC3
requires explicit erase.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
The MSPM0 pinctrl driver called DL_GPIO_initPeripheralFunction() and
DL_GPIO_initPeripheralAnalogFunction() from TI DriverLib to configure
IOMUX PINCM registers. These are single-register writes that can be
expressed directly using sys_write32(), removing the dependency on the
vendor HAL.
The IOMUX base address is obtained from the pinctrl node reg property
via DT_INST_REG_ADDR(0), which now returns the correct hardware address
after the DTS reorganization.
The pinctrl_soc_pin_t iomux field already encodes configuration bits at
positions that match the PINCM hardware register layout, so values can
be written directly without translation.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
MODEM_CELLULAR_EVENT_PPP_DEAD had no case in the await registered state,
so it was discarded. A vendor with no network script enters that state
after a successful dial, with PPP attached and the carrier on, so a drop
reported there as an LCP phase change went unnoticed: the driver settled
into the registered state and stayed there, never re-dialling, because
the periodic script keeps passing on a module that is itself healthy.
Entering that state also clears the dormant flag, taking the interface
operationally up over a dead PDN.
An in-band NO CARRIER is not addressed here, as it raises no event in
this state. The interface stays dormant until the registered state
clears it, so the net_if_carrier_off modem_ppp performs takes it from
dormant to down, which notifies nothing and leaves the PPP L2 phase
unchanged.
Handle the event as the registered state already does, entering await
ppp dead so its existing timeout re-dials.
Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
The modem cellular driver was sending `AT+CGSN` expecting an IMEI to be
returned, but `AT+CGSN` returns the serial number, not the IMEI, which
are not the same as each other for the nRF93M1.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The `AT+CGSN` query has several variants, the base `AT+CGSN` which
returns the `<sn>` without any prefix, and several explicit serial
number types, which include a `+CGSN: ` prefix.
```
AT+CGSN // <sn>, serial number as determined by manufacturer
AT+CGSN=0 // <sn>, serial number as determined by manufacturer
AT+CGSN=1 // <imei> International Mobile station Equipment Identity
AT+CGSN=2 // <imeisv> IMEI & Software Version Number
AT+CGSN=3 // <svn> Software Version Number
```
According to the specification, while `<sn>` is "typically" the IMEI,
manufacturers may choosed to provide whatever information they want in
the response. The new common match objects allows modem to explicitly
request the IMEI, instead of the manufacturer specific `<sn>`.
Reference: 3GPP 27.007 Ch. 5.4.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Output the `CELLULAR_MODEM_INFO_SERIAL_NUMBER` event from inside the
`modem_cellular_chat_on_imei` callback, as the callback runs in response
to `AT+CGSN`, which is documented as returning the serial number, not
IMEI.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Define a new information type for the modem serial number. While the
serial number is often the same as the IMEI, it is not always
(e.g. nRF93M1).
Signed-off-by: Jordan Yates <jordan@embeint.com>
GPIO_OPEN_DRAIN and GPIO_OPEN_SOURCE share the GPIO_SINGLE_ENDED bit and
differ only in GPIO_LINE_OPEN_DRAIN. The open-source rejection test
masked with GPIO_OPEN_SOURCE, which also matches open-drain, so any
attempt to configure a pin as open-drain wrongly returned -ENOTSUP.
Detect open-source on the GPIO_LINE_OPEN_DRAIN bit instead so open-drain
is accepted, and reject open-drain only on RTL8752H: open-drain is
supported on all current and future Bee ICs, and RTL8752H is the sole
older part without a hardware open-drain output mode, so a blacklist is
intentional here.
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Without a deadline the do/while loop can spin forever if the hardware
never asserts the Conversion Ready Flag (e.g. a faulty device). Add a
5-second timeout using k_uptime_get() so the function returns -ETIMEDOUT
instead of hanging, while preserving immediate propagation of I2C errors.
Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
In triggered mode, ina237_sample_fetch() called
ina237_trigg_one_shot_request() which only writes to the ADC_CONFIG
register to start a one-shot conversion, then returned immediately
without waiting for the conversion to complete.
This violates the sensor API contract: after sensor_sample_fetch()
returns, the data must be ready to read via sensor_channel_get().
Fix by polling the DIAG_ALRT register until the CNVRF (Conversion
Ready Flag, bit 1) is set before calling ina2xx_sample_fetch() to
read the converted data.
Fixes#98547
Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
Add an optional TCPC operation reporting whether a port applies the
USB-C dead battery resistors to its CC lines, and implement it for
ucpd_stm32 and ucpd_numaker.
Signed-off-by: Nicholas Cadieux <ncadieux@qti.qualcomm.com>
Add the mbox driver implementation on top of
IPC hw block as a native Zephyr driver.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
The STM32 FMC MIPI DBI driver only supported the Intel 8080 16-bit bus
mode and rejected any other configuration. Displays wired to the FMC
over an 8-bit parallel bus could not be used.
Add support for MIPI_DBI_MODE_8080_BUS_8_BIT:
- Validate the DBI mode against the configured FMC bus width, accepting
both the 8-bit and 16-bit combinations and rejecting mismatches.
- Use 8-bit accesses (sys_write8) for command and data transfers when
the bus is configured in 8-bit mode.
- Compute the data address offset without the extra bit shift in 8-bit
mode, since the register-select line maps directly to the byte
address instead of the half-word address used in 16-bit mode.
Signed-off-by: Michele Vaccari <michele.vaccari@outlook.com>
A frame handed to the ENET QoS transmit DMA when the link goes down is
never written back, so the completion interrupt that returns the packet
and frees the single transmit slot never arrives. The slot stays taken
across the link coming back, every later send on the interface fails
with -EBUSY, and the packet and its fragments are gone from their pools
for good, so a handful of link transitions exhaust the buffer pool and
the interface stops transmitting.
Give the driver a claim and release pair so that completion and
abandonment race for the packet and exactly one of them returns it, and
arm a transmit watchdog, CONFIG_ETH_NXP_ENET_QOS_TX_TIMEOUT_MS, that
takes the descriptors back, flushes the transmit queue and reinitializes
the ring when the DMA does not finish. Abandon an outstanding frame from
the PHY callback on carrier loss, and program speed and duplex with the
transmitter and receiver disabled before the carrier is announced, so
the MAC configuration write cannot land on a frame the stack has already
handed to the DMA.
Publish the packet, arm the watchdog and start the DMA as one step under
irq_lock so an abort can never observe a half-built submission, and flush
the transmit queue with a bounded wait.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Every RX descriptor writeback clobbers RDES0, which in read format is
the buffer address: the writeback formats alias it with the VLAN tag or
the timestamp low word. The success path restores it before handing the
descriptor back to the DMA, but the four drop paths (errored frame,
packet alloc failure, bad length, fragment alloc failure) re-arm the
descriptor with whatever the writeback left there, so the next use of
that slot makes the DMA write into flash or reserved address space and
receive stops permanently. Restore the reserved buffer's address on
every drop path, as the success path does.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Allow connecting the `fuel-gauge-composite` instance to a charger
device, to limit the reported SoC to 99% while still charging, and
forcing it to 100% when charging terminates.
Signed-off-by: Jordan Yates <jordan@embeint.com>
If we have a measured current and a configured internal resistance,
adjust the measured voltage to provide a less jumpy state-of-charge
computation under charging conditions.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Set the time for the next sample from the point the sampling finishes,
not from when `composite_get_prop` is called.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add support for the Analog Devices ADIN1140 10BASE-T1S MAC-PHY:
ethernet driver, MDIO bus driver and PHY driver.
Signed-off-by: Raluca Bozdog <raluca.bozdog@analog.com>
Co-authored-by: Jason Murphy <jason.murphy@analog.com>
Add a warning to recommend to move the stm32h5 devices
to the mspi stm32 controller with the mspi stm32 xspi driver.
The flash stm32 xspi driver will be deprecated v4.5.0
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Extend the stm32 flash driver config to the MSPI st,nor compatible
device to enable the external flash in MemoryMapped mode.
This commit checks the KconfigFormat correctly.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a new video driver for NXP FlexIO-based parallel camera
interface (DVP). The driver captures 8-bit parallel pixel data
via FlexIO shifters, with pixel clock (PCLK) gating and horizontal
sync (HREF) line synchronization. Pixel data is transferred to
memory using eDMA, with frame boundaries synchronized via VSYNC
GPIO interrupt. An optional XCLK output can be generated by a FlexIO
timer for camera sensor clock supply.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Enable the esp32 HCI driver on the ESP32-C61: extend the
controller Kconfig gates, report the C61 vendor hardware
variant id, add the hci devicetree node and enable it on the
esp32c61_devkitc board. The C61 BLE controller reuses the C6
controller sources and blobs through the hal.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Currently driver only acknowledged the boot handshake when
TARGET_BOOT_DONE was already asserted.
On a cold boot the virtual wire reads back 0, so the condition never
held and the EC never sent TARGET_BOOT_STS/TARGET_BOOT_DONE together,
leaving the host stalled waiting for boot-load-done.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
