This patch adds driver support for TI ECAP module which can capture an
external input or work as a standalone APWM generator.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Enable the iProc endpoint driver by default when the corresponding
devicetree node is present.
Drop the now-redundant board defconfig selections from the bcm958402m2
variants.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
ADd `brcm,iproc-pcie-ep-v2` to represent the version difference
with `brcm,iproc-pcie-ep`.
This property can replace the CONFIG_PCIE_EP_IPROC_V2.
So, we removed it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Enable the following G1 DAC Kconfig options by default for
Microchip SAM D5x/E5x devices:
- DAC_MCHP_G1_REFRESH
- DAC_MCHP_G1_EXTERNAL_FILTER
- DAC_MCHP_G1_OVERSAMPLING_RATIO
These Kconfig symbols were introduced during the addition
of DAC driver support for PIC32CX SG family devices, but
the default enablement for SAM D5x/E5x devices was missed.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
loading the mac address for stm32 is
the same for all 4 stm32 ethernet drivers,
combine that into a shared function.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Previously Max3421e driver locked and unlocked `uhc_data` mutex by using
`k_mutex_lock()` and `k_mutex_unlock()` instead the already existing
uhc helpers: `uhc_lock_internal()` and `uhc_unlock_internal()`.
Signed-off-by: Benjamin Jurewicz <bjurewicz@internships.antmicro.com>
Some RCP modules (e.g. IW61X) require an asynchronous firmware load
sequence before the 15.4 SPI interface becomes operational.
The firmware is uploaded via a separate transport (e.g. BT UART H4),
Without this option, Zephyr's net_if_post_init() automatically brings up
the OpenThread interface at boot, before the RCP is ready, causing Spinel
command failures and NULL dereferences.
Add CONFIG_HDLC_RCP_IF_SPI_DEFERRED_INIT (default n, preserves existing
behavior) which:
- hdlc_iface_init(): skip ieee802154_init(), set NET_IF_NO_AUTO_START
to block net_if_post_init() from starting the interface
before the RCP is ready.
- hdlc_rcp_if_spi_init(): skip SPI IRQ arming and RCP reset,
- hdlc_deferred_init(): arms the SPI IRQ and clears NET_IF_NO_AUTO_START.
Signed-off-by: Jean-Yves Salaun <jean-yves.salaun@nxp.com>
In hdlc_rcp_if_push_pull_spi(), two cases cause OpenThread Tx
timeouts and RCP resets on the host side.
- RECV_LEN undersized when data->rx_len == 0
When the host sends a frame and no RX is pending, RECV_LEN was
unconditionally set to CONFIG_HDLC_RCP_IF_SPI_SMALL_PACKET_SIZE.
As RECV_LEN is less than tx_len, the RCP does not answer and the
host goes into Tx timeout.
Fix: set RECV_LEN to max(CONFIG_HDLC_RCP_IF_SPI_SMALL_PACKET_SIZE,
tx_len), matching the OpenThread POSIX reference implementation
- No retry when RCP RECV_LEN < tx_len
When peer_max_rx (slave RECV_LEN) < tx_len, the outgoing frame was
silently dropped after logging a warning.
Fix: The host must keep tx_len and tx_ready
to retry on the next SPI transaction.
Signed-off-by: Jean-Yves Salaun <jean-yves.salaun@nxp.com>
Add support for decompressing the initrd before using it as the RAM Disk.
For now, only LZ4 compression is supported.
It is advised to use smaller block sizes for the compressed initrd to
reduce the size of heap memory required for decompression.
Requires adding the lz4 external module on application layer.
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
The driver used a macro which was effectively a reimplementation of the
`_current_cpu` macro, but less safe. Use the real `_current_cpu` macro
directly and drop the driver's handrolled version.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The PMUX register was not being properly cleared before setting
the new mux value. This causes incorrect pin configuration when
the register contains non-zero initial values.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
The siwx91x SPI driver required to wait for a very small amouth of time
(100ns to 50µs).
When CONFIG_PM is enabled, the granularity of k_busy_wait() is not
sufficient (~32µs). So, the driver implement a raw busy loop.
This busy loop depends on the frequency of the CPU. This was wrongly
retrieved from CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
DT_PROP(DT_NODELABEL(cpu0), clock_frequency) is more accurate.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
When the SPI hardware block is use to send data (without receiving any
data), the DMA callback is called when the data are transmitted to the SPI
controller, but before the data are actually sent over the wire.
Then, the chip-select signal could be released while the Tx was still in
progress.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
When processing LE Extended Advertising Report events in
is_hci_event_discardable(), the evt_type field of adv_info[0] may
reside at an unaligned address. This occurs because evt_data can
point to shared memory (e.g., IMU buffer) at an odd address, and
the evt_type (uint16_t) ends up at an odd offset after the packed
struct layout.
On Cortex-M33 with UNALIGN_TRP enabled, this causes a HardFault.
Use sys_le16_to_cpu() to read the evt_type field, which ensures
the compiler generates byte-level access (LDRB) for the packed
struct member, avoiding the unaligned LDRH instruction.
Signed-off-by: Gang Li <gang.li_1@nxp.com>
Add a periodic script that queries the current serving cell info and
broadcasts it out through the `CELLULAR_EVENT_NETWORK_STATUS_CHANGED`
event. Drop the periodic script frequency down to every 30 seconds for
this modem as it is not used as a comms keepalive check.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Subscribe to the CEREG URC that contains more information about the
registration state, specifically the access technology that
`modem_cellular` consumes.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Add generic 3GPP modem queries to the init path so that
`CELLULAR_EVENT_MODEM_INFO_CHANGED` events fire on modem startup. The
SIM card IMSI can only be queried after putting the modem into full
functional mode (`AT+CFUN=1`) and even then only after a short delay.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The nRF93M1 has been observed to take up to 1.5 seconds to send its
"RDY" message after the CMUX disconnect occurs. Set the timeout to
double this value. In normal operation this timeout is never hit, as
the state machine continues on as soon as the "RDY" event is received.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Allow modem driver to explicitly set the timeout for the modem to return
to AT mode after CMUX disconnects. If not specified, it falls back to
the current behaviour (`reset_pulse_duration_ms`).
Signed-off-by: Jordan Yates <jordan@embeint.com>
Some modems output a message after a CMUX session disconnects and it is
ready to accept commands again on the non-multiplexed interface (nRF93M1
for example outputs `RDY`). Update the `INIT_POWER_OFF` handling to
support early exit from this state if a `MODEM_READY` event is received.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Notify all CMUX users that the interface has closed immediately upon
receiving the `CMUX_DISCONNECTED` event, instead of at some arbitrarily
later time point (`reset_pulse_duration_ms` later).
Signed-off-by: Jordan Yates <jordan@embeint.com>
ifx_tcpwm_counter_set_top_value() previously updated only the software
cache (data->value) and never reset the hardware counter register.
After counter_set_top_value() reduced the period (PERIOD register), the
TCPWM CNT register kept its old value. If that value was greater than
the new period, the counter had to wrap the full 16-bit (or 32-bit)
range before terminal count, instead of one new period's worth of
ticks.
This caused tests/drivers/counter/counter_basic_api
test_set_top_value_with_alarm to fail on Infineon TCPWM-based boards:
the test computes its timeout assuming the alarm fires within a few
new periods, but the first turnaround took several seconds (e.g. ~6 s
on a 16-bit counter clocked at 10 kHz).
Reset the hardware counter to 0 after writing the new period. When
COUNTER_TOP_CFG_DONT_RESET is set, return -ETIME if the current value
is already past the new ticks (matching the counter API contract);
also reset to 0 in that case when COUNTER_TOP_CFG_RESET_WHEN_LATE is
set.
Verified on kit_pse84_eval (m33+m55), kit_pse84_ai (m33+m55) and
cyw920829m2evk_02: all counter_basic_api subtests pass.
Assisted-by: GitHub Copilot (Claude)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Switch from a binary semaphore to a mutex with priority inheritance.
Write in chunks (~128 B) so ISRs can run between chunks. Add per-operation
retry logic (up to 3 attempts) to handle transient voltage drops. Add cache
invalidation after write/erase on SoCs with D-cache. Extend HAL dispatch
to cover Apollo2x/3x (am_hal_flash), Apollo4x, and Apollo5x (MRAM).
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
uart drivers, that init in POST_KERNEL and
not in PRE_KERNEL_1 can't support
CONFIG_EARLY_CONSOLE, add a Kconfig for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add support Microchip MEC/XEC mailbox which is an eSPI peripheral
channel device. We modified the eSPI driver header file as follows:
a. Add a mailbox peripheral to the enum for eSPI peripherals.
b. Add custom Host command opcodes to get/set mailbox data using
ACPI EC for host commands.
c. Add ACPI and private event types for Host sending data, command,
or clearing data written to the Host by the EC (OBE).
d. Add a Microchip XEC vendor specific eSPI header with side-band
API's to access the mailbox.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The lptimer unlike every other free running counter and compare has
cascaded 16bit counters and. The cascade happens on a match rather
than on a roll over. This means we cannot simply let the counter0/counter1
cacscade into a 32bit counter with a 32 bit match (compare). Instead use
counter2 as the definitive value on cycle counts and counter0/counter1
as a relative delay.
This costs some time to reset, program the match, and re-enable the
counters but does provide correct behavior. At most we can get a
tick rate of 1/4 the low frequency clock rate with correct behavior.
Simplifies the driver a great deal and adds lots of hopefully helpful
commentary to help the next person understand the design well enough.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
The offload .get hook only populates offload_context when the
ESP-AT interface is the default one at net_context_get() time.
When ESP-AT is a secondary interface, a context can be routed or
bound to it afterwards and reach the offload send, recv, bind and
connect ops with a NULL offload_context, leading to a NULL
dereference.
Allocate the backing socket lazily on first use through a helper
so the driver works regardless of interface ordering, and guard
the put op against a context that never reached the offload layer.
The helper rejects non-IPv4 contexts before claiming a pool slot,
and only claims contexts whose interface is the ESP-AT one so a
context routed to another interface, such as DNS resolved over a
native Ethernet iface, is left for that interface to service.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add selects for GPIO, FLASH, and REGULATOR to the Kconfig
files for the CS40L26/27 and CS40L5x drivers.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
virtq_create() received a pointer to a struct virtq allocated by the
callers via k_malloc(). k_malloc() does not zero memory, so fields such
as lock could contain garbage. When CONFIG_SPIN_VALIDATE is enabled,
taking the spinlock then triggers an assertion because lock.thread_cpu
is non-zero.
Zero the whole struct at the start of virtq_create() so that all fields
are initialized before the descriptor table is set up.
Fixes#112349
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Introduce STM32_LPTIM_* abstraction defines in the LPTIM timer driver to
map HAL1 and HAL2 polarity and preload symbols.
Use the abstraction in polarity and update mode setup so the same code
path works across HAL generations.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Switch the STM32 LPTIM timer driver from SoC-series checks to a
Devicetree compatible check for U5-style LPTIM instances.
Update STM32 dtsi files to advertise "st,stm32u5-lptim" alongside
the legacy compatible so the new detection path is used consistently.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Rename LPTIM LL clear-flag API calls from ClearFLAG_* to ClearFlag_*
in the STM32 LPTIM timer driver.
Add STM32MP1 compatibility aliases so platforms that still expose the
legacy ClearFLAG names keep building and running.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The FIFO error flag is triggered either by wrong configuration
or by overrun/underrun condition. The configuration is handled
by stm32_dma_check_fifo_mburst function. For overrun/underrun
condition, there is no data loss, so it is rather warning
and can be ignored.
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
There is an upcoming MDK change to remove MSPI_TMOD_TMOD_TXANDRX
due to it being redundant. The wrapper TMOD register only needs
to be set in peripheral mode.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Add the ESP32-P4 USB-OTG high-speed controller using the
espressif,esp32-usb-otg-hs binding and the internal UTMI PHY. The
high-speed PHY uses dedicated pins, so no pad configuration is
needed. Enable the controller on the function ev board.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Introduce a shared Espressif USB-OTG binding scheme and rename the
existing full-speed quirk to the speed specific
espressif,esp32-usb-otg-fs compatible. The internal PHY D+/D- pad
numbers now come from the phy-dp-pin and phy-dm-pin device tree
properties, so migrate the esp32s3 node accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Accept MSPI_TIMING_PARAM_DUMMY in api_timing_config() as a
no-op instead of returning -ENOTSUP, allowing device drivers
that call mspi_timing_config() unconditionally to work on
controllers without platform-specific timing calibration.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Implement software auto-CE-break. When mem_boundary and
time_to_break are configured via mspi_dev_config(), sync
transfers are transparently split at address-aligned boundaries
and at a maximum segment size derived from the tCEM time budget.
time_to_break (in µs) is converted to max_clocks_per_ce using
the actual clock rate. At transfer time, command, address, and
dummy phase clocks are subtracted from this budget and the
remaining clocks are converted to a data byte limit, ensuring
no single CE assertion exceeds the device's maximum CE-low time.
Introduce sub_pkt indirection so that start_next_packet() and
handle_fifos() read from a staging packet rather than indexing
directly into the user packet array. This is required for
CE-break splitting, where run_one_packet() constructs synthetic
sub-packets with adjusted address and byte counts that do not
exist in the original xfer.packets array.
Async transfers with CE-break splitting are currently unsupported.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
The DACC_MR_ONE bit has to be set to one in the DAC driver
but it only applies to SAM4S and SAM4E.
SAM3S and SAM3X, SAM3A do on have this bit.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Add vendor quirks for nRF54LM20 PHY configuration for DWC2 in host mode.
Given the PHY is powered from USB, the PHY needs to be configured and
powered on before registers can be accessed or the SoC freezes on any
register access.
Signed-off-by: Josuah Demangeon <josuah.demangeon@nordicsemi.no>
Add interrupt-driven PWM event callback functionality to the TI AM3352
EHRPWM driver. Note that only one event can be enabled at a time, hence we
require all callbacks to have same event trigger or none at all.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
The virtio device enumeration asserts that every advertised queue size is
a power of two. A device may legitimately advertise a zero-size queue for
a feature it does not use (e.g. the virtiofs hiprio queue), which then
trips the assertion under CONFIG_ASSERT. Treat a zero size as "unused"
and skip the power-of-two check for it.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
