clock_control: stm32: add handling of clocks for the stm32mp13
Add enabled_clock, on / off and configure support for the clocks of the stm32mp13. Describes the peripheral clock source selection. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This commit is contained in:
Alain Volmat
Fabio Baltieri
parent
983d891829
commit
88d8003109
3 changed files with 223 additions and 3 deletions
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@ -17,6 +17,29 @@
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/sys/util.h>
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/** @brief Verifies clock is part of active clock configuration */
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int enabled_clock(uint32_t src_clk)
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{
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if ((src_clk == STM32_SRC_HSE && IS_ENABLED(STM32_HSE_ENABLED)) ||
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(src_clk == STM32_SRC_HSI && IS_ENABLED(STM32_HSI_ENABLED)) ||
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(src_clk == STM32_SRC_LSE && IS_ENABLED(STM32_LSE_ENABLED)) ||
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(src_clk == STM32_SRC_LSI && IS_ENABLED(STM32_LSI_ENABLED)) ||
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(src_clk == STM32_SRC_PLL1_P && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL2_P && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL2_Q && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
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(src_clk == STM32_SRC_PLL2_R && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
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(src_clk == STM32_SRC_PLL3_P && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL3_Q && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
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(src_clk == STM32_SRC_PLL3_R && IS_ENABLED(STM32_PLL3_R_ENABLED)) ||
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(src_clk == STM32_SRC_PLL4_P && IS_ENABLED(STM32_PLL4_P_ENABLED)) ||
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(src_clk == STM32_SRC_PLL4_Q && IS_ENABLED(STM32_PLL4_Q_ENABLED)) ||
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(src_clk == STM32_SRC_PLL4_R && IS_ENABLED(STM32_PLL4_R_ENABLED))) {
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return 0;
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}
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return -ENOTSUP;
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}
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static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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@ -57,6 +80,32 @@ static int stm32_clock_control_off(const struct device *dev, clock_control_subsy
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return 0;
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}
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static int stm32_clock_control_configure(const struct device *dev,
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clock_control_subsys_t sub_system,
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void *data)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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int err;
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ARG_UNUSED(dev);
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ARG_UNUSED(data);
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err = enabled_clock(pclken->bus);
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if (err < 0) {
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/* Attempt to configure a src clock not available or not valid */
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return err;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
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STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
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STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
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STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
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STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system, uint32_t *rate)
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{
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@ -99,10 +148,37 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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return 0;
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}
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static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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ARG_UNUSED(dev);
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if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Gated clocks */
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if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
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== pclken->enr) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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} else {
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/* Domain clock sources */
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if (enabled_clock(pclken->bus) == 0) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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}
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}
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static DEVICE_API(clock_control, stm32_clock_control_api) = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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.configure = stm32_clock_control_configure,
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.get_status = stm32_clock_control_get_status,
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};
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static void set_up_fixed_clock_sources(void)
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@ -179,7 +179,8 @@
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay)
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
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#define STM32_PLL_ENABLED 1
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#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
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#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
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@ -215,7 +216,8 @@
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay)
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
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#define STM32_PLL2_ENABLED 1
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#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
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#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
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@ -235,7 +237,8 @@
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay)
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
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DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
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#define STM32_PLL3_ENABLED 1
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#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
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#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
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@ -251,6 +254,20 @@
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#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
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#define STM32_PLL4_ENABLED 1
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#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
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#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
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#define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
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#define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
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#define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
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#define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
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#define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
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#define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
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#define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
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#define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
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#define STM32_PLL_ENABLED 1
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#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
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@ -8,6 +8,24 @@
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#include "stm32_common_clocks.h"
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/** System clock */
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/* defined in stm32_common_clocks.h */
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/** Fixed clocks */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
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/** PLL outputs */
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#define STM32_SRC_PLL1_P (STM32_SRC_HSI + 1)
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#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_P + 1)
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#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
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#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
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#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
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#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
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#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
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#define STM32_SRC_PLL4_P (STM32_SRC_PLL3_R + 1)
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#define STM32_SRC_PLL4_Q (STM32_SRC_PLL4_P + 1)
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#define STM32_SRC_PLL4_R (STM32_SRC_PLL4_Q + 1)
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/** Bus clocks */
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#define STM32_CLOCK_BUS_APB1 0x700
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#define STM32_CLOCK_BUS_APB2 0x708
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@ -24,4 +42,113 @@
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_APB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_AHB6
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/** @brief Device domain clocks selection helpers */
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#define MCO1CFGR_REG 0x460
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#define MCO2CFGR_REG 0x464
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#define I2C12CKSELR_REG 0x600
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#define I2C345CKSELR_REG 0x604
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#define SPI2S1CKSELR_REG 0x608
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#define SPI2S23CKSELR_REG 0x60c
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#define SPI45CKSELR_REG 0x610
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#define UART12CKSELR_REG 0x614
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#define UART35CKSELR_REG 0x618
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#define UART4CKSELR_REG 0x61c
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#define UART6CKSELR_REG 0x620
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#define UART78CKSELR_REG 0x624
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#define LPTIM1CKSELR_REG 0x628
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#define LPTIM23CKSELR_REG 0x62c
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#define LPTIM45CKSELR_REG 0x630
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#define SAI1CKSELR_REG 0x634
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#define SAI2CKSELR_REG 0x638
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#define FDCANCKSELR_REG 0x63c
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#define SPDIFCKSELR_REG 0x640
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#define ADC12CKSELR_REG 0x644
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#define SDMMC12CKSELR_REG 0x648
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#define ETH12CKSELR_REG 0x64c
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#define USBCKSELR_REG 0x650
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#define QSPICKSELR_REG 0x654
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#define FMCCKSELR_REG 0x658
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#define RNG1CKSELR_REG 0x65c
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#define STGENCKSELR_REG 0x660
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#define DCMIPPCKSELR_REG 0x664
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#define SAESCKSELR_REG 0x668
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/** MCO1CFGR / MCO2CFGR devices */
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO1CFGR_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO1CFGR_REG)
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#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO2CFGR_REG)
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#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO2CFGR_REG)
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#define MCOX_ON BIT(12)
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/* MCO1 source */
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#define MCO1_SEL_HSI 0
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#define MCO1_SEL_HSE 1
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#define MCO1_SEL_CSI 2
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#define MCO1_SEL_LSI 3
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#define MCO1_SEL_LSE 4
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/* MCO2 source */
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#define MCO2_SEL_MPU 0
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#define MCO2_SEL_AXI 1
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#define MCO2_SEL_MLAHB 2
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#define MCO2_SEL_PLL4 3
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#define MCO2_SEL_HSE 4
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#define MCO2_SEL_HSI 5
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 0
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#define MCO_PRE_DIV_2 1
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#define MCO_PRE_DIV_3 2
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#define MCO_PRE_DIV_4 3
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#define MCO_PRE_DIV_5 4
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#define MCO_PRE_DIV_6 5
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#define MCO_PRE_DIV_7 6
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#define MCO_PRE_DIV_8 7
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#define MCO_PRE_DIV_9 8
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#define MCO_PRE_DIV_10 9
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#define MCO_PRE_DIV_11 10
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#define MCO_PRE_DIV_12 11
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#define MCO_PRE_DIV_13 12
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#define MCO_PRE_DIV_14 13
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#define MCO_PRE_DIV_15 14
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#define MCO_PRE_DIV_16 15
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#define I2C12_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C12CKSELR_REG)
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#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C345CKSELR_REG)
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#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, I2C345CKSELR_REG)
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#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 6, I2C345CKSELR_REG)
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#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S1CKSELR_REG)
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#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S23CKSELR_REG)
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#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI45CKSELR_REG)
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#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SPI45CKSELR_REG)
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#define UART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART12CKSELR_REG)
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#define UART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, UART12CKSELR_REG)
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#define UART35_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART35CKSELR_REG)
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#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART4CKSELR_REG)
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#define UART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART6CKSELR_REG)
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#define UART78_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART78CKSELR_REG)
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#define LPTIME1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM1CKSELR_REG)
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#define LPTIME2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM23CKSELR_REG)
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#define LPTIME3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, LPTIM23CKSELR_REG)
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#define LPTIME45_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM45CKSELR_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI1CKSELR_REG)
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#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI2CKSELR_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FDCANCKSELR_REG)
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#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SPDIFCKSELR_REG)
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#define ADC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ADC12CKSELR_REG)
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#define ADC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 2, ADC12CKSELR_REG)
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#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SDMMC12CKSELR_REG)
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#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SDMMC12CKSELR_REG)
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#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ETH12CKSELR_REG)
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#define ETH2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 8, ETH12CKSELR_REG)
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#define USBPHY_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, USBCKSELR_REG)
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#define USBOTG_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x1, 4, USBCKSELR_REG)
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#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, QSPICKSELR_REG)
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#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FMCCKSELR_REG)
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#define RNG1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, RNG1CKSELR_REG)
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#define STGEN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, STGENCKSELR_REG)
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#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, DCMIPPCKSELR_REG)
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#define SAES_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SAESCKSELR_REG)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_ */
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