If `CONFIG_SDMMC_STM32_EMMC=y`, the compiler complains about undefined
reference to `HAL_SD_Erase()` because those files are not included in the
build. Unfortunately, if eMMC is installed `CONFIG_SDMMC_STM32_EMMC=n`
is not an option because the SD and eMMC protocols are different enough
that eMMC will not work.
Signed-off-by: Canyon Bliss <canyon@recursivebliss.com>
Validate the chip ID using a switch statement, use correct variant
name for chip id macros and add support for CST820_CHIP_ID (0xB7).
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
This PR allows to use the VOL/MICDET pin to control the DAC volume.
See chapter 6.3.10.3 Volume Control Pin of the datasheet.
Signed-off-by: Stefan Schmidt <kontakt@stefanschmidt-embedded.de>
Add Counter driver support for Renesas RZ/A2M
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add shared code in 'dac_dacx311.c' and configuration files.
Support power mode bits via configuration.
Signed-off-by: Andreas Wolf <awolf002@gmail.com>
This reverts commit 2d17d0c613
as it introduced a failure in main which can be reproduced for example
with
```
mkdir build && cd build
cmake -GNinja -DBOARD=frdm_mcxw71/mcxw716c \
../samples/net/sockets/echo_client/
ninja
```
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
I2C_RTIO, I3C_RTIO and SPI_RTIO should be selected in the driver
itself on the basis of which busses have these devices instances.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The read clear in i2c_dw_error_chk() will misclean the tx_abrt interrupt.
This patch will move the read clear function into the isr handler
to make the transaction flow end normally.
Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
Remove MBOX_TI_SECURE_PROXY_PRIORITY in favor of MBOX_INIT_PRIORITY which
by default is set to 40, which is desirable so that the priority dependency
on interrupt controllers like ARM GICv3 gets fulfilled. This change is for
convenience of building at default priorities.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Change priority from KERNEL_INIT_PRIORITY_OBJECTS to
KERNEL_INIT_PRIORITY_DEFAULT so that the priority dependency on TI secure
proxy mailbox fulfilled.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Change priority from KERNEL_INIT_PRIORITY_OBJECTS to
KERNEL_INIT_PRIORITY_DEFAULT so that the priority dependency on TISCI
protocol/firmware layer gets fulfilled.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
- Deletes virtual "nxp,cmc-reset-cause" compatible,
as it is covered by existing "nxp,cmc".
- Fixes the issue discovered during discussion in
https://github.com/zephyrproject-rtos/zephyr/issues/104464
#issuecomment-3957779329
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
rtio_cqe_consume() can return NULL, but the result is dereferenced
and released without any NULL check. Add a NULL guard to avoid a
NULL pointer dereference, returning -EIO on failure.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
rtio_cqe_release() is called unconditionally after rtio_cqe_consume(),
but if the consume returns NULL, this passes a NULL pointer to the
release function. Move the release call inside the non-NULL branch.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
On the stm32U3 with 512K of flash in a single bank,
reset the BKER bit of the FLASH_CR register.
See RefMan Table Flash module organization"
Note "2. When DUALBANK is set to 0 in the option bytes,
for 512-Kbyte single-bank STM32U375/385 devices,
the flash is addressed as a single bank,
and the page numbers are continuous from 0 to 127.
Set BKER = 0 to select bank 1."
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32U3 series, erase/program operation requires
the voltage range is set to range 1.
This is done before loop on erase/write and the initial voltage
range is restored afterwards.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On the stm32U3, like it is on the stm32U5 series,
gives the exact nb of pages of 4KB depending on the flash size.
For the page layout, the nb of pages does not depends on the
DUALBANK option byte.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add serial driver support for Renesas RZ/G3E
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
The clock initialization for RX devices is not appropriate when it is
placed under the root clock node. Without an external fixed clock on the
board, the clock is never initialized. Therefore, the clock
setup must be handled inside soc_early_init_hook.
Signed-off-by: Y Huynh <y.huynh.xw@renesas.com>
Reconfigure the bandcfg when disabling AP so that the band
configurations are match between hostapd and wifi driver.
Signed-off-by: Hui Bai <hui.bai@nxp.com>
rename gpio_step_dir.c to gpio_step_dir_stepper_ctrl.c
rename h_bridge_stepper.c to h_bridge_stepper_ctrl.c
remover zephyr prefix from gpio_step_dir_stepper_ctrl.c structs
add ctrl suffix to h_bridge_stepper_ctrl.c structs and function
rename in kconfig to match
adds a prefix STEPPER_ in cmake to comply the changes in the kconfig
Signed-off-by: Mustafa Taher <mustafataherramp@gmail.com>
- Enables GPIO input+output mode to enable gpio_api_1pin test
- Retains current pin state when no output init flag specified.
- Adds pull up register validation, sets pull up register in
both pull-up and pull-up+pull-down cases.
Signed-off-by: John Batch <john.batch@infineon.com>
Refactors the drive mode selection logic for input and output pins into
dedicated helper functions.
Signed-off-by: John Batch <john.batch@infineon.com>
Add CCOUNT compensation for time spent in LPM mode (CPU stalled).
Add sys_clock_idle_exit() for dticks announcement when leaving LPM.
Add hooks for SoC specific implementation of LP timer timestamp call.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Modify driver to process interrupts from upper half ISR then signal a
bottom half ISR thread which performs callback invokation. This ensures
callbacks run in thread context which is necessary for proper operation of
various classes.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
In the bt_hci_stm32wba_send() function, in case of the function
bt_buf_get_evt() fails, call k_sem_give() before return.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Restore the channel in the stm32wba_802154_start()
function because channel is reset by the link layer
when the stm32wba_802154_ral_sleep() is called
in the stm32wba_802154_stop() function.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Disable continuous reception when ieee802154 stop
is called.
Configure continuous reception when ieee802154 start
is called.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add FM_Init() function call in the Flash driver initialization
to initialize the Flash Module.
This function is introduced by the STM32Cube_FW_WBA_V1.8.0
release.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
When tickless is enabled, it is necessary to ensure
that lptmr can be set for a period of time instead of generating
an interrupt at one tick.
LPTMR hardware does not synchronize writes to the
compare register (CMR)
If CMR is changed exactly when the counter increments,
the hardware may compare part of the counter against
the old CMR value and part against the new one, leading to TCF
being set incorrectly on some SoCs.
Reorder the update sequence to:
- disable the LPTMR interrupt,
- clear TCF,
- write the new CMR,
- re-enable the interrupt.
This provides a safe workaround for tickless mode case.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Add support for prescaler bypass configuration via devicetree
property. This aligns the timer driver with the counter driver
implementation.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Logic for error handling for CE polarity was inverted, causing
configuration to incorrectly return early without completing
the configuration when a valid CE polarity was provided.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
On MAX32 SoCs, some timer instances can use an external clock input.
This commit ensures that when the external clock is selected as the
source, its frequency is read and used correctly.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
MAX32 timers can optionally use external input/output pins.
Enable pinctrl support in the counter driver so these pins
can be properly configured via device tree.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Properly handle the scenario where the reset GPIO is not connected, and
simply rely on software reset during init.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Now that requesting ACLK made it into PDM driver,
allow it on target with CLKSELECT as long as
clock control is enabled.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Refer to this comment for more information:
https://github.com/zephyrproject-rtos/zephyr/pull/92923#discussion_r2637725041
This patch enables Non-Secure mode support for the RP2350 MBOX
driver. It replaces the hardcoded SIO base address with the address
derived from the devicetree parent node. This allows the driver to
use the correct hardware alias in both Secure and Non-Secure contexts.
Signed-off-by: Raul Hernandez <raul.hernandez@spaceface.dev>
Fix incorrect array index on line 101. Should use cfg_idx (which accounts
for non-contiguous pin layouts) instead of pin when accessing pin_muxes
array elements. This prevents potential out-of-bounds access and ensures
correct pull configuration on i.MX RT118x SOCs.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Remove inclusions that date back to the original addition of this driver
and that are no more required when PSA API is used.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
i3c_ccc_do_setvendor() uses I3C_CCC_VENDOR(false, id) indicating a
direct CCC, but never sets up the target payload with the target's
address. The memset zeros out targets.num_targets and targets.payloads,
so the CCC is sent with no target address.
Add a ccc_tgt_payload with the target's dynamic address and the
write data, matching how i3c_ccc_do_getvendor() is structured.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
i3c_ccc_do_rstdaa() sets rnw = 1 (read) for the directed RSTDAA CCC,
but per the I3C spec RSTDAA is a Direct Write CCC with zero data
bytes. This causes the wrong R/W bit to be driven on the bus header.
Change rnw to 0 to correctly indicate a write operation.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
