arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
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# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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2017-01-19 02:01:01 +01:00
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|
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# SPDX-License-Identifier: Apache-2.0
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
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|
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|
2019-07-17 19:17:05 +02:00
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|
|
menu "RISCV Options"
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depends on RISCV
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
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config ARCH
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string
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2024-02-07 11:23:28 +01:00
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default "riscv"
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arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
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2020-04-08 00:24:36 +02:00
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config FLOAT_HARD
|
2022-03-09 12:05:12 +01:00
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bool "Hard-float calling convention"
|
2020-04-08 00:24:36 +02:00
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default y
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2020-04-23 10:27:24 +02:00
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depends on FPU
|
2020-04-08 00:24:36 +02:00
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help
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This option enables the hard-float calling convention.
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2021-08-16 20:38:33 +02:00
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config RISCV_GP
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2022-03-09 12:05:12 +01:00
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bool "RISC-V global pointer relative addressing"
|
2021-08-16 20:38:33 +02:00
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default n
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help
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Use global pointer relative addressing for small globals declared
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anywhere in the executable. It can benefit performance and reduce
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the code size.
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Note: To support this feature, RISC-V SoC needs to initialize
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global pointer at program start or earlier than any instruction
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using GP relative addressing.
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2022-06-30 14:40:52 +02:00
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config RISCV_ALWAYS_SWITCH_THROUGH_ECALL
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bool "Do not use mret outside a trap handler context"
|
2023-05-30 22:30:56 +02:00
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depends on MULTITHREADING
|
2022-06-30 14:40:52 +02:00
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depends on !RISCV_PMP
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help
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Use mret instruction only when in a trap handler.
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This is for RISC-V implementations that require every mret to be
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balanced with an ecall. This is not required by the RISC-V spec
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and most people should say n here to minimize context switching
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overhead.
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2024-04-02 10:57:04 +02:00
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config RISCV_ENABLE_FRAME_POINTER
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bool
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default y
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depends on OVERRIDE_FRAME_POINTER_DEFAULT && !OMIT_FRAME_POINTER
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help
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Hidden option to simplify access to OVERRIDE_FRAME_POINTER_DEFAULT
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and OMIT_FRAME_POINTER. It is automatically enabled when the frame
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pointer unwinding is enabled.
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config RISCV_EXCEPTION_STACK_TRACE
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bool
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default y
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depends on EXCEPTION_STACK_TRACE
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imply THREAD_STACK_INFO
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help
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Internal config to enable runtime stack traces on fatal exceptions.
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2019-07-17 19:17:05 +02:00
|
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menu "RISCV Processor Options"
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
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config INCLUDE_RESET_VECTOR
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bool "Include Reset vector"
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help
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2018-11-02 23:17:45 +01:00
|
|
|
Include the reset vector stub, which initializes the stack and
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|
|
prepares for running C code.
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
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|
2024-01-03 12:39:36 +01:00
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config RISCV_PRIVILEGED
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bool
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select ARCH_HAS_RAMFUNC_SUPPORT if XIP
|
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help
|
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|
Option selected by SoCs implementing the RISC-V privileged ISA.
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2022-12-27 20:14:51 +01:00
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config RISCV_SOC_HAS_ISR_STACKING
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bool
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depends on !USERSPACE
|
|
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|
|
help
|
|
|
|
|
Enable low-level SOC-specific hardware stacking / unstacking
|
|
|
|
|
operations during ISR. This hidden option needs to be selected by SoC
|
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if this feature is supported.
|
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Some SOCs implement a mechanism for which, on interrupt handling,
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part of the context is automatically saved by the hardware on the
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stack according to a custom ESF format. The same part of the context
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|
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is automatically restored by hardware on mret.
|
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|
Enabling this option requires that the SoC provides a
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|
|
soc_isr_stacking.h header which defines the following:
|
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- SOC_ISR_SW_STACKING: macro guarded by _ASMLANGUAGE called by the
|
|
|
|
|
IRQ wrapper assembly code on ISR entry to save in the ESF the
|
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|
|
remaining part of the context not pushed already on the stack by
|
|
|
|
|
the hardware.
|
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|
|
- SOC_ISR_SW_UNSTACKING: macro guarded by _ASMLANGUAGE called by the
|
|
|
|
|
IRQ wrapper assembly code on ISR exit to restore the part of the
|
|
|
|
|
context from the ESF that won't be restored by hardware on mret.
|
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|
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|
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|
- SOC_ISR_STACKING_ESF_DECLARE: structure declaration for the ESF
|
|
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|
|
guarded by !_ASMLANGUAGE. The ESF should be defined to account for
|
|
|
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|
the hardware stacked registers in the proper order as they are
|
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|
|
saved on the stack by the hardware, and the registers saved by the
|
|
|
|
|
software macros. The structure must be called '__esf'.
|
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|
2023-12-21 13:41:59 +01:00
|
|
|
config RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
|
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bool
|
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|
|
help
|
|
|
|
|
This allows the SoC to overwrite the irq handling. If enabled, the
|
|
|
|
|
function __soc_handle_all_irqs has to be implemented. It shall service
|
|
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|
and clear all pending interrupts.
|
|
|
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|
|
2023-01-03 17:56:18 +01:00
|
|
|
config RISCV_SOC_HAS_CUSTOM_IRQ_LOCK_OPS
|
|
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|
bool
|
|
|
|
|
help
|
|
|
|
|
Hidden option to allow SoC to overwrite arch_irq_lock(),
|
|
|
|
|
arch_irq_unlock() and arch_irq_unlocked() functions with
|
|
|
|
|
platform-specific versions named z_soc_irq_lock(), z_soc_irq_unlock()
|
|
|
|
|
and z_soc_irq_unlocked().
|
|
|
|
|
|
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|
Enable this hidden option and specialize the z_soc_* functions when
|
|
|
|
|
the RISC-V SoC needs to do something different and more than reading and
|
|
|
|
|
writing the mstatus register to lock and unlock the IRQs.
|
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|
|
2023-07-25 11:50:40 +02:00
|
|
|
config RISCV_SOC_HAS_CUSTOM_SYS_IO
|
|
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|
bool
|
|
|
|
|
help
|
|
|
|
|
Hidden option to allow SoC to overwrite sys_read*(), sys_write*() functions with
|
|
|
|
|
platform-specific versions named z_soc_sys_read*() and z_soc_sys_write*().
|
|
|
|
|
|
|
|
|
|
Enable this hidden option and specialize the z_soc_* functions when
|
|
|
|
|
the RISC-V SoC needs to do something different and more than reading and
|
|
|
|
|
writing the registers.
|
|
|
|
|
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
config RISCV_SOC_CONTEXT_SAVE
|
2022-03-09 12:05:12 +01:00
|
|
|
bool "SOC-based context saving in IRQ handlers"
|
2018-12-03 01:46:26 +01:00
|
|
|
select RISCV_SOC_OFFSETS
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
help
|
2018-11-02 05:25:13 +01:00
|
|
|
Enable low-level SOC-specific context management, for SOCs
|
|
|
|
|
with extra state that must be saved when entering an
|
|
|
|
|
interrupt/exception, and restored on exit. If unsure, leave
|
|
|
|
|
this at the default value.
|
|
|
|
|
|
|
|
|
|
Enabling this option requires that the SoC provide a
|
|
|
|
|
soc_context.h header which defines the following macros:
|
|
|
|
|
|
|
|
|
|
- SOC_ESF_MEMBERS: structure component declarations to
|
|
|
|
|
allocate space for. The last such declaration should not
|
|
|
|
|
end in a semicolon, for portability. The generic RISC-V
|
|
|
|
|
architecture code will allocate space for these members in
|
|
|
|
|
a "struct soc_esf" type (typedefed to soc_esf_t), which will
|
|
|
|
|
be available if arch.h is included.
|
|
|
|
|
|
|
|
|
|
- SOC_ESF_INIT: structure contents initializer for struct soc_esf
|
|
|
|
|
state. The last initialized member should not end in a comma.
|
|
|
|
|
|
|
|
|
|
The generic architecture IRQ wrapper will also call
|
2018-12-07 18:29:14 +01:00
|
|
|
\_\_soc_save_context and \_\_soc_restore_context routines at
|
2018-11-02 05:25:13 +01:00
|
|
|
ISR entry and exit, respectively. These should typically
|
|
|
|
|
be implemented in assembly. If they were C functions, they
|
|
|
|
|
would have these signatures:
|
|
|
|
|
|
|
|
|
|
``void __soc_save_context(soc_esf_t *state);``
|
|
|
|
|
|
|
|
|
|
``void __soc_restore_context(soc_esf_t *state);``
|
|
|
|
|
|
|
|
|
|
The calls obey standard calling conventions; i.e., the state
|
|
|
|
|
pointer address is in a0, and ra contains the return address.
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
|
2018-12-03 01:46:26 +01:00
|
|
|
config RISCV_SOC_OFFSETS
|
2022-03-09 12:05:12 +01:00
|
|
|
bool "SOC-based offsets"
|
2018-12-03 01:46:26 +01:00
|
|
|
help
|
|
|
|
|
Enabling this option requires that the SoC provide a soc_offsets.h
|
|
|
|
|
header which defines the following macros:
|
|
|
|
|
|
|
|
|
|
- GEN_SOC_OFFSET_SYMS(): a macro which expands to
|
|
|
|
|
GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
|
|
|
|
|
to ensure offset macros for SOC_ESF_MEMBERS are defined
|
|
|
|
|
in offsets.h. The last one should not end in a semicolon.
|
|
|
|
|
See gen_offset.h for more details.
|
|
|
|
|
|
2024-01-16 16:01:41 +01:00
|
|
|
config RISCV_HAS_PLIC
|
|
|
|
|
bool
|
|
|
|
|
depends on RISCV_PRIVILEGED
|
|
|
|
|
help
|
|
|
|
|
Does the SOC provide support for a Platform Level Interrupt Controller (PLIC).
|
|
|
|
|
|
|
|
|
|
config RISCV_HAS_CLIC
|
|
|
|
|
bool
|
|
|
|
|
depends on RISCV_PRIVILEGED
|
|
|
|
|
help
|
|
|
|
|
Does the SOC provide support for a Core-Local Interrupt Controller (CLIC).
|
|
|
|
|
|
2024-01-16 16:31:26 +01:00
|
|
|
config RISCV_SOC_EXCEPTION_FROM_IRQ
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Option selected by SoCs that require a custom mechanism to check if
|
|
|
|
|
an exception is the result of an interrupt or not. If selected,
|
|
|
|
|
__soc_is_irq() needs to be implemented by the SoC.
|
|
|
|
|
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
config RISCV_SOC_INTERRUPT_INIT
|
2022-03-09 12:05:12 +01:00
|
|
|
bool "SOC-based interrupt initialization"
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
Enable SOC-based interrupt initialization
|
|
|
|
|
(call soc_interrupt_init, within _IntLibInit when enabled)
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
|
2024-01-10 15:53:24 +01:00
|
|
|
config RISCV_MCAUSE_EXCEPTION_MASK
|
2020-03-03 13:27:10 +01:00
|
|
|
hex
|
|
|
|
|
default 0x7FFFFFFFFFFFFFFF if 64BIT
|
|
|
|
|
default 0x7FFFFFFF
|
|
|
|
|
help
|
|
|
|
|
Specify the bits to use for exception code in mcause register.
|
|
|
|
|
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
config RISCV_GENERIC_TOOLCHAIN
|
|
|
|
|
bool "Compile using generic riscv32 toolchain"
|
|
|
|
|
default y
|
|
|
|
|
help
|
2017-12-13 16:08:21 +01:00
|
|
|
Compile using generic riscv32 toolchain.
|
|
|
|
|
Allow SOCs that have custom extended riscv ISA to still
|
|
|
|
|
compile with generic riscv32 toolchain.
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
|
2017-02-13 19:11:54 +01:00
|
|
|
config GEN_ISR_TABLES
|
|
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
config GEN_IRQ_VECTOR_TABLE
|
|
|
|
|
default n
|
|
|
|
|
|
2023-06-07 16:03:45 +02:00
|
|
|
config RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET
|
|
|
|
|
int
|
|
|
|
|
default 0
|
|
|
|
|
depends on GEN_ISR_TABLES
|
|
|
|
|
help
|
|
|
|
|
On some RISCV platform the first interrupt vectors are primarly
|
|
|
|
|
intended for inter-hart interrupt signaling and so retained for that
|
|
|
|
|
purpose and not available. When this option is set, all the IRQ
|
|
|
|
|
vectors are shifted by this offset value when installed into the
|
|
|
|
|
software ISR table and the IRQ vector table. CONFIG_NUM_IRQS must be
|
|
|
|
|
properly sized to take into account this offset. This is a hidden
|
|
|
|
|
option which needs to be set per architecture and left alone.
|
|
|
|
|
|
2019-10-25 12:01:04 +02:00
|
|
|
config NUM_IRQS
|
|
|
|
|
int
|
|
|
|
|
|
2023-01-16 14:53:06 +01:00
|
|
|
config RV_BOOT_HART
|
|
|
|
|
int "Starting HART ID"
|
|
|
|
|
default 0
|
|
|
|
|
help
|
|
|
|
|
This option sets the starting HART ID for the SMP core.
|
|
|
|
|
For RISC-V systems such as MPFS and FU540 this would be set to 1 to
|
|
|
|
|
skip the E51 HART 0 as it is not usable in SMP configurations.
|
|
|
|
|
|
2024-03-07 17:00:36 +01:00
|
|
|
config RISCV_HART_MASK
|
|
|
|
|
int
|
|
|
|
|
default -1
|
|
|
|
|
help
|
|
|
|
|
Configures the mask for the HART ID.
|
|
|
|
|
For RISC-V systems with HART ID starting from non-zero value,
|
|
|
|
|
i.e. 128, 129, ..(0x80, 8x81, ..), this can be configured to 63 (0x7f)
|
|
|
|
|
such that we can extract the bits that start from 0.
|
|
|
|
|
|
2022-05-13 06:00:19 +02:00
|
|
|
config RISCV_PMP
|
2020-07-21 15:59:23 +02:00
|
|
|
bool "RISC-V PMP Support"
|
|
|
|
|
select THREAD_STACK_INFO
|
2020-11-05 23:30:20 +01:00
|
|
|
select CPU_HAS_MPU
|
2022-05-13 06:00:19 +02:00
|
|
|
select ARCH_HAS_USERSPACE
|
2022-10-24 19:32:58 +02:00
|
|
|
select ARCH_HAS_STACK_PROTECTION
|
2020-11-05 23:30:20 +01:00
|
|
|
select MPU
|
|
|
|
|
select SRAM_REGION_PERMISSIONS
|
2020-07-21 15:59:23 +02:00
|
|
|
select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
|
2022-04-07 04:03:54 +02:00
|
|
|
select ARCH_MEM_DOMAIN_DATA if USERSPACE
|
2022-06-07 15:37:59 +02:00
|
|
|
select THREAD_LOCAL_STORAGE if USERSPACE
|
2024-04-25 21:10:03 +02:00
|
|
|
select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS
|
|
|
|
|
select MEM_DOMAIN_ISOLATED_STACKS
|
2020-07-21 15:59:23 +02:00
|
|
|
help
|
|
|
|
|
MCU implements Physical Memory Protection.
|
|
|
|
|
|
|
|
|
|
if RISCV_PMP
|
2022-04-07 04:03:54 +02:00
|
|
|
|
2022-04-07 21:44:42 +02:00
|
|
|
config PMP_SLOTS
|
2022-04-07 04:03:54 +02:00
|
|
|
int "Number of PMP slots"
|
|
|
|
|
default 8
|
|
|
|
|
help
|
|
|
|
|
This is the number of PMP entries implemented by the hardware.
|
|
|
|
|
Typical values are 8 or 16.
|
|
|
|
|
|
2023-02-09 19:15:45 +01:00
|
|
|
config PMP_NO_TOR
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Set this if TOR (Top Of Range) mode is not supported.
|
|
|
|
|
|
|
|
|
|
config PMP_NO_NA4
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Set this if NA4 (Naturally Aligned 4-byte) mode is not supported.
|
|
|
|
|
|
|
|
|
|
config PMP_NO_NAPOT
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Set this if NAPOT (Naturally Aligned Power Of Two) is not supported.
|
|
|
|
|
|
2022-04-07 04:03:54 +02:00
|
|
|
config PMP_POWER_OF_TWO_ALIGNMENT
|
2023-02-09 19:15:45 +01:00
|
|
|
bool "Enforce power-of-two alignment on PMP memory areas" if !PMP_NO_TOR
|
2022-04-07 04:03:54 +02:00
|
|
|
default y if TEST_USERSPACE
|
2022-04-07 21:44:42 +02:00
|
|
|
default y if (PMP_SLOTS = 8)
|
2023-02-09 19:15:45 +01:00
|
|
|
default y if PMP_NO_TOR
|
2022-04-07 04:03:54 +02:00
|
|
|
select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
|
|
|
|
|
select GEN_PRIV_STACKS
|
|
|
|
|
help
|
|
|
|
|
This option reduces the PMP slot usage but increases
|
2022-05-13 06:00:19 +02:00
|
|
|
memory consumption. Useful when enabling userspace mode with
|
|
|
|
|
many memory domains and/or few PMP slots available.
|
2022-04-07 04:03:54 +02:00
|
|
|
|
2023-03-28 04:46:14 +02:00
|
|
|
config PMP_GRANULARITY
|
|
|
|
|
int "The granularity of PMP address matching"
|
|
|
|
|
default 8 if (PMP_NO_TOR && PMP_NO_NA4)
|
|
|
|
|
default 4
|
|
|
|
|
help
|
|
|
|
|
The granularity must be a power of 2 greater than or equal to 4
|
|
|
|
|
(ie 4, 8, 16, ...), but if neither TOR mode nor NA4 mode is
|
|
|
|
|
supported, the minimum granularity is 8.
|
|
|
|
|
|
2020-07-21 15:59:23 +02:00
|
|
|
endif #RISCV_PMP
|
|
|
|
|
|
2022-05-13 06:00:19 +02:00
|
|
|
config PMP_STACK_GUARD
|
|
|
|
|
def_bool y
|
2022-07-30 03:26:45 +02:00
|
|
|
depends on MULTITHREADING
|
2022-05-13 06:00:19 +02:00
|
|
|
depends on HW_STACK_PROTECTION
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config PMP_STACK_GUARD_MIN_SIZE
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int "Stack Guard area size"
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depends on PMP_STACK_GUARD
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default 1024 if 64BIT
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default 512
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help
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The Hardware Stack Protection implements a guard area at the bottom
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of the stack using the PMP to catch stack overflows by marking that
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guard area not accessible.
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This is the size of the guard area. This should be large enough to
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catch any sudden jump in stack pointer decrement, plus some
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wiggle room to accommodate the eventual overflow exception
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stack usage.
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2023-05-23 05:55:43 +02:00
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# Implement the null pointer detection using the Physical Memory Protection
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# (PMP) Unit.
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config NULL_POINTER_EXCEPTION_DETECTION_PMP
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bool "Use PMP for null pointer exception detection"
|
|
|
|
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depends on RISCV_PMP
|
|
|
|
|
help
|
|
|
|
|
Null pointer dereference detection implemented
|
|
|
|
|
using PMP functionality.
|
|
|
|
|
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|
|
|
|
if NULL_POINTER_EXCEPTION_DETECTION_PMP
|
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|
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config NULL_POINTER_EXCEPTION_REGION_SIZE
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|
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hex "Inaccessible region to implement null pointer detection"
|
|
|
|
|
default 0x10
|
|
|
|
|
help
|
|
|
|
|
Use a PMP slot to make region (starting at address 0x0) inaccessible for
|
|
|
|
|
detecting null pointer dereferencing (raising a CPU access fault).
|
|
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|
|
Minimum is 4 bytes.
|
|
|
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|
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endif # NULL_POINTER_EXCEPTION_DETECTION_PMP
|
|
|
|
|
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
endmenu
|
|
|
|
|
|
2021-01-07 21:16:10 +01:00
|
|
|
config MAIN_STACK_SIZE
|
|
|
|
|
default 4096 if 64BIT
|
2022-04-30 21:12:31 +02:00
|
|
|
default 2048 if PMP_STACK_GUARD
|
2021-01-07 21:16:10 +01:00
|
|
|
|
2022-02-17 17:09:09 +01:00
|
|
|
config TEST_EXTRA_STACK_SIZE
|
2023-02-01 03:08:13 +01:00
|
|
|
default 1536
|
2021-01-07 21:16:10 +01:00
|
|
|
|
|
|
|
|
config CMSIS_THREAD_MAX_STACK_SIZE
|
|
|
|
|
default 1024 if 64BIT
|
|
|
|
|
|
|
|
|
|
config CMSIS_V2_THREAD_MAX_STACK_SIZE
|
|
|
|
|
default 1024 if 64BIT
|
|
|
|
|
|
2022-06-27 10:51:28 +02:00
|
|
|
config ARCH_IRQ_VECTOR_TABLE_ALIGN
|
|
|
|
|
default 256
|
|
|
|
|
|
2023-09-01 12:55:07 +02:00
|
|
|
config RISCV_TRAP_HANDLER_ALIGNMENT
|
|
|
|
|
int "Alignment of RISC-V trap handler in bytes"
|
|
|
|
|
default 4
|
|
|
|
|
help
|
|
|
|
|
This value configures the alignment of RISC-V trap handling
|
|
|
|
|
code. The requirement for a particular alignment arises from
|
|
|
|
|
the format of MTVEC register which is RISC-V platform-specific.
|
|
|
|
|
The minimum alignment is 4 bytes according to the Spec.
|
|
|
|
|
|
2022-06-27 10:51:28 +02:00
|
|
|
config GEN_IRQ_VECTOR_TABLE
|
2024-01-03 12:39:36 +01:00
|
|
|
select RISCV_VECTORED_MODE if RISCV_PRIVILEGED
|
2022-06-27 10:51:28 +02:00
|
|
|
|
2022-07-30 03:26:45 +02:00
|
|
|
config ARCH_HAS_SINGLE_THREAD_SUPPORT
|
|
|
|
|
default y if !SMP
|
|
|
|
|
|
2022-05-12 12:03:47 +02:00
|
|
|
rsource "Kconfig.isa"
|
|
|
|
|
|
arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 00:24:30 +01:00
|
|
|
endmenu
|
