arch: riscv: optionally stores a pointer to csf in struct arch_esf
The callee-saved-registers can be helpful to debug the state of a core upon an exception, however, currently there's no way to access that information in user-implemented `k_sys_fatal_error_handler()`, even though the csf is already stored in the stack. This patch conditionally add a `csf` member in the `arch_esf` when `CONFIG_EXTRA_EXCEPTION_INFO=y`*, which the `_isr_wrapper` would update when a fatal error occurs before invoking `z_riscv_fatal_error_csf()`. Functions such as `k_sys_fatal_error_handler()` would then be able to access the callee-saved-registers at the time of exception via `esf->csf`. * For SoCs that select `RISCV_SOC_HAS_ISR_STACKING`, the `SOC_ISR_STACKING_ESF_DECLARE` has to include the `csf` member, otherwise the build would fail. Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
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5 changed files with 35 additions and 1 deletions
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@ -238,6 +238,14 @@ config RISCV_HART_MASK
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i.e. 128, 129, ..(0x80, 8x81, ..), this can be configured to 63 (0x7f)
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such that we can extract the bits that start from 0.
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config EXTRA_EXCEPTION_INFO
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bool "Collect extra exception info"
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depends on EXCEPTION_DEBUG
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help
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This option enables the collection of extra information, such as
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register state, when a fault occurs. This information can be useful
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to collect for post-mortem analysis and debug of issues.
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config RISCV_PMP
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bool "RISC-V PMP Support"
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select THREAD_STACK_INFO
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@ -450,10 +450,15 @@ do_fault:
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STORE_CALLEE_SAVED() ;
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mv a2, sp
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#ifdef CONFIG_EXTRA_EXCEPTION_INFO
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/* Store csf's addr into esf (a1 still holds the pointer to the esf at this point) */
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sr a2 __struct_arch_esf_csf_OFFSET(a1)
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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tail z_riscv_fatal_error_csf
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#else
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tail z_riscv_fatal_error
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#endif
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#endif /* CONFIG_EXCEPTION_DEBUG */
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#if defined(CONFIG_IRQ_OFFLOAD)
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do_irq_offload:
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@ -118,6 +118,10 @@ GEN_OFFSET_STRUCT(arch_esf, s0);
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GEN_OFFSET_STRUCT(arch_esf, sp);
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#endif
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#ifdef CONFIG_EXTRA_EXCEPTION_INFO
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GEN_OFFSET_STRUCT(arch_esf, csf);
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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#if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE)
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GEN_OFFSET_STRUCT(arch_esf, soc_context);
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#endif
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@ -64,6 +64,13 @@ Architectures
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* The stack traces upon fatal exception now prints the address of stack pointer (sp) or frame
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pointer (fp) depending on the build configuration.
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* When :kconfig:option:`CONFIG_EXTRA_EXCEPTION_INFO` is enabled, the exception stack frame (arch_esf)
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has an additional field ``csf`` that points to the callee-saved-registers upon an fatal error,
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which can be accessed in :c:func:`k_sys_fatal_error_handler` by ``esf->csf``.
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* For SoCs that select `RISCV_SOC_HAS_ISR_STACKING`, the `SOC_ISR_STACKING_ESF_DECLARE` has to
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include the `csf` member, otherwise the build would fail.
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* Xtensa
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* x86
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@ -45,6 +45,12 @@ struct soc_esf {
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};
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#endif
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#ifdef CONFIG_EXTRA_EXCEPTION_INFO
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/* Forward declaration */
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struct _callee_saved;
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typedef struct _callee_saved _callee_saved_t;
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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#if defined(CONFIG_RISCV_SOC_HAS_ISR_STACKING)
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SOC_ISR_STACKING_ESF_DECLARE;
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#else
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@ -81,6 +87,10 @@ struct arch_esf {
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unsigned long sp; /* preserved (user or kernel) stack pointer */
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#endif
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#ifdef CONFIG_EXTRA_EXCEPTION_INFO
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_callee_saved_t *csf; /* pointer to callee-saved-registers */
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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struct soc_esf soc_context;
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#endif
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