arch: riscv32: follow-on tweaks
A couple of follow-on patches suggested after previous RISCV32 arch changes were merged. Tweak some help in arch/riscv32/kconfig to better work with the RST docs. Take out all the CONFIG_PRINTK ifdeffery in fatal.c. The cause_str() routine should get compiled out if PRINTK=n anyway. Signed-off-by: Marti Bolivar <marti@foundries.io>
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2 changed files with 1 additions and 5 deletions
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@ -51,7 +51,7 @@ config RISCV_SOC_CONTEXT_SAVE
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See gen_offset.h for more details.
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The generic architecture IRQ wrapper will also call
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__soc_save_context and __soc_restore_context routines at
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\_\_soc_save_context and \_\_soc_restore_context routines at
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ISR entry and exit, respectively. These should typically
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be implemented in assembly. If they were C functions, they
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would have these signatures:
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@ -166,7 +166,6 @@ hang_system:
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}
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#ifdef CONFIG_PRINTK
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static char *cause_str(u32_t cause)
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{
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switch (cause) {
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@ -186,7 +185,6 @@ static char *cause_str(u32_t cause)
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return "unknown";
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}
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}
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#endif
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FUNC_NORETURN void _Fault(const NANO_ESF *esf)
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@ -196,9 +194,7 @@ FUNC_NORETURN void _Fault(const NANO_ESF *esf)
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__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
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mcause &= SOC_MCAUSE_EXP_MASK;
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#ifdef CONFIG_PRINTK
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printk("Exception cause %s (%d)\n", cause_str(mcause), (int)mcause);
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#endif
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_NanoFatalErrorHandler(_NANO_ERR_CPU_EXCEPTION, esf);
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}
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