arch: riscv: add pmp support
- Set some helper function to write/clear/print PMP config registers. - Add support for different PMP slot size function to core/board. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
This commit is contained in:
Alexandre Mergnat
Anas Nashif
parent
6340dd7a59
commit
18962e4ab8
7 changed files with 553 additions and 0 deletions
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@ -25,6 +25,7 @@ menu "RISCV Processor Options"
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config CORE_E31
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bool "Use E31 core"
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select RISCV_PMP
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select ARCH_HAS_USERSPACE
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select ARCH_HAS_STACK_PROTECTION if PMP_STACK_GUARD
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default n
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@ -112,6 +113,19 @@ config GEN_IRQ_VECTOR_TABLE
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config NUM_IRQS
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int
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menuconfig RISCV_PMP
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bool "RISC-V PMP Support"
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default n
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select THREAD_STACK_INFO
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select MEMORY_PROTECTION
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select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
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help
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MCU implements Physical Memory Protection.
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if RISCV_PMP
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source "arch/riscv/core/pmp/Kconfig"
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endif #RISCV_PMP
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endmenu
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endmenu
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@ -1,5 +1,7 @@
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory_ifdef(CONFIG_RISCV_PMP pmp)
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zephyr_library()
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zephyr_library_sources(
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14
arch/riscv/core/pmp/CMakeLists.txt
Normal file
14
arch/riscv/core/pmp/CMakeLists.txt
Normal file
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@ -0,0 +1,14 @@
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#
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# Copyright (c) 2020 BayLibre, SAS
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_RISCV_PMP core_pmp.c)
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zephyr_library_include_directories(
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.
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../../include
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)
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11
arch/riscv/core/pmp/Kconfig
Normal file
11
arch/riscv/core/pmp/Kconfig
Normal file
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@ -0,0 +1,11 @@
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# Physical Memory Protection (PMP) configuration options
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# Copyright (c) 2020 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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config PMP_SLOT
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int "Number of PMP slot"
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default 8
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help
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Depend of the arch/board. Take care to don't put value higher
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than the Hardware allow you.
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221
arch/riscv/core/pmp/core_pmp.c
Normal file
221
arch/riscv/core/pmp/core_pmp.c
Normal file
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@ -0,0 +1,221 @@
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/*
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* Copyright (c) 2020 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <kernel_internal.h>
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#include "core_pmp.h"
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#include <arch/riscv/csr.h>
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#include <stdio.h>
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#define PMP_SLOT_NUMBER CONFIG_PMP_SLOT
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#ifdef CONFIG_USERSPACE
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extern ulong_t is_user_mode;
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#endif
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enum {
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CSR_PMPCFG0,
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CSR_PMPCFG1,
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CSR_PMPCFG2,
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CSR_PMPCFG3,
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CSR_PMPADDR0,
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CSR_PMPADDR1,
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CSR_PMPADDR2,
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CSR_PMPADDR3,
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CSR_PMPADDR4,
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CSR_PMPADDR5,
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CSR_PMPADDR6,
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CSR_PMPADDR7,
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CSR_PMPADDR8,
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CSR_PMPADDR9,
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CSR_PMPADDR10,
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CSR_PMPADDR11,
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CSR_PMPADDR12,
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CSR_PMPADDR13,
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CSR_PMPADDR14,
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CSR_PMPADDR15
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};
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ulong_t csr_read_enum(int pmp_csr_enum)
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{
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ulong_t res = -1;
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switch (pmp_csr_enum) {
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case CSR_PMPCFG0:
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res = csr_read(0x3A0); break;
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case CSR_PMPCFG1:
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res = csr_read(0x3A1); break;
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case CSR_PMPCFG2:
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res = csr_read(0x3A2); break;
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case CSR_PMPCFG3:
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res = csr_read(0x3A3); break;
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case CSR_PMPADDR0:
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res = csr_read(0x3B0); break;
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case CSR_PMPADDR1:
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res = csr_read(0x3B1); break;
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case CSR_PMPADDR2:
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res = csr_read(0x3B2); break;
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case CSR_PMPADDR3:
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res = csr_read(0x3B3); break;
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case CSR_PMPADDR4:
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res = csr_read(0x3B4); break;
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case CSR_PMPADDR5:
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res = csr_read(0x3B5); break;
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case CSR_PMPADDR6:
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res = csr_read(0x3B6); break;
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case CSR_PMPADDR7:
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res = csr_read(0x3B7); break;
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case CSR_PMPADDR8:
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res = csr_read(0x3B8); break;
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case CSR_PMPADDR9:
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res = csr_read(0x3B9); break;
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case CSR_PMPADDR10:
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res = csr_read(0x3BA); break;
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case CSR_PMPADDR11:
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res = csr_read(0x3BB); break;
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case CSR_PMPADDR12:
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res = csr_read(0x3BC); break;
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case CSR_PMPADDR13:
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res = csr_read(0x3BD); break;
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case CSR_PMPADDR14:
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res = csr_read(0x3BE); break;
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case CSR_PMPADDR15:
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res = csr_read(0x3BF); break;
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default:
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break;
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}
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return res;
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}
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void csr_write_enum(int pmp_csr_enum, ulong_t value)
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{
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switch (pmp_csr_enum) {
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case CSR_PMPCFG0:
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csr_write(0x3A0, value); break;
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case CSR_PMPCFG1:
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csr_write(0x3A1, value); break;
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case CSR_PMPCFG2:
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csr_write(0x3A2, value); break;
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case CSR_PMPCFG3:
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csr_write(0x3A3, value); break;
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case CSR_PMPADDR0:
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csr_write(0x3B0, value); break;
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case CSR_PMPADDR1:
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csr_write(0x3B1, value); break;
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case CSR_PMPADDR2:
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csr_write(0x3B2, value); break;
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case CSR_PMPADDR3:
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csr_write(0x3B3, value); break;
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case CSR_PMPADDR4:
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csr_write(0x3B4, value); break;
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case CSR_PMPADDR5:
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csr_write(0x3B5, value); break;
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case CSR_PMPADDR6:
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csr_write(0x3B6, value); break;
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case CSR_PMPADDR7:
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csr_write(0x3B7, value); break;
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case CSR_PMPADDR8:
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csr_write(0x3B8, value); break;
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case CSR_PMPADDR9:
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csr_write(0x3B9, value); break;
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case CSR_PMPADDR10:
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csr_write(0x3BA, value); break;
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case CSR_PMPADDR11:
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csr_write(0x3BB, value); break;
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case CSR_PMPADDR12:
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csr_write(0x3BC, value); break;
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case CSR_PMPADDR13:
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csr_write(0x3BD, value); break;
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case CSR_PMPADDR14:
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csr_write(0x3BE, value); break;
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case CSR_PMPADDR15:
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csr_write(0x3BF, value); break;
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default:
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break;
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}
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}
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int z_riscv_pmp_set(unsigned int index, ulong_t cfg_val, ulong_t addr_val)
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{
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ulong_t reg_val;
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ulong_t shift, mask;
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int pmpcfg_csr;
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int pmpaddr_csr;
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if ((index >= PMP_SLOT_NUMBER) | (index < 0))
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return -1;
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/* Calculate PMP config/addr register, shift and mask */
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#ifdef CONFIG_64BIT
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pmpcfg_csr = CSR_PMPCFG0 + ((index >> 3) << 1);
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shift = (index & 0x7) << 3;
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#else
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pmpcfg_csr = CSR_PMPCFG0 + (index >> 2);
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shift = (index & 0x3) << 3;
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#endif /* CONFIG_64BIT */
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pmpaddr_csr = CSR_PMPADDR0 + index;
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/* Mask = 0x000000FF<<((index%4)*8) */
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mask = 0x000000FF << shift;
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cfg_val = cfg_val << shift;
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addr_val = TO_PMP_ADDR(addr_val);
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reg_val = csr_read_enum(pmpcfg_csr);
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reg_val = reg_val & ~mask;
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reg_val = reg_val | cfg_val;
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csr_write_enum(pmpaddr_csr, addr_val);
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csr_write_enum(pmpcfg_csr, reg_val);
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return 0;
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}
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int pmp_get(unsigned int index, ulong_t *cfg_val, ulong_t *addr_val)
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{
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ulong_t shift;
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int pmpcfg_csr;
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int pmpaddr_csr;
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if ((index >= PMP_SLOT_NUMBER) | (index < 0))
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return -1;
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/* Calculate PMP config/addr register and shift */
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#ifdef CONFIG_64BIT
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pmpcfg_csr = CSR_PMPCFG0 + (index >> 4);
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shift = (index & 0x0007) << 3;
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#else
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pmpcfg_csr = CSR_PMPCFG0 + (index >> 2);
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shift = (index & 0x0003) << 3;
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#endif /* CONFIG_64BIT */
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pmpaddr_csr = CSR_PMPADDR0 + index;
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*cfg_val = (csr_read_enum(pmpcfg_csr) >> shift) & 0xFF;
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*addr_val = FROM_PMP_ADDR(csr_read_enum(pmpaddr_csr));
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return 0;
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}
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void z_riscv_pmp_clear_config(void)
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{
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for (unsigned int i = 0; i < RISCV_PMP_CFG_NUM; i++)
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csr_write_enum(CSR_PMPCFG0 + i, 0);
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}
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/* Function to help debug */
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void z_riscv_pmp_print(unsigned int index)
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{
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ulong_t cfg_val;
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ulong_t addr_val;
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if (pmp_get(index, &cfg_val, &addr_val))
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return;
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#ifdef CONFIG_64BIT
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printf("PMP[%d] :\t%02lX %16lX\n", index, cfg_val, addr_val);
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#else
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printf("PMP[%d] :\t%02lX %08lX\n", index, cfg_val, addr_val);
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#endif /* CONFIG_64BIT */
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}
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57
arch/riscv/include/core_pmp.h
Normal file
57
arch/riscv/include/core_pmp.h
Normal file
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@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2020 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef CORE_PMP_H_
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#define CORE_PMP_H_
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/* Configuration register flags (cfg_val)*/
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#define PMP_R 0x01 /* Allow read */
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#define PMP_W 0x02 /* Allow write */
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#define PMP_X 0x04 /* Allow execute */
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#define PMP_A 0x18 /* Address-matching mode field */
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#define PMP_L 0x80 /* PMP entry is locked */
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#define PMP_OFF 0x00 /* Null region */
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#define PMP_TOR 0x08 /* Top of range */
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#define PMP_NA4 0x10 /* Naturally aligned four-byte region */
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#define PMP_NAPOT 0x18 /* Naturally aligned power-of-two region */
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#define PMP_SHIFT_ADDR 2
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#define PMP_TYPE_MASK 0x18
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#define TO_PMP_ADDR(addr) ((addr) >> PMP_SHIFT_ADDR)
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#define FROM_PMP_ADDR(addr) ((addr) << PMP_SHIFT_ADDR)
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#define TO_NAPOT_RANGE(size) (((size) - 1) >> 1)
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#define TO_PMP_NAPOT(addr, size) TO_PMP_ADDR(addr | \
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TO_NAPOT_RANGE(size))
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#ifdef CONFIG_RISCV_PMP
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/*
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* @brief Set a Physical Memory Protection slot
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*
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* Configure a memory region to be secured by one of the 16 PMP entries.
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*
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* @param index Number of the targeted PMP entrie (0 to 15 only).
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* @param cfg_val Configuration value (cf datasheet or defined flags)
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* @param addr_val Address register value
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*
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* This function shall only be called from Secure state.
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*
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* @return -1 if bad argument, 0 otherwise.
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*/
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int z_riscv_pmp_set(unsigned int index, ulong_t cfg_val, ulong_t addr_val);
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/*
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* @brief Reset to 0 all PMP setup registers
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*/
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void z_riscv_pmp_clear_config(void);
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/*
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* @brief Print PMP setup register for info/debug
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*/
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void z_riscv_pmp_print(unsigned int index);
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#endif /* CONFIG_RISCV_PMP */
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#endif /* CORE_PMP_H_ */
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234
include/arch/riscv/csr.h
Normal file
234
include/arch/riscv/csr.h
Normal file
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@ -0,0 +1,234 @@
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/*
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* Copyright (c) 2020 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef CSR_H_
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#define CSR_H_
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#define MSTATUS_UIE 0x00000001
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#define MSTATUS_SIE 0x00000002
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#define MSTATUS_HIE 0x00000004
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#define MSTATUS_MIE 0x00000008
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#define MSTATUS_UPIE 0x00000010
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#define MSTATUS_SPIE 0x00000020
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#define MSTATUS_HPIE 0x00000040
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#define MSTATUS_MPIE 0x00000080
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#define MSTATUS_SPP 0x00000100
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#define MSTATUS_HPP 0x00000600
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#define MSTATUS_MPP 0x00001800
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_SUM 0x00040000
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#define MSTATUS_MXR 0x00080000
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#define MSTATUS_TVM 0x00100000
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#define MSTATUS_TW 0x00200000
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#define MSTATUS_TSR 0x00400000
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS_UXL 0x0000000300000000
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#define MSTATUS_SXL 0x0000000C00000000
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#define MSTATUS64_SD 0x8000000000000000
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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#define SSTATUS_SPIE 0x00000020
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_SUM 0x00040000
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#define SSTATUS_MXR 0x00080000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS_UXL 0x0000000300000000
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#define SSTATUS64_SD 0x8000000000000000
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#define DCSR_XDEBUGVER (3U<<30)
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#define DCSR_NDRESET (1<<29)
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#define DCSR_FULLRESET (1<<28)
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#define DCSR_EBREAKM (1<<15)
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#define DCSR_EBREAKH (1<<14)
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#define DCSR_EBREAKS (1<<13)
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#define DCSR_EBREAKU (1<<12)
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#define DCSR_STOPCYCLE (1<<10)
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#define DCSR_STOPTIME (1<<9)
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#define DCSR_CAUSE (7<<6)
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#define DCSR_DEBUGINT (1<<5)
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#define DCSR_HALT (1<<3)
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#define DCSR_STEP (1<<2)
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#define DCSR_PRV (3<<0)
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#define DCSR_CAUSE_NONE 0
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#define DCSR_CAUSE_SWBP 1
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#define DCSR_CAUSE_HWBP 2
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#define DCSR_CAUSE_DEBUGINT 3
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#define DCSR_CAUSE_STEP 4
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#define DCSR_CAUSE_HALT 5
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#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
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#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
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#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
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#define MCONTROL_SELECT (1<<19)
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#define MCONTROL_TIMING (1<<18)
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#define MCONTROL_ACTION (0x3f<<12)
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#define MCONTROL_CHAIN (1<<11)
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#define MCONTROL_MATCH (0xf<<7)
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#define MCONTROL_M (1<<6)
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#define MCONTROL_H (1<<5)
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#define MCONTROL_S (1<<4)
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#define MCONTROL_U (1<<3)
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#define MCONTROL_EXECUTE (1<<2)
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#define MCONTROL_STORE (1<<1)
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#define MCONTROL_LOAD (1<<0)
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#define MCONTROL_TYPE_NONE 0
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#define MCONTROL_TYPE_MATCH 2
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|
||||
#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
|
||||
#define MCONTROL_ACTION_DEBUG_MODE 1
|
||||
#define MCONTROL_ACTION_TRACE_START 2
|
||||
#define MCONTROL_ACTION_TRACE_STOP 3
|
||||
#define MCONTROL_ACTION_TRACE_EMIT 4
|
||||
|
||||
#define MCONTROL_MATCH_EQUAL 0
|
||||
#define MCONTROL_MATCH_NAPOT 1
|
||||
#define MCONTROL_MATCH_GE 2
|
||||
#define MCONTROL_MATCH_LT 3
|
||||
#define MCONTROL_MATCH_MASK_LOW 4
|
||||
#define MCONTROL_MATCH_MASK_HIGH 5
|
||||
|
||||
#define MIP_SSIP (1 << IRQ_S_SOFT)
|
||||
#define MIP_HSIP (1 << IRQ_H_SOFT)
|
||||
#define MIP_MSIP (1 << IRQ_M_SOFT)
|
||||
#define MIP_STIP (1 << IRQ_S_TIMER)
|
||||
#define MIP_HTIP (1 << IRQ_H_TIMER)
|
||||
#define MIP_MTIP (1 << IRQ_M_TIMER)
|
||||
#define MIP_SEIP (1 << IRQ_S_EXT)
|
||||
#define MIP_HEIP (1 << IRQ_H_EXT)
|
||||
#define MIP_MEIP (1 << IRQ_M_EXT)
|
||||
|
||||
#define SIP_SSIP MIP_SSIP
|
||||
#define SIP_STIP MIP_STIP
|
||||
|
||||
#define PRV_U 0
|
||||
#define PRV_S 1
|
||||
#define PRV_H 2
|
||||
#define PRV_M 3
|
||||
|
||||
#define SATP32_MODE 0x80000000
|
||||
#define SATP32_ASID 0x7FC00000
|
||||
#define SATP32_PPN 0x003FFFFF
|
||||
#define SATP64_MODE 0xF000000000000000
|
||||
#define SATP64_ASID 0x0FFFF00000000000
|
||||
#define SATP64_PPN 0x00000FFFFFFFFFFF
|
||||
|
||||
#define SATP_MODE_OFF 0
|
||||
#define SATP_MODE_SV32 1
|
||||
#define SATP_MODE_SV39 8
|
||||
#define SATP_MODE_SV48 9
|
||||
#define SATP_MODE_SV57 10
|
||||
#define SATP_MODE_SV64 11
|
||||
|
||||
#define PMP_R 0x01
|
||||
#define PMP_W 0x02
|
||||
#define PMP_X 0x04
|
||||
#define PMP_A 0x18
|
||||
#define PMP_L 0x80
|
||||
#define PMP_SHIFT 2
|
||||
|
||||
#define PMP_TOR 0x08
|
||||
#define PMP_NA4 0x10
|
||||
#define PMP_NAPOT 0x18
|
||||
|
||||
#define IRQ_S_SOFT 1
|
||||
#define IRQ_H_SOFT 2
|
||||
#define IRQ_M_SOFT 3
|
||||
#define IRQ_S_TIMER 5
|
||||
#define IRQ_H_TIMER 6
|
||||
#define IRQ_M_TIMER 7
|
||||
#define IRQ_S_EXT 9
|
||||
#define IRQ_H_EXT 10
|
||||
#define IRQ_M_EXT 11
|
||||
#define IRQ_COP 12
|
||||
#define IRQ_HOST 13
|
||||
|
||||
#define DEFAULT_RSTVEC 0x00001000
|
||||
#define CLINT_BASE 0x02000000
|
||||
#define CLINT_SIZE 0x000c0000
|
||||
#define EXT_IO_BASE 0x40000000
|
||||
#define DRAM_BASE 0x80000000
|
||||
|
||||
/* page table entry (PTE) fields */
|
||||
#define PTE_V 0x001 /* Valid */
|
||||
#define PTE_R 0x002 /* Read */
|
||||
#define PTE_W 0x004 /* Write */
|
||||
#define PTE_X 0x008 /* Execute */
|
||||
#define PTE_U 0x010 /* User */
|
||||
#define PTE_G 0x020 /* Global */
|
||||
#define PTE_A 0x040 /* Accessed */
|
||||
#define PTE_D 0x080 /* Dirty */
|
||||
#define PTE_SOFT 0x300 /* Reserved for Software */
|
||||
|
||||
#define PTE_PPN_SHIFT 10
|
||||
|
||||
#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
|
||||
|
||||
#define INSERT_FIELD(val, which, fieldval) \
|
||||
( \
|
||||
((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))) \
|
||||
) \
|
||||
|
||||
#define csr_read(csr) \
|
||||
({ \
|
||||
register unsigned long __v; \
|
||||
__asm__ volatile ("csrr %0, " #csr \
|
||||
: "=r" (__v)); \
|
||||
__v; \
|
||||
})
|
||||
|
||||
#define csr_write(csr, val) \
|
||||
({ \
|
||||
unsigned long __v = (unsigned long)(val); \
|
||||
__asm__ volatile ("csrw " #csr ", %0" \
|
||||
: : "rK" (__v) \
|
||||
: "memory"); \
|
||||
})
|
||||
|
||||
|
||||
#define csr_read_set(csr, val) \
|
||||
({ \
|
||||
unsigned long __v = (unsigned long)(val); \
|
||||
__asm__ volatile ("csrrs %0, " #csr ", %1" \
|
||||
: "=r" (__v) : "rK" (__v) \
|
||||
: "memory"); \
|
||||
__v; \
|
||||
})
|
||||
|
||||
#define csr_set(csr, val) \
|
||||
({ \
|
||||
unsigned long __v = (unsigned long)(val); \
|
||||
__asm__ volatile ("csrs " #csr ", %0" \
|
||||
: : "rK" (__v) \
|
||||
: "memory"); \
|
||||
})
|
||||
|
||||
#define csr_read_clear(csr, val) \
|
||||
({ \
|
||||
unsigned long __v = (unsigned long)(val); \
|
||||
__asm__ volatile ("csrrc %0, " #csr ", %1" \
|
||||
: "=r" (__v) : "rK" (__v) \
|
||||
: "memory"); \
|
||||
__v; \
|
||||
})
|
||||
|
||||
#define csr_clear(csr, val) \
|
||||
({ \
|
||||
unsigned long __v = (unsigned long)(val); \
|
||||
__asm__ volatile ("csrc " #csr ", %0" \
|
||||
: : "rK" (__v) \
|
||||
: "memory"); \
|
||||
})
|
||||
|
||||
#endif /* CSR_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue