arch: soc: riscv32: Separate soc offsets from soc context save
The zero-riscy core on the rv32m1 soc does not implement hardware loop extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes from GEN_SOC_OFFSET_SYMS(). Split out the soc offset symbols into a separate config so we can enable them without enabling soc context saving. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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6 changed files with 65 additions and 23 deletions
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@ -21,6 +21,7 @@ config INCLUDE_RESET_VECTOR
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config RISCV_SOC_CONTEXT_SAVE
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bool "Enable SOC-based context saving in IRQ handlers"
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select RISCV_SOC_OFFSETS
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help
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Enable low-level SOC-specific context management, for SOCs
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with extra state that must be saved when entering an
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@ -40,12 +41,6 @@ config RISCV_SOC_CONTEXT_SAVE
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- SOC_ESF_INIT: structure contents initializer for struct soc_esf
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state. The last initialized member should not end in a comma.
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- GEN_SOC_OFFSET_SYMS(): a macro which expands to
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GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
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to ensure offset macros for SOC_ESF_MEMBERS are defined
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in offsets.h. The last one should not end in a semicolon.
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See gen_offset.h for more details.
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The generic architecture IRQ wrapper will also call
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\_\_soc_save_context and \_\_soc_restore_context routines at
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ISR entry and exit, respectively. These should typically
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@ -59,6 +54,18 @@ config RISCV_SOC_CONTEXT_SAVE
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The calls obey standard calling conventions; i.e., the state
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pointer address is in a0, and ra contains the return address.
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config RISCV_SOC_OFFSETS
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bool "Enable SOC-based offsets"
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help
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Enabling this option requires that the SoC provide a soc_offsets.h
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header which defines the following macros:
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- GEN_SOC_OFFSET_SYMS(): a macro which expands to
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GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
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to ensure offset macros for SOC_ESF_MEMBERS are defined
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in offsets.h. The last one should not end in a semicolon.
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See gen_offset.h for more details.
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config RISCV_SOC_INTERRUPT_INIT
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bool "Enable SOC-based interrupt initialization"
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help
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@ -20,6 +20,9 @@
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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#include <soc_context.h>
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#endif
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#ifdef CONFIG_RISCV_SOC_OFFSETS
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#include <soc_offsets.h>
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#endif
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/* thread_arch_t member offsets */
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GEN_OFFSET_SYM(_thread_arch_t, swap_return_value);
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@ -64,6 +67,8 @@ GEN_OFFSET_SYM(NANO_ESF, mstatus);
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#if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE)
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GEN_OFFSET_SYM(NANO_ESF, soc_context);
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#endif
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#if defined(CONFIG_RISCV_SOC_OFFSETS)
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GEN_SOC_OFFSET_SYMS();
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#endif
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@ -36,6 +36,10 @@ config RISCV_SOC_CONTEXT_SAVE
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bool
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default y if SOC_OPENISA_RV32M1_RI5CY
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config RISCV_SOC_OFFSETS
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bool
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default y
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config RISCV_SOC_INTERRUPT_INIT
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bool
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default y
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@ -31,22 +31,6 @@
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0xdeadbaad, \
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0xdeadbaad
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/*
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* Ensure offset macros are available in <offsets.h> for the above.
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*
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* Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR,
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* for use in assembly.
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*/
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
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GEN_OFFSET_SYM(soc_esf_t, lpend0); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
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GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
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GEN_OFFSET_SYM(soc_esf_t, lpend1); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount1); \
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GEN_ABSOLUTE_SYM(__EVENT0_INTPTPENDCLEAR, \
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(uint32_t)&EVENT0->INTPTPENDCLEAR)
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
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#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_ */
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@ -40,7 +40,7 @@ SECTION_FUNC(exception.other, __soc_is_irq)
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* INTPTPENDCLEAR.
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*/
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SECTION_FUNC(exception.other, __soc_handle_irq)
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la t0, __EVENT0_INTPTPENDCLEAR
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la t0, __EVENT_INTPTPENDCLEAR
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li t1, 1
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sll t1, t1, a0
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sw t1, 0x00(t0)
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42
soc/riscv32/openisa_rv32m1/soc_offsets.h
Normal file
42
soc/riscv32/openisa_rv32m1/soc_offsets.h
Normal file
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
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*/
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#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
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#define SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
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#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
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/*
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* Ensure offset macros are available in <offsets.h>.
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*
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* Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR,
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* for use in assembly.
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*/
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
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GEN_OFFSET_SYM(soc_esf_t, lpend0); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
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GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
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GEN_OFFSET_SYM(soc_esf_t, lpend1); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount1); \
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GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
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(uint32_t)&EVENT0->INTPTPENDCLEAR)
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
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#ifdef CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
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(uint32_t)&EVENT1->INTPTPENDCLEAR)
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#endif /* CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY */
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#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_ */
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