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arch: soc: riscv32: Separate soc offsets from soc context save

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The zero-riscy core on the rv32m1 soc does not implement hardware loop
extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it
does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes
from GEN_SOC_OFFSET_SYMS().

Split out the soc offset symbols into a separate config so we can enable
them without enabling soc context saving.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2018-12-02 18:46:26 -06:00 • committed by Kumar Gala
commit bc9f67f97f
6 changed files with 65 additions and 23 deletions
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19
arch/riscv32/Kconfig
View file

@ -21,6 +21,7 @@ config INCLUDE_RESET_VECTOR
config RISCV_SOC_CONTEXT_SAVE
bool "Enable SOC-based context saving in IRQ handlers"
select RISCV_SOC_OFFSETS
help
Enable low-level SOC-specific context management, for SOCs
with extra state that must be saved when entering an
@ -40,12 +41,6 @@ config RISCV_SOC_CONTEXT_SAVE
- SOC_ESF_INIT: structure contents initializer for struct soc_esf
state. The last initialized member should not end in a comma.
- GEN_SOC_OFFSET_SYMS(): a macro which expands to
GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
to ensure offset macros for SOC_ESF_MEMBERS are defined
in offsets.h. The last one should not end in a semicolon.
See gen_offset.h for more details.
The generic architecture IRQ wrapper will also call
\_\_soc_save_context and \_\_soc_restore_context routines at
ISR entry and exit, respectively. These should typically
@ -59,6 +54,18 @@ config RISCV_SOC_CONTEXT_SAVE
The calls obey standard calling conventions; i.e., the state
pointer address is in a0, and ra contains the return address.
config RISCV_SOC_OFFSETS
bool "Enable SOC-based offsets"
help
Enabling this option requires that the SoC provide a soc_offsets.h
header which defines the following macros:
- GEN_SOC_OFFSET_SYMS(): a macro which expands to
GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
to ensure offset macros for SOC_ESF_MEMBERS are defined
in offsets.h. The last one should not end in a semicolon.
See gen_offset.h for more details.
config RISCV_SOC_INTERRUPT_INIT
bool "Enable SOC-based interrupt initialization"
help

5
arch/riscv32/core/offsets/offsets.c
View file

@ -20,6 +20,9 @@
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
#include <soc_context.h>
#endif
#ifdef CONFIG_RISCV_SOC_OFFSETS
#include <soc_offsets.h>
#endif
/* thread_arch_t member offsets */
GEN_OFFSET_SYM(_thread_arch_t, swap_return_value);
@ -64,6 +67,8 @@ GEN_OFFSET_SYM(NANO_ESF, mstatus);
#if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE)
GEN_OFFSET_SYM(NANO_ESF, soc_context);
#endif
#if defined(CONFIG_RISCV_SOC_OFFSETS)
GEN_SOC_OFFSET_SYMS();
#endif

4
soc/riscv32/openisa_rv32m1/Kconfig.defconfig
View file

@ -36,6 +36,10 @@ config RISCV_SOC_CONTEXT_SAVE
bool
default y if SOC_OPENISA_RV32M1_RI5CY
config RISCV_SOC_OFFSETS
bool
default y
config RISCV_SOC_INTERRUPT_INIT
bool
default y

16
soc/riscv32/openisa_rv32m1/soc_context.h
View file

@ -31,22 +31,6 @@
0xdeadbaad, \
0xdeadbaad
/*
* Ensure offset macros are available in <offsets.h> for the above.
*
* Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR,
* for use in assembly.
*/
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
GEN_OFFSET_SYM(soc_esf_t, lpend0); \
GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
GEN_OFFSET_SYM(soc_esf_t, lpend1); \
GEN_OFFSET_SYM(soc_esf_t, lpcount1); \
GEN_ABSOLUTE_SYM(__EVENT0_INTPTPENDCLEAR, \
(uint32_t)&EVENT0->INTPTPENDCLEAR)
#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_ */

2
soc/riscv32/openisa_rv32m1/soc_irq.S
View file

@ -40,7 +40,7 @@ SECTION_FUNC(exception.other, __soc_is_irq)
* INTPTPENDCLEAR.
*/
SECTION_FUNC(exception.other, __soc_handle_irq)
la t0, __EVENT0_INTPTPENDCLEAR
la t0, __EVENT_INTPTPENDCLEAR
li t1, 1
sll t1, t1, a0
sw t1, 0x00(t0)

42
soc/riscv32/openisa_rv32m1/soc_offsets.h Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
*/
#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
#define SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
/*
* Ensure offset macros are available in <offsets.h>.
*
* Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR,
* for use in assembly.
*/
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
GEN_OFFSET_SYM(soc_esf_t, lpend0); \
GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
GEN_OFFSET_SYM(soc_esf_t, lpend1); \
GEN_OFFSET_SYM(soc_esf_t, lpcount1); \
GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
(uint32_t)&EVENT0->INTPTPENDCLEAR)
#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
#ifdef CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY
#define GEN_SOC_OFFSET_SYMS() \
GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
(uint32_t)&EVENT1->INTPTPENDCLEAR)
#endif /* CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY */
#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_ */