zephyr/arch
Adam Szczygieł f4747547d9 arch: ISR table size optimization
Allow to use a switch-case instead of an array holding ISR entries.

When most of IRQs are not used, they share the same, default entry.
It results in most of the ISR array entries being identical duplicates.

This change allows to use dynamically generated function (after first
linker pass) that uses switch-case instead of a full array.
Default entries are handled only once, in a default section.
Used IRQs have their own case sections.
This can help reduce binary size.

Signed-off-by: Adam Szczygieł <adam.szczygiel@nordicsemi.no>
2026-04-17 12:35:34 +01:00
..
arc soc: arch: select SCHED_IPI_SUPPORTED if SMP 2026-04-14 22:31:16 -04:00
arm arch: ISR table size optimization 2026-04-17 12:35:34 +01:00
arm64 arm64: mm: increase MAX_XLAT_TABLES for USERSPACE && TEST 2026-04-15 17:17:55 -04:00
common arch: ISR table size optimization 2026-04-17 12:35:34 +01:00
mips llext: custom sections for heap 2026-03-16 10:07:20 -04:00
openrisc arch: openrisc: only compile irq_offload when enabled 2026-04-14 22:34:23 -04:00
posix nsi: move nsos_fcntl to more generic nsi_fcntl 2026-04-17 10:40:50 +02:00
riscv arch: riscv: Support up to 64 PMP registers 2026-04-15 05:50:45 -04:00
rx soc: Add FPU config for RXv2 and RXv3 2026-03-19 15:27:18 +09:00
sparc llext: custom sections for heap 2026-03-16 10:07:20 -04:00
x86 kernel: move smp code into smp/ 2026-04-14 22:31:16 -04:00
xtensa xtensa: ptables: fix dangling memory domains 2026-04-15 05:51:51 -04:00
archs.yml arch: drop Synopsis / Designware from ARC's full name 2026-04-14 10:37:34 -05:00
CMakeLists.txt cmake: enable -Wshadow partially for in-tree code 2023-08-22 11:39:58 +02:00
Kconfig arch: ISR table size optimization 2026-04-17 12:35:34 +01:00