Commit graph

125 commits

Author SHA1 Message Date
Daniel Leung
60db257e69 soc: intel_s1000: add dummy atexit() for Clang++
Add a dummy atexit() function when compiling C++ source files
using Clang++.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-01-07 17:09:38 +01:00
Daniel Leung
ac4ebe4ffb soc: intel_s1000: move XCC fixes into its own directory
Turns out it's going to have more fixes than just Newlib.
So put them into one directory.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-01-07 17:09:38 +01:00
Ulf Magnusson
984bfae831 global: Remove leading/trailing blank lines in files
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.

Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.

Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-11 19:17:27 +01:00
Daniel Leung
fc7916aeae soc: intel_s1000_crb: fix XCC build error with newlib
The Newlib in the XCC toolchain for intel_s1000_crb has a few
missing functions which are reentrant versions of the one
defined in lib/libc/newlib/libc-hooks.c. So make these call
the correct functions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-12-02 09:58:00 -05:00
Daniel Leung
90dc1e5d7a soc: intel_s1000_crb: fix cmake warning about HAS_*_DW
Both HAS_I2C_DW and HAS_SPI_DW are not valid unless I2C and
SPI are both selected. So make them dependent on the parent
subsystem config.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-12-02 09:58:00 -05:00
Daniel Leung
fadeb3eb47 soc: intel_s1000_crb: update LP_SRAM macros
The DT_LP_SRAM_* are aliases to DT_MIMO_SRAM_1_* which
are deprecated, so changing these to DT_INST_1_MMIO_SRAM_*.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
fc42c82cb9 soc: intel_s1000: define default MEMCTL reg value
When not using XCC, XCHAL_CACHE_MEMCTL_DEFAULT is not defined
which results in some variables not being able to be defined.
So define them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
c6f4a970f1 soc: intel_s1000: add _heap_sentry to linker script
Newlib requires a _heap_sentry so we add it to the linker script,
similar to what other xtensa linker scripts.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
28fb42643a soc: xtensa/intel_s1000_crb: fix build error on xtensa_api.h
Commit 2d7460482d missed replacing
the path to xtensa_api.h in the intel_s1000_crb soc.c file.
So update it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-07 21:34:03 -05:00
Ulf Magnusson
bd6e04411e kconfig: Clean up header comments and make them consistent
Use this short header style in all Kconfig files:

    # <description>

    # <copyright>
    # <license>

    ...

Also change all <description>s from

    # Kconfig[.extension] - Foo-related options

to just

    # Foo-related options

It's clear enough that it's about Kconfig.

The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)

    git ls-files '*Kconfig*' | \
        xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-04 17:31:27 -05:00
Kumar Gala
00c7ce7942 linker: move where we define _LINKER and _ASMLANGUAGE
Move _LINKER and _ASMLANGUAGE to target.cmake because of how we pick the
linker script that might be used.  This way regardless of how or where a
linker.ld gets included we will always set _LINKER & _ASMLANGUAGE (so
any header that needs check based on those defines they can,
specifically generated_dts_board.h)

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-11-03 12:55:16 +01:00
Ulf Magnusson
2b61031c8f kconfig: Remove symbol types from Kconfig.defconfig files
Same deal as in commit 7fdb525754 ("kconfig: Use 'default' instead of
'def_bool' in Kconfig.defconfig files"), but I hacked Kconfiglib to also
find cases where the type is given separately as e.g.

    config FOO
            int
            default 3

Motivation (from a note in
https://docs.zephyrproject.org/latest/guides/kconfig/index.html):

    For a symbol defined in multiple locations (e.g., in a
    Kconfig.defconfig file in Zephyr), it is best to only give the
    symbol type for the "base" definition of the symbol, and to use
    'default' (instead of 'def_<type>' value) for the remaining
    definitions. That way, if the base definition of the symbol is
    removed, the symbol ends up without a type, which generates a
    warning that points to the other definitions. That makes the extra
    definitions easier to discover and remove.

It's also nice if 'def_bool' and the like turn into a semi-reliable flag
that the symbol is only defined in Kconfig.defconfig files. That might
be a sign that things could be cleaned up.

Will do a separate pass later to remove some symbols only defined in
Kconfig.defconfig files.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-10-24 12:40:22 -05:00
Jan Van Winkel
70fb574a6e linker: cxx: xtensa: Added .gcc_except_table.*
Make sure that all sub-sections of .gcc_except_table are mapped in
rodata else C++ builds with exceptions enabled will generate warnings
due to orphan sections.

Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
2019-09-19 09:26:42 -05:00
Andrew Boie
6fd6b7e50a xtensa: remove legacy arch implementation
We re-wrote the xtensa arch code, but never got around
to purging the old implementation.

Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.

Fixes: #18138

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-12 01:26:34 -04:00
Kumar Gala
d6e6a2be38 irq: intel_s1000: Fixup IRQ values for multi-level IRQ handling
Remove the handcoded multi-level IRQ values in device tree.  We now are
able to generate the encoded multi-level IRQ value.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-09-10 07:34:57 -05:00
Daniel Leung
04ae38085c intel_s1000: implement z_soc_irq_is_enabled()
This provides an implemention for z_soc_irq_is_enabled()
as it is needed for multi-level interrupts.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-09-07 10:20:51 -04:00
Piotr Zięcik
4a543e138d drivers: spi_dw: Get clock frequency from DTS
The spi_dw driver used system clock frequency
as a base for SPI bus frequency calculation.
This commit corrects that by obtaining the needed value from DTS.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-07-24 15:10:02 +02:00
Piotr Zięcik
f2d84f08ff arch: xtensa: Get CPU clock frequency from DTS
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-07-24 15:10:02 +02:00
Sathish Kuttan
876deb420d soc: intel_s1000: add lpsram in linker script
Add LPSRAM definition in MEMORY
Place DMA buffer section in LPSRAM

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-06-11 16:36:30 -04:00
Sathish Kuttan
35c4f53ad1 soc: intel_s1000: define lpsram memory for linker
Add definitions in memory.h for use in linker script
- LPRAM_BASE
- LPRAM_SIZE

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-06-11 16:36:30 -04:00
Sathish Kuttan
1f99253b6c soc: intel_s1000: add dts fixup for low power sram
Add dts fixup definitions for low power sram base address and size
- DT_LP_SRAM_BASE
- DT_LP_SRAM_SIZE

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-06-11 16:36:30 -04:00
Daniel Leung
7fe29dcee9 soc: intel_s1000: change cached regions to write-through
The i2s_cavs.c driver manipulates cache lines before commencing
any DMA transfers. With write-back cache, if the DMA receive
buffer is not aligned to the cache lines, the data around
the buffer will be invalidated and may never written to memory.
Since the driver takes an external memory slab as buffer and
there is no easy way to force cache line alignment on
the application side, set the cached region to write-through
to avoid potential issue.

Fixes #13223

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-04-12 17:59:06 -04:00
Anas Nashif
3ae52624ff license: cleanup: add SPDX Apache-2.0 license identifier
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier.  Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.

By default all files without license information are under the default
license of Zephyr, which is Apache version 2.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-07 08:45:22 -04:00
Patrik Flykt
24d71431e9 all: Add 'U' suffix when using unsigned variables
Add a 'U' suffix to values when computing and comparing against
unsigned variables.

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-28 17:15:58 -05:00
Ulf Magnusson
53376394b7 kconfig: Remove blank lines at the beginning/end of files
Maybe this is some "just in case" thing that got copied around. There's
no need to have a blank line at the beginning or end of Kconfig files.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-03-13 07:29:42 -05:00
Patrik Flykt
4344e27c26 all: Update reserved function names
Update reserved function names starting with one underscore, replacing
them as follows:
   '_k_' with 'z_'
   '_K_' with 'Z_'
   '_handler_' with 'z_handl_'
   '_Cstart' with 'z_cstart'
   '_Swap' with 'z_swap'

This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.

Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.

Various generator scripts have also been updated as well as perf,
linker and usb files. These are
   drivers/serial/uart_handlers.c
   include/linker/kobject-text.ld
   kernel/include/syscall_handler.h
   scripts/gen_kobject_list.py
   scripts/gen_syscall_header.py

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2019-03-11 13:48:42 -04:00
Daniel Leung
adb9f0e02e xtensa: intel_s1000: turn on XTENSA_ASM2
Turns on XTENSA_ASM2 by default for intel_s1000.

Fixes #11034

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-28 14:53:52 -08:00
Daniel Leung
4c77c91f83 soc: intel_s1000_crb: fix GPIO IRQ in dts_fixup.h
The IRQ defined in DTS has already been shifted so there is
no need to shift again in dts_fixup.h.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-26 20:18:13 -06:00
Daniel Leung
f8cafdeb8e soc: intel_s1000: make zephyr_prebuilt.elf a lot smaller
Due to fake IDT_BASE address, zephyr_prebuilt.elf is about 1.1GB
in size due to all the empty space between end of SRAM and IDT_BASE.
So move the IDT_BASE to the empty space just after SRAM. The section
will be discarded in the final zephyr.elf so it should not be a big
issue. After this change, zephyr_prebuilt.elf is now a bit smaller
than 5MB.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-26 20:17:47 -06:00
Daniel Leung
603f068690 uart/ns16550: Use DT_ prefix for remaining device configs
Previous rename from CONFIG_* to DT_* left a few remaining
CONFIG_*. So rename them manually now.

Fix #13753

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-26 20:06:26 -06:00
Sathish Kuttan
1b064787ef soc: intel_s1000: remove wrappers for cache ops
Remove function wrappers for cache operations
Replaced by SOC level macros.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-02-20 07:33:11 -05:00
Sathish Kuttan
9ab20620d8 soc: intel_s1000: macros for data cache operations
Add SOC level macros to flush and invalidate data cache.
Individual drivers can use this macro instead of defining
their own macros.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-02-20 07:33:11 -05:00
Daniel Leung
1e7025c2e7 boards: intel_s1000_crb: fix setting cache attributes
This reverts commit c9ace83c89 which
bypasses setting cache attributes.

The previous cache attributes actually set the text/data/etc.
sections to be inaccessible. So fix it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-15 16:21:50 -05:00
Sathish Kuttan
66d0898a21 soc: intel_s1000: add audio master clock config
Added a SOC level routine to configure master clock outputs
if CONFIG_AUDIO is defined.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-02-11 21:34:08 -05:00
Kumar Gala
4c51684918 drivers: i2c: dw: Convert to new DT_<COMPAT>_<INSTANCE> defines
Convert designware i2c driver to use new defines so we can remove the
dts_fixup.h code for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-08 22:50:07 -05:00
Sathish Kuttan
04e72b7dae soc: intel_s1000: Encoded IRQ definitions for I2S
Use IRQ encoding macro to define the IRQ identifiers for I2S

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-02-04 00:52:15 -05:00
Sathish Kuttan
22c217b7ba soc: intel_s1000: Macro to encode multi-level IRQ
Add Macro to encode multi-level aggregation of interrupts
into an encoded IRQ value

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-02-04 00:52:15 -05:00
Daniel Leung
659c892b29 soc/intel_s1000: update DTS fixup due to CONFIG_SRAM_* changes
Commit ce7ed18989 moved CONFIG_SRAM_*
so dts_fixup.h needs to be updated for properly generated linker
script.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-01 19:14:29 -05:00
Kumar Gala
d3623a2fba soc: xtensa: intel_s1000: Encode IRQ in dts
Move IRQ number encoding out of dts_fixup.h and into the dtsi files.
For now just change devices on the dw_intc.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-02-01 04:09:01 -06:00
Rajavardhan Gundi
e584b05215 dts: intel_s1000: Exclude sram space dedicated for mcubootloader
The starting 192kB SRAM is reserved for the mcubootloader. Exclude
this region while building an application to be loaded by mcubootloader.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2019-01-16 21:22:56 -05:00
Rajavardhan Gundi
b5dd8ac37c Kconfig: intel_s1000: Move FIFO_DEPTH to soc Kconfig
FIFO_DEPTH should be in the SoC's Kconfig as this is a
configuration of SPI master controller in SoC.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2019-01-16 21:22:56 -05:00
Sathish Kuttan
39570b5bae soc: intel_s1000: Add SoC routine for GNA power-up
Add an SoC level routine to turn power and clock on for
Intel GNA block in Intel S1000 SoC.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-01-14 08:43:51 -05:00
Sathish Kuttan
c3da9238f1 soc: intel_s1000: add DMIC power control
Add DMIC power on to SoC init sequence

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-01-07 16:50:49 -05:00
Rajavardhan Gundi
4df8ba3fe0 linker: intel_s1000: Remove limits on code and data sections
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.

Fixes #11268.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-12-10 22:05:06 -05:00
Rajavardhan Gundi
022990f73d xtensa: Implement CONFIG_TEXT_SECTION_OFFSET
CONFIG_TEXT_SECTION_OFFSET allows the entire image to be moved
in memory to allow space for some type of header. The mcubootloader
can boot only such images which reserve some space for the header.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-12-05 15:48:49 +01:00
Patrik Flykt
8325a395ea soc: Add 'U' to unsigned variable assignments
Add 'U' to a value when assigning it to an unsigned variable.
MISRA-C rule 7.2

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-12-04 22:51:56 -05:00
Sathish Kuttan
1b656beb84 soc: intel_s1000: remove pinmux configuration
Since pinmux configuration is board dependent and is now under
boards/xtensa/intel_s1000, the configuration in soc.c is removed.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-29 14:23:24 -08:00
Sathish Kuttan
55002ad4d6 soc: intel_s1000: add I/O mux definitions
Added I/O mux selection definitions in order to use with a pinmux driver

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-29 14:23:24 -08:00
Sathish Kuttan
1b1c80256f dts: intel_s1000: add pinctrl to device tree
Add pinctrl node to Intel S1000 SoC device tree for I/O MUX selection

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-29 14:23:24 -08:00
Sathish Kuttan
23f11933b9 dts: intel_s1000: enable DTS for GPIO
Added GPIO to SoC device tree
Updated SoC DTS fixup
Removed Kconfig variables now replaced by DT

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-26 06:56:48 -08:00