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soc: intel_s1000: Macro to encode multi-level IRQ

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Add Macro to encode multi-level aggregation of interrupts
into an encoded IRQ value

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This commit is contained in:
Sathish Kuttan 2019-01-31 14:56:05 -08:00 • committed by Anas Nashif
commit 22c217b7ba
1 changed files with 11 additions and 0 deletions
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11
soc/xtensa/intel_s1000/soc.h
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@ -28,6 +28,17 @@
#define INTR_CNTL_IRQ_NUM(_irq) \
(((_irq >> INTR_CNTL_IRQ_NUM_SHIFT) & INTR_CNTL_IRQ_NUM_MASK) - 1)
/* Macro that aggregates the tri-level interrupt into an IRQ number */
#define SOC_AGGREGATE_IRQ(ictl_irq, cavs_irq, core_irq) \
(((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \
(((cavs_irq) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) | \
(((ictl_irq) & INTR_CNTL_IRQ_NUM_MASK) << INTR_CNTL_IRQ_NUM_SHIFT))
#define CAVS_L2_AGG_INT_LEVEL2 DT_CAVS_ICTL_0_IRQ
#define CAVS_L2_AGG_INT_LEVEL3 DT_CAVS_ICTL_1_IRQ
#define CAVS_L2_AGG_INT_LEVEL4 DT_CAVS_ICTL_2_IRQ
#define CAVS_L2_AGG_INT_LEVEL5 DT_CAVS_ICTL_3_IRQ
#define IOAPIC_EDGE 0
#define IOAPIC_HIGH 0