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drivers: spi_dw: Get clock frequency from DTS

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The spi_dw driver used system clock frequency
as a base for SPI bus frequency calculation.
This commit corrects that by obtaining the needed value from DTS.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit is contained in:
Piotr Zięcik 2019-04-11 14:28:52 +02:00 • committed by Carles Cufí
commit 4a543e138d
7 changed files with 19 additions and 16 deletions
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10
drivers/spi/spi_dw.c
View file

@ -252,7 +252,8 @@ static int spi_dw_configure(const struct spi_dw_config *info,
if (!spi_dw_is_slave(spi)) {
/* Baud rate and Slave select, for master only */
write_baudr(SPI_DW_CLK_DIVIDER(config->frequency), info->regs);
write_baudr(SPI_DW_CLK_DIVIDER(info->clock_frequency,
config->frequency), info->regs);
write_ser(1 << config->slave, info->regs);
}
@ -273,7 +274,8 @@ static int spi_dw_configure(const struct spi_dw_config *info,
LOG_DBG("Installed master config %p: freq %uHz (div = %u),"
" ws/dfs %u/%u, mode %u/%u/%u, slave %u",
config, config->frequency,
SPI_DW_CLK_DIVIDER(config->frequency),
SPI_DW_CLK_DIVIDER(info->clock_frequency,
config->frequency),
SPI_WORD_SIZE_GET(config->operation), spi->dfs,
(SPI_MODE_GET(config->operation) &
SPI_MODE_CPOL) ? 1 : 0,
@ -535,6 +537,7 @@ struct spi_dw_data spi_dw_data_port_0 = {
const struct spi_dw_config spi_dw_config_0 = {
.regs = DT_SPI_0_BASE_ADDRESS,
.clock_frequency = DT_SPI_0_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS),
@ -583,6 +586,7 @@ struct spi_dw_data spi_dw_data_port_1 = {
static const struct spi_dw_config spi_dw_config_1 = {
.regs = DT_SPI_1_BASE_ADDRESS,
.clock_frequency = DT_SPI_1_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_1_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS),
@ -631,6 +635,7 @@ struct spi_dw_data spi_dw_data_port_2 = {
static const struct spi_dw_config spi_dw_config_2 = {
.regs = DT_SPI_2_BASE_ADDRESS,
.clock_frequency = DT_SPI_2_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS),
@ -679,6 +684,7 @@ struct spi_dw_data spi_dw_data_port_3 = {
static const struct spi_dw_config spi_dw_config_3 = {
.regs = DT_SPI_3_BASE_ADDRESS,
.clock_frequency = DT_SPI_3_CLOCK_FREQUENCY,
#ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS),

12
drivers/spi/spi_dw.h
View file

@ -20,6 +20,7 @@ typedef void (*spi_dw_config_t)(void);
/* Private structures */
struct spi_dw_config {
u32_t regs;
u32_t clock_frequency;
#ifdef CONFIG_CLOCK_CONTROL
const char *clock_name;
void *clock_data;
@ -42,15 +43,8 @@ struct spi_dw_data {
/* Helper macros */
#ifdef DT_SPI_DW_SPI_CLOCK
#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \
((DT_SPI_DW_SPI_CLOCK / ssi_clk_hz) & 0xFFFF)
/* provision for soc.h providing a clock that is different than CPU clock */
#else
#define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \
((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / ssi_clk_hz) & 0xFFFF)
#endif
#define SPI_DW_CLK_DIVIDER(clock_freq, ssi_clk_hz) \
((clock_freq / ssi_clk_hz) & 0xFFFF)
#ifdef CONFIG_SPI_DW_ARC_AUX_REGS
#define Z_REG_READ(__sz) sys_in##__sz

2
soc/arc/quark_se_c1000_ss/dts_fixup.h
View file

@ -77,6 +77,7 @@
#define DT_ADC_0_BASE_ADDRESS DT_SNPS_DW_ADC_80015000_BASE_ADDRESS
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS
#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_80010000_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_80010000_LABEL
#define DT_SPI_0_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT
#define DT_SPI_0_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY
@ -86,6 +87,7 @@
#define DT_SPI_0_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS
#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_80010100_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_80010100_LABEL
#define DT_SPI_1_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT
#define DT_SPI_1_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY

5
soc/arc/snps_emsk/dts_fixup.h
View file

@ -69,18 +69,17 @@
*/
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS
#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_F0006000_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS
#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_F0007000_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL
#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0
#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY
#define DT_SPI_DW_IRQ_FLAGS 0
#define DT_SPI_DW_SPI_CLOCK DT_NS16550_F0009000_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */

2
soc/arc/snps_emsk/soc.h
View file

@ -82,8 +82,6 @@
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
/* SPI */
#define DT_SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
#define DT_SPI_DW_IRQ_FLAGS 0
/*

3
soc/x86/intel_quark/quark_se/dts_fixup.h
View file

@ -50,16 +50,19 @@
#define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001000_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS
#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001400_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL
#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0
#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY
#define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS
#define DT_SPI_2_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_B0001800_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL
#define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0
#define DT_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY

1
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -42,6 +42,7 @@
#define DT_DW_ICTL_IRQ_FLAGS DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS
#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_E000_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_E000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0
#define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE