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irq: intel_s1000: Fixup IRQ values for multi-level IRQ handling

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Remove the handcoded multi-level IRQ values in device tree.  We now are
able to generate the encoded multi-level IRQ value.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-08-08 15:03:45 -05:00 • committed by Kumar Gala
commit d6e6a2be38
2 changed files with 6 additions and 9 deletions
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12
dts/xtensa/intel/intel_s1000.dtsi
View file

@ -5,8 +5,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <mem.h>
#define IRQ_DW(x) ((x) << 16 | (7) << 8 | (6))
/ {
cpus {
#address-cells = <1>;
@ -92,7 +90,7 @@
reg = <0x00081800 0x400>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <7 0 0>;
interrupts = <6 0 0>;
interrupt-parent = <&cavs0>;
};
@ -101,7 +99,7 @@
reg = <0x00080c00 0x400>;
bits = <32>;
label = "GPIO";
interrupts = <IRQ_DW(4) 1 0>;
interrupts = <3 1 0>;
interrupt-parent = <&dw_intc>;
gpio-controller;
@ -118,7 +116,7 @@
reg = <0x80800 0x400>;
label = "UART_0";
clock-frequency = <38400000>;
interrupts = <IRQ_DW(3) 0 0>;
interrupts = <2 0 0>;
interrupt-parent = <&dw_intc>;
@ -131,7 +129,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80400 0x400>;
interrupts = <IRQ_DW(2) 0 0>;
interrupts = <1 0 0>;
interrupt-parent = <&dw_intc>;
label = "I2C_0";
@ -144,7 +142,7 @@
#size-cells = <0>;
reg = <0x0000E000 0x400>;
clocks = <&sysclk>;
interrupts = <IRQ_DW(7) 0 0>;
interrupts = <6 0 0>;
interrupt-parent = <&dw_intc>;
label = "SPI_0";
};

3
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -36,8 +36,7 @@
#define DT_CAVS_ICTL_3_IRQ_FLAGS DT_INTEL_CAVS_INTC_78830_IRQ_0_SENSE
#define DT_DW_ICTL_BASE_ADDR DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
#define DT_DW_ICTL_IRQ ((DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(DT_INTEL_CAVS_INTC_78800_IRQ_0 << 0))
#define DT_DW_ICTL_IRQ DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0
#define DT_DW_ICTL_IRQ_PRI DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
#define DT_DW_ICTL_IRQ_FLAGS DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE