soc: intel_s1000: add DMIC power control
Add DMIC power on to SoC init sequence Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
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978bdf0d5d
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c3da9238f1
2 changed files with 26 additions and 5 deletions
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@ -186,12 +186,23 @@ u32_t soc_get_ref_clk_freq(void)
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static void soc_set_power_and_clock(void)
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{
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volatile struct soc_dsp_shim_regs *regs =
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(volatile struct soc_dsp_shim_regs *)
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SOC_DSP_SHIM_REG_BASE;
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volatile struct soc_dsp_shim_regs *dsp_shim_regs =
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(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
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#if (CONFIG_AUDIO_INTEL_DMIC)
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volatile struct soc_dmic_shim_regs *dmic_shim_regs =
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(volatile struct soc_dmic_shim_regs *)SOC_DMIC_SHIM_REG_BASE;
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regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK | SOC_CLKCTL_OCS_FAST_CLK;
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regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 |
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/* enable power */
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dmic_shim_regs->dmiclctl |= SOC_DMIC_SHIM_DMICLCTL_SPA;
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while ((dmic_shim_regs->dmiclctl & SOC_DMIC_SHIM_DMICLCTL_CPA) == 0) {
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/* wait for power status */
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}
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#endif
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dsp_shim_regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK |
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SOC_CLKCTL_OCS_FAST_CLK;
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dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 |
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SOC_PWRCTL_DISABLE_PWR_GATING_DSP0;
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}
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@ -117,6 +117,16 @@ struct soc_resource_alloc_regs {
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u32_t geno;
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};
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/* DMIC SHIM Registers */
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#define SOC_DMIC_SHIM_REG_BASE 0x00071E80
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#define SOC_DMIC_SHIM_DMICLCTL_SPA BIT(0)
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#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
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struct soc_dmic_shim_regs {
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u32_t dmiclcap;
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u32_t dmiclctl;
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};
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/* SOC DSP SHIM Registers */
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#define SOC_DSP_SHIM_REG_BASE 0x00071F00
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/* SOC DSP SHIM Register - Clock Control */
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