Commit graph

23 commits

Author SHA1 Message Date
Kumar Gala
79e0ab743e soc: xtensa: linker: Update linker scripts for C++ build
When we link in crtbegin.o for C++ exception support we end up pulling
in the .tm_clone_table section.  We need to update the linker scripts
to handle this.  soc/xtensa/sample_controller/linker.ld was already
updated, this fixes the others.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-05-28 09:32:44 -05:00
Daniel Leung
c7ed7e492b xtensa: intel_s1000: enable thread local storage
Adds the bits to enable thread local storage for
intel_s1000 SoC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-10-24 10:52:00 -07:00
Stephanos Ioannidis
3322489d22 config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between
the beginning of the ROM area and the address of the first ROM section.

This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because
the first ROM section is not always the `.text` section.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-07-09 14:02:38 -04:00
Kumar Gala
8aeb8a3814 soc: xtensa: rework DT_L2_SRAM and DT_L2_SRAM
Rename DT_L2_SRAM_* to just L2_SRAM_* and set it using new DT macros.
Do something similar for DT_LP_SRAM_* renamed to LP_SRAM_*

Updated the intel_gna driver as it used the DT_L2_SRAM_* defines.

This change also lets us remove dts_fixup.h on intel_s1000 and
intel_apl_adsp SoCs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-25 09:32:00 -05:00
Daniel Leung
0ba204083d soc: intel_s1000: add SMP support
This adds SMP support for Intel S1000 SoC.

Some of the start-up code is borrowed from ESP32.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-03-25 19:07:28 -04:00
Ulf Magnusson
4e85006ba4 dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}
generated_dts_board.h is pretty redundant and confusing as a name. Call
it devicetree.h instead.

dts.h would be another option, but DTS stands for "devicetree source"
and is the source code format, so it's a bit confusing too.

The replacement was done by grepping for 'generated_dts_board' and
'GENERATED_DTS_BOARD'.

Two build diagram and input-output SVG files were updated as well, along
with misc. documentation.

hal_ti, mcuboot, and ci-tools updates are included too, in the west.yml
update.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-01-17 17:57:59 +01:00
Daniel Leung
fc42c82cb9 soc: intel_s1000: define default MEMCTL reg value
When not using XCC, XCHAL_CACHE_MEMCTL_DEFAULT is not defined
which results in some variables not being able to be defined.
So define them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Daniel Leung
c6f4a970f1 soc: intel_s1000: add _heap_sentry to linker script
Newlib requires a _heap_sentry so we add it to the linker script,
similar to what other xtensa linker scripts.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-13 06:26:10 -06:00
Kumar Gala
00c7ce7942 linker: move where we define _LINKER and _ASMLANGUAGE
Move _LINKER and _ASMLANGUAGE to target.cmake because of how we pick the
linker script that might be used.  This way regardless of how or where a
linker.ld gets included we will always set _LINKER & _ASMLANGUAGE (so
any header that needs check based on those defines they can,
specifically generated_dts_board.h)

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-11-03 12:55:16 +01:00
Jan Van Winkel
70fb574a6e linker: cxx: xtensa: Added .gcc_except_table.*
Make sure that all sub-sections of .gcc_except_table are mapped in
rodata else C++ builds with exceptions enabled will generate warnings
due to orphan sections.

Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
2019-09-19 09:26:42 -05:00
Sathish Kuttan
876deb420d soc: intel_s1000: add lpsram in linker script
Add LPSRAM definition in MEMORY
Place DMA buffer section in LPSRAM

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-06-11 16:36:30 -04:00
Daniel Leung
7fe29dcee9 soc: intel_s1000: change cached regions to write-through
The i2s_cavs.c driver manipulates cache lines before commencing
any DMA transfers. With write-back cache, if the DMA receive
buffer is not aligned to the cache lines, the data around
the buffer will be invalidated and may never written to memory.
Since the driver takes an external memory slab as buffer and
there is no easy way to force cache line alignment on
the application side, set the cached region to write-through
to avoid potential issue.

Fixes #13223

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-04-12 17:59:06 -04:00
Daniel Leung
1e7025c2e7 boards: intel_s1000_crb: fix setting cache attributes
This reverts commit c9ace83c89 which
bypasses setting cache attributes.

The previous cache attributes actually set the text/data/etc.
sections to be inaccessible. So fix it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-15 16:21:50 -05:00
Rajavardhan Gundi
4df8ba3fe0 linker: intel_s1000: Remove limits on code and data sections
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.

Fixes #11268.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-12-10 22:05:06 -05:00
Rajavardhan Gundi
022990f73d xtensa: Implement CONFIG_TEXT_SECTION_OFFSET
CONFIG_TEXT_SECTION_OFFSET allows the entire image to be moved
in memory to allow space for some type of header. The mcubootloader
can boot only such images which reserve some space for the header.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2018-12-05 15:48:49 +01:00
Andrzej Głąbek
20202902f2 dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig
These changes were obtained by running a script  created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:

1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
   #define X Y)
3. Check if that name is also the name of a Kconfig option
   3.a If it is, then do nothing
   3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
       has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
   (.c, .h, .ld)

Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.

Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 10:44:42 -06:00
Andrew Boie
506f15c381 interrupts: simplify position of sw ISR table
We now place the linker directives for the SW ISR table
in the common linker scripts, instead of repeating it
everywhere.

The table will be placed in RAM if dynamic interrupts are
enabled.

A dedicated section is used, as this data must not move
in between build phases.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-10 11:01:22 -05:00
Sathish Kuttan
3d19f891a3 soc: intel_s1000: GNA model - linker script entry
Add a linker script entry for embedding a GNA model at a
4KB page aligned address in .data section

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-11-08 17:08:19 -05:00
Daniel Leung
c229126f55 xtensa: intel_s1000: turn on XTENSA_ASM2
This adds the necessary bits to support ASM2 with XCC
for Intel S1000 SoC. With ASM2 enabled, xcc is now
required to build for Intel S1000 SoC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 17:52:45 -04:00
Daniel Leung
6600c64331 linker: warn about orphan sections
(Previous patch set was reverted due to issue with priv_stack.
 Resubmitting after fixing the faults caused by priv_stack.noinit
 not at the end of RAM.)

This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.

Relates to #5534.

Fixes #10473, #10474, #10515.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-19 16:11:34 -04:00
Anas Nashif
0d4b5daeaa Revert "linker: warn about orphan sections"
This reverts commit 8ce758a8ff.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-10-14 12:14:04 -04:00
Daniel Leung
8ce758a8ff linker: warn about orphan sections
This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.

Relates to #5534.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2018-10-09 08:23:41 -04:00
Anas Nashif
cea0b3a9c2 xtensa: move soc to top-level dir soc/
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Renamed from arch/xtensa/soc/intel_s1000/linker.ld (Browse further)