Commit graph

5973 commits

Author SHA1 Message Date
Yuval Peress
86cadf9283 ztest: Fix userspace ztests in new API
Update the new API to use K_USER as the flags for both
CONFIG_USERSPACE and CONFIG_TEST_USERSPACE. Also, fix the linker
script to properly include the suites, tests, and rules.

Fixes #44108

Signed-off-by: Yuval Peress <peress@google.com>
2022-05-25 11:20:13 +09:00
Stephanos Ioannidis
b2c8f26e34 soc: npcx: scripts: Initialise Colorama during module load
This commit adds a call to the Colorama initialisation function during
the module execution so that ANSI color sequences are properly
converted to the relevant Win32 API calls on the Windows.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-24 09:00:16 -07:00
Filip Kokosinski
70c978bb97 soc/riscv/sifive-freedom/fe310: use correct SYS_CLOCK_HW_CYCLES_PER_SEC
This commit introduces changes in three places in order to fix the
problem with timer-related tests on FE310-based boards:
* tests/kernel/sleep/kernel.common.timing
* tests/kernel/tickless/tickless_concept/kernel.tickless.concept
* tests/kernel/workq/work_queue/kernel.workqueue

The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC
value back to 32768 Hz to match FE310's datasheet description.

The second change is CLINT frequency reduction in Renode simulation
model to 16 MHz to correspond with the oscillator frequency given by the
FE310's datasheet and the HiFive1 board schematic. This fixes the first
two tests.

The last change is reducing the MIN_DELAY define to 100. This causes the
RISC-V machine timer driver to update the mtimecmp register more often,
which in turn addresses the `work_queue/kernel.workqueue` problem with
work items finishing prematurely, causing the above-mentioned test to
fail.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-05-24 08:58:43 -07:00
Lukasz Majewski
0f9c8c2935 arm: stm32h7: Enable DCache when CONFIG_DCACHE is defined
Up till now the usage of CONFIG_NOCACHE_MEMORY also explicitly disables
data cache on the STM32H7 SoC.

With this change the usage of CONFIG_NOCACHE_MEMORY has been decoupled
from data cache enabling as new Kconfig option - namely
CONFIG_DCACHE is now used to explicitly enable it.

After this change it would be possible to use data cache on STM32H7
with DMA buffers, fragile to cache coherency issues, defined with
'__nocache' attribute.

Such approach would improve the overall STM32H7 performance until the
moment when proper (i.e. in-DMA) buffer cache management is developed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-05-24 08:47:20 -07:00
Sylvio Alves
8148449db0 soc: esp32: move libc strings in dram area
Move libc strings to RAM area so that ESP32
doesn't crash when flash cache is disabled

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-20 12:36:36 +02:00
Mulin Chao
0f18c4c4ab pinctrl: npcx: config pwm open-drain without enabling STORE_REG
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-05-20 12:36:22 +02:00
Jose Alberto Meza
4e443dac34 soc: arm: microchip: mec172x: Enclose macro in brackets
Macro should be in brackets.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-05-20 12:35:37 +02:00
Krzysztof Chruscinski
99fb57652a soc: arm: nordic: Change tick rate for non-tickless kernel
Set SYS_CLOCK_TICKS_PER_SEC to 128 for non-tickless kernel.
Previously it was set to 32768 disregarding kernel mode and that
lead to too frequent interrupts in non-tickless mode (tick every
30 us). Change to smaller value.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-05-19 11:03:50 +02:00
Nicolas Pitre
1cb557dccf riscv: rationalize PMP related Kconfig options
ARCH_HAS_USERSPACE and ARCH_HAS_STACK_PROTECTION are direct functions
of RISCV_PMP regardless of the SoC.

PMP_STACK_GUARD is a function of HW_STACK_PROTECTION (from
ARCH_HAS_STACK_PROTECTION) and not the other way around.

This allows for tests/kernel/fatal/exception to test protection against
various stack overflows based on the PMP stack guard functionality.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-05-18 10:54:53 +02:00
Sylvio Alves
f3d2dd2b6c soc: esp32: move phy tx power to soc config
PHY TX power configuration must be added into soc level.
It was previously hardcoded in hal_espressif, which was removed.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-17 18:11:50 +02:00
Henrik Brix Andersen
a195f98265 soc: arm: gigadevice: undefine CAN_MODE_NORMAL
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-16 12:56:50 +02:00
Henrik Brix Andersen
957000c9d8 soc: riscv: privilege: gd32vf103: undefine CAN_MODE_NORMAL
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.

Fixes: #45611

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-16 12:56:50 +02:00
Nazar Palamar
5a99e93d69 soc: arm: cypress: Update PSoC 6 implementation to use mtb-pdl-cat1
Updated PSoC 6 implementation to use hal_infineon/mtb-pdl-cat1

This PR is reflected changes according to Task#1 for RFC#42883.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2022-05-13 21:34:59 +02:00
Thomas Altenbach
cc51031445 drivers/entropy: stm32: fix inter-core race condition
On STM32WB and dual-core STM32H7 MCUs, the RNG peripheral is shared
between the cores and its access is protected by a hardware semaphore.
Locking was not performed in the current entropy driver, leading to a
race condition when multiple cores concurrently used the RNG. This
commit implements the necessary logic for locking the HSEM during entropy
generation on multi-core STM32 MCUs. It also reconfigures the RNG in case
the configuration was changed by the other core, as this can happen e.g
on STM32WB MCUs.

Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
2022-05-13 10:28:53 -05:00
Daniel DeGrasse
946b9dc1e1 boards: imx8mm: add partial pin control support
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
dea2e642b2 soc: mimx8ml8_m7: add pin control support for mimx8ml8_m7
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
e1ef51ce39 soc: mimx8mm6_m4: add pin control support.
Add pin control support for mimx8mm6_m4 IOMUXC peripheral.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
e3b4c0b314 soc: mimx8mq6_m4: add pin control support
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
5d374d7b29 soc: mcimx7_m4: add pin control support
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
e5fd7d8e67 soc: mcimx6x_m4 add pin control support
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
bc841e1fb7 drivers: pinctrl: refactor pin control support for imx rt
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Mulin Chao
d53d574bf0 drivers: pinctrl: npcx: add initial pin-controller driver
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-05-12 14:24:03 -05:00
Mahesh Mahadevan
14ed412359 soc: rt: Add MIPI support for MXRT1170
Add MIPI support for NXP's MXRT1170

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-05-12 09:26:50 -05:00
Gerard Marull-Paretas
9678bd6970 pinctrl: nrf: prefix custom drive-mode property
The drive-mode property is nRF specific, so prefix it with `nordic,`,
same as the `nordic,invert` property.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-12 09:22:12 +02:00
Jun Lin
51978d9d61 driver: eSPI: npcx: workaround the errata rev1_2, No.3.10
Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel,
etc.) during an eSPI transaction might (with low probability) cause the
eSPI_SIF module to transition to a wrong state and therefore response
with FATAL_ERROR on an incoming transaction.
This CL workarounds this issue by clearing the bit 4 of NPCX eSPI
specific register#2.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-05-12 09:21:24 +02:00
Henrik Brix Andersen
3f97d11afd drivers: can: convert enum can_mode to a bit field
Convert the can_mode enum to a bit field to prepare for future extensions
(CAN-FD mode, transmitter delay compensation, one-shot mode, 3-samples
mode, ...).

Rename the existing modes:
- CAN_NORMAL_MODE   -> CAN_MODE_NORMAL
- CAN_SILENT_MODE   -> CAN_MODE_LISTENONLY
- CAN_LOOPBACK_MODE -> CAN_MODE_LOOPBACK

These mode names align with the Linux naming for CAN control modes.

The old CAN_SILENT_LOOPBACK_MODE can be set with the bitmask
(CAN_MODE_LISTENONLY | CAN_MODE_LOOPBACK).

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-11 10:47:54 +02:00
Georgij Cernysiov
827343a3da soc: stm32: h7: add support for stm32h730xx
Adds support for STM32H730XX SoC.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-05-11 10:47:43 +02:00
Sylvio Alves
896809bfcc soc: esp32s2: add _gettimeofday_r workaround
Add reentrant _gettimeofday_ call so that build
won't fail. This is only a workaround for now.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Sylvio Alves
9d4d144377 linker: esp32s2: changes to enable newlibc and cpp support
This PR adds missing configuration to enable newlibc
and cpp code to run in ESP32S2 SoC. This isn't enough though.
Toolchain changes are also needed and will come up next.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Sylvio Alves
bb077a3d82 soc: esp32c3: linker changes to enable newlibc and cpp
Adds linker changes to enable cpp and newlibc code.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Sylvio Alves
3b83e39e16 soc: esp32: decrease region 1 default pool size
Make the available heap for the 128k bank smaller
so that it frees up space for some samples
as pktqueue and smp. In the context of toolchain,
this enables having twister test to pass in those tests
that requires more memory.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Sylvio Alves
c9f6d18dfc soc: esp32: add Espressif HAL config
Current Espressif porting requires standard include as
part of hal implementation. compiler_flags.cmake checks for
variant name to keep those stdinc in build.
Instead of using variant name as check, use this new CONFIG
to make it clear and to allow having toolchain integrated
in zephyr-sdk package.
stdinc dependency in hal_espressif will be worked out and removed
soon.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Sylvio Alves
a53e3c1b2b soc: esp32: add toolchain name
Add ESP32 and ESP32S2 toolchain name that is addressed
when integrated with zephyr-sdk.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Sylvio Alves
b6ab394d14 soc: esp32: add _gettimeofday_r workaround
Add reentrant _gettimeofday_ call so that build
won't fail. This is only a workaround for now.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Sylvio Alves
e131679d99 linker: esp32: changes to enable newlibc and cpp support
This PR adds missing configuration to enable newlibc
and cpp code to run in ESP32 SoC. This isn't enough though.
Toolchain changes are also needed and will come up next.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-11 10:47:27 +02:00
Daniel DeGrasse
fed6d6b754 soc: lpc11u6x: enable pin control
Enable pin control for lpc11u6x soc by selecting CONFIG_PINCTRL=y.
At this time no drivers are ported.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-10 17:27:44 -05:00
Daniel DeGrasse
dc4d168952 soc: lpc11u6x: add pin control header
add pin control header to enable pin control support for lpc11u6x

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-10 17:27:44 -05:00
Daniel DeGrasse
ea9df42b25 soc: lpc11u6x: add pin control definitions to LPC11u6x soc file
add pin control definitions to LPC11u6x soc file, to handle the lack of
a HAL for this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-10 17:27:44 -05:00
Evgeniy Paltsev
bb6c89bef8 ARC: boards: allow MWDT toolchain for nsim_hs6x and nsim_hs6x_smp
Allow MWDT toolchain and add corresponding compiler options
for nsim_hs6x and nsim_hs6x_smp.

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2022-05-10 14:12:25 -04:00
Evgeniy Paltsev
d5038c49ba ARC: boards: add nsim_hs5x and nsim_hs5x_smp boards
Add nSIM-based (simulator) boards with
 * nsim_hs5x - single core ARCv3 HS5x 32 bit CPU
 * nsim_hs5x_smp - SMP, two core ARCv3 HS5x 32 bit CPU

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2022-05-10 14:12:25 -04:00
Esteban Valverde
11ba0802b5 soc: arm: Add Cyclone V SoC FPGA Support
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).

Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
2022-05-10 13:29:47 -04:00
Andrzej Głąbek
e7b389ddf5 dts: nordic: Add missing qdec0 node labels
This is a follow-up to commit 586e26e8fc.

Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-05-10 18:41:14 +02:00
Bernardo Perez Priego
2fc78a9b39 drivers: adc: Add threshold_reg_offset to NPCX adc config structure
ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
2022-05-10 18:40:24 +02:00
Piotr Dymacz
15b22e066f soc: arm: cc13x2_cc26x2: Kconfig: select CPU_HAS_ARM_MPU
This adds missing 'CPU_HAS_ARM_MPU' for Texas Instruments SimpleLink
CC13x2 and CC26x2 SoC series.

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
2022-05-10 18:33:50 +02:00
Flavio Ceolin
99be4358af soc: nxmp: rt10xx: Fix pm callbacks
The pm hooks for this target were not updated to follow the current API.
These weak functions will never be called for the pm subsystem.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-05-10 09:44:17 -05:00
Eugene Cohen
816229128d arch/arm64: update gicv3 sre enablement
Fix writing of ICC_SRE_EL3 to or-in bits to align
with original intent to read-modify-write this
register.

Also disable FIQ and IRQ bypass so interrupt delivery
occurs through GIC.  Platforms may choose to override
this behavior in z_arm64_el3_plat_init implementations.

Remove ICC_SRE_EL3 config from viper and qemu since
this is now handled in the arm64 arch core.

Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com>
2022-05-10 09:13:20 +02:00
Gerard Marull-Paretas
26a924a44e soc: riscv: mpfs: update include paths
Use the <zephyr/...> prefix.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas
4b91c2d79f asm: update files with <zephyr/...> include prefix
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas
d342e4c4c1 linker: update files with <zephyr/...> include prefix
Linker files were not migrated with the new <zephyr/...> prefix.  Note
that the conversion has been scripted, refer to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Henrik Brix Andersen
03bece0b70 soc: arm: atmel: samv71: enable the UPLL clock
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-05-09 09:27:40 +02:00