Commit graph

5973 commits

Author SHA1 Message Date
Vaishnav Achath
e2ed8cf130 drivers: pinctrl: add CC13XX/CC26XX pinctrl driver
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.

`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.

Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
2022-04-18 18:19:46 -04:00
Ruibin Chang
4aa6e98292 ITE drivers/kscan: clean up it8xxx2 kscan driver
1.Declare the member type to match the kscan_it8xxx2_regs, so
we needn't to transform the local structure in the function.
2.Stop using DRV_CONFIG, DRV_DATA, DRV_REG macros.
3.Delete unused register defines.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-04-15 10:35:35 -07:00
Ryan McClelland
c5b59282d6 arch: arm: aarch32: add Kconfig for arm cortex-m that implements a cache
The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.

Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
2022-04-14 16:12:03 -05:00
Immo Birnbaum
ab5b451557 soc: arm: xilinx_zynq7000: remove unnecessary "EOF" comments
remove unnecessary EOF comment lines at the end of each file.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-04-14 14:43:52 -05:00
Daniel DeGrasse
65a3f3e468 soc: rt11xx: enable AHB clock during CM7 sleep
Zephyr kernel will always execute WFI in k_cpu_idle(), so access to TCM
will be gated. Keep the AHB clock enabled in sleep unless CONFIG_PM is
selected, to avoid this error.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-14 13:40:52 -05:00
Ederson de Souza
c0b7864840 arch/xtensa: Enable backtrace on panic on Intel ADSP platforms
Platform specific functions necessary to enable this feature were
implemented (z_xtensa_ptr_executable() and
z_xtensa_stack_ptr_is_sane() for Intel ADSP platforms.

Current implementation just ensures stack pointer and program counter
are within relevant areas defined in the linker scripts, without going
too fine grained.

Also, `.iram1` section, used by the backtrace code, also added to
Intel ADSP linker script.

Finally, update west manifest to use up-to-date SOF, which contains a
patch to fix build issues related to the linker changes.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-04-14 11:03:40 -04:00
Daniel DeGrasse
b15ac058fa soc: arm: add mpu REGION_FLASH_SIZE definitions for larger flash regions
Add MPU REGION_FLASH_SIZE definitions for 128M-512M flash sizes, to handle
arm SOCs with large flash regions.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-13 13:32:23 -07:00
Jay Vasanth
2e9c18cd0d emi: fix MEC172x emi registers fields size
Rectify reserved fields size in MEC172x emi_regs structure

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-04-13 08:52:57 -05:00
Frank Li
4651a38e5d soc: mxrt10xx: remove forces enable boot header
When we use a third-party or custom bootloader, there is also
need to remove the boot header. Change the select to imply,
so that the boot header can be removed by configuration when
MCUBoot is not used.

Signed-off-by: Frank Li <lgl88911@163.com>
2022-04-12 09:54:01 +02:00
Kai Vehmanen
5be08296d6 soc/intel_adsp: XTENSA_WAITI_BUG must be set of cAVS1.8 and newer
Align definitions with definitions used in SOF upstream and define
CONFIG_XTENSA_WAITI_BUG for cAVS1.8, cAVS2.0 and cAVS2.5 platforms. On
these platforms, a workaround is needed with waiti.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-04-11 08:29:06 -04:00
Alexander Vasiliev
a19311f3c7 soc: stm32: Fix DBGMCU register write for SWO configuration
DBGMCU register, which is used for SWO pin configuration,
may not have TRACE_MODE bits in some STM32 MCUs.
Replace register access with LL functions selected based on SoC family.

Fixes #44584

Signed-off-by: Alexander Vasiliev <alex.m.vasil@gmail.com>
2022-04-08 15:53:56 -07:00
Francois Ramu
40f76516d9 soc: arm: stm32 adjust wdt timer due to LSI oscillator characteristics
Due to a wide range of variuation in the LSI RC oscillator
characteristics given by the datasheet of the soc,
It is necessary to add a delay for hardware watchdog.
This is done by the CONFIG_TASK_WDT_HW_FALLBACK_DELAY

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-04-08 10:41:55 -05:00
Joakim Andersson
e74e8b2048 soc: nordic_nrf: Add soc_secure_mem_read implementation in secure
Add soc_secure_mem_read implementation for secure.
This simplifies users code so that ifdefs are not required.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-04-07 11:02:52 -04:00
Joakim Andersson
2dae1823ab hwinfo: Add dependency handling for HWINFO_NRF in nonsecure
The limitation on HWINFO_NRF depending on not nonsecure was removed in
52be3030aa.
This caused problems when TF-M was not enabled.

This happens on the thingy53_nrf5340_cpuapp_ns board since this board
is not supported by TF-M.

Introduce proper dependency handling for the soc secure functions
to make HWINFO_NRF unavailable when no secure services exist in
nonsecure.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-04-07 11:02:52 -04:00
Stephanos Ioannidis
b64b29cd2b Revert "soc/it8xxx2: enable FPU support"
This reverts commit b1ad97bc26 since it
causes the following build failure:

  cc1: error: requested ABI requires '-march' to subsume the 'F'
  extension

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-04-07 10:25:37 -04:00
Daniel DeGrasse
9226cf338e soc: add lpc pinctrl definition header
Add pinctrl definition header, to parse pinctrl groups in board level
DTS into pinctrl_soc_pin_t values.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-06 20:57:22 -07:00
Adrian Bonislawski
a52aa7f2ab soc/intel_adsp: set default cavs kconfig to cavs platforms only
This will set intel cavs kconfig to cavs platforms only

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-04-06 14:43:18 -04:00
Shawn Nematbakhsh
2a9b2dd7b9 soc: riscv: sifive-freedom: Revert whitespace mistake.
Revert the deleted spaces from PR#42280 / c74526919.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 17:09:40 -04:00
Shawn Nematbakhsh
a8ffd19281 soc: riscv: sifive-freedom: fe310: Support custom coreclk rate in DTS.
Allow coreclk to be configured up to 320 MHz from DTS.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 12:00:03 +02:00
Shawn Nematbakhsh
c74526919d soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.

This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2022-04-05 12:00:03 +02:00
Peter Marheine
b1ad97bc26 soc/it8xxx2: enable FPU support
IT8xxx2 supports the standard 'F' extension for single-precision
floating point: select the relevant Kconfig option for the SoC so
users can build floating-point code.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ie6da1d38d5654061553cb1ce13b0a0a96aa71ce0
2022-04-05 11:18:40 +02:00
Gerard Marull-Paretas
c925b5991a include: remove unnecessary autoconf.h includes
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-05 11:18:20 +02:00
Jay Vasanth
9777c5e90e drivers: peci: Microchip XEC PECI driver add MEC172x support
Update Microchip XEC PECI driver to support MEC172x.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-04-05 11:16:41 +02:00
Carlo Caione
b91d21d32c dt: mpu: Generate MPU regions from DT nodes
Currently the only way for a BOARD/SOC to configure at compile time the
MPU regions is to add, in a soc-specific file, the 'mpu_config' struct
adding static entries for the new regions with the needed attributes
(cacheable, non-cacheable, etc...). This exported struct is then read by
the MPU driver at boot time and used to properly setup the MPU regions.

At the same time it is now possible to introduce new memory regions in
the DT using the newly introduced 'zephyr,memory-region' attribute.

What is missing is the link between these two solutions: that is how to
declare the memory regions in the DT and automatically configure these
regions in the MPU with the correct attributes.

This patch is trying to address exactly this problem.

It is now possible to declare the memory regions in the DT and define
the MPU attributes for the regions using the 'zephyr,memory-region-mpu'
property. When this new property is present together with the
'zephyr,memory-region' property and a the 'zephyr,memory-region'
compatible, the 'mpu_config' struct is automatically extended at
compile-time to host the DT defined regions with the correct MPU
attributes.

So for example in the DT we can now have:

       sram_cache: memory@20200000 {
                compatible = "zephyr,memory-region", "mmio-sram";
                reg = <0x20200000 0x100000>;
                zephyr,memory-region = "SRAM_CACHE";
                zephyr,memory-region-mpu = "RAM";
        };

and a new region will be created called "SRAM_CACHE" and a new MPU
region will be configure at boot time with the attribute
"REGION_RAM_ATTR".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-04-05 11:16:31 +02:00
Yuval Peress
5416abfe5f util: convert wait_for macro to uppercase
This macro conflicts with C++'s std::condition_variable::wait_for
and makes it very difficult to use Zephyr with C++. Replace it with
an all uppercase name which fits the naming standard better.

Signed-off-by: Yuval Peress <peress@google.com>
2022-04-04 09:50:28 -05:00
Joakim Andersson
02bd034255 soc: nordic_nrf: Add soc_secure_read_deviceid
Add soc_secure_read_deviceid function for reading the device ID from
FICR when executing in non-secure processing environment.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-04-04 11:15:28 +02:00
Joakim Andersson
6a14a0233b soc: nordic_nrf: Refactor soc_secure handling
Refactor soc_secure handling to not use TF-M directly in the header.
Move from nRF53 to common since nRF91 also supports TF-M.

Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
2022-04-04 11:15:28 +02:00
Andrzej Głąbek
586e26e8fc soc: nrf: Use data from DTS to populate HAS_HW_NRF_* Kconfig options
Instead of selecting appropriate HAS_HW_NRF_* options for particular
nRF SoCs (and simulated nRF52 target), set their values basing on
information from devicetree.
Correct also semantics of those options so that they are set only when
a corresponding DT node is enabled. This allows using them directly in
Kconfig dependencies of Zephyr drivers for nRF peripherals. Update
appropriately these dependencies.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-04-02 15:14:38 +02:00
Andrzej Głąbek
56a1ac3817 dts: Add missing nodes and bindings for peripherals present in nRF SoCs
Add missing devicetree nodes representing the following peripherals
in nRF SoCs:
- ACL
- BPROT
- CCM
- COMP/LPCOMP
- CTRLAP
- DCNF
- MPU (nRF MPU peripheral in nRF51 Series, not ARM MPU)
- MUTEX
- MWU
- NFCT
- OSCILLATORS
- POWER (in nRF51 and nRF52 Series)
- PPI
- RESET
- SWI
- USBREG
Add also corresponding bindings and validation of base addresses of
these nodes.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-04-02 15:14:38 +02:00
David Leach
314e8484e2 hal: nxp: Centralize handling of SDK custom sections
The NXP SDK defines CodeQuickAccess and DataQuickAccess sections
for locating critical items that need faster access. Centralize
the handling of these sections instead of doing it per SOC.

Fixes #44453

Signed-off-by: David Leach <david.leach@nxp.com>
2022-04-02 13:30:44 +02:00
Dino Li
5b9db5a251 it8xxx2: re-factor idle routine
Don't leave idle state if soc isn't waked-up by an interrupt.
(We change to check interrupt controller register)

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-04-01 12:49:09 -05:00
Ruibin Chang
aefe13f86c ITE boards/riscv/it8xxx2_evb: define CONFIG_SYS_CLOCK_TICKS_PER_SEC
When run the test_mutex_lock_timeout(), we need more time (>300us)
for the testing thread to finish the job, or we will get a fail
(we didn't run the test before).

Because our event timer doesn't handle the float part, and 32768 is
divisible by 8192 which is closest to kernel tick default 10000, I add
CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192 for all board of it8xxx2 series.

If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 32768,
the 10 tick of timeout = 300us.
If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192,
the 10 tick of timeout = 1200us.
So we can get more time to finish the job.

Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/sleep
west build -p auto -b it8xxx2_evb tests/subsys/portability/cmsis_rtos_v2

fixes #43513
fixes #42847

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-04-01 12:33:11 -05:00
Tom Burdick
9933f18ad3 dma/cavs_hda: Provide pending/free byte lengths
In status the pending/free byte lengths are now provided

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-04-01 09:12:20 -04:00
Tom Burdick
602ef3fb0e soc/intel_adsp: Require definitions for cavs_hda.h
Rather than defining them in the header, require a set of defines
be provided to cavs_hda.h as part of the expected input to the API.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-04-01 09:12:20 -04:00
Tom Burdick
e018a3dff7 dma/cavs_hda: DMA driver for HDA on cAVS
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.

Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF

Simple test case is provided for both drivers.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-04-01 09:12:20 -04:00
Tom Burdick
cc6e9c094a soc/intel_adsp: Low level HDA driver and tests
Adds a header only low level driver for HDA streams along with smoke
tests to ensure basic host in and out stream functionality.

The tests require host side interaction. In cavstool a new HDAStream
class encapsulates somewhat a single stream and its registers. This
is manipulated in the tests using IPC with the Host ensuring that a
specific order of operations is done.

This low level driver allows testing certain hardware configurations
and flows with easy to use register dump debugging. It is not
intended to be the end API an application might use. That would be
a DMA driver using this.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-04-01 09:12:20 -04:00
Tom Burdick
345a536794 soc/intel_adsp: common testing code in cavstool.h
The IPC enum definition and WAIT_FOR macro are useful outside of
the board smoke tests for intel_adsp. They can be commonly used
by other board tests for a variety of peripherals that require
DSP and Host interaction (using cavstool).

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-04-01 09:12:20 -04:00
Jose Alberto Meza
5a3f528387 soc: arm: microchip: mec172x: Fix eSPI flash operations
Correct eSPI flash macro so it not always results in zero,
leading to eSPI flash read operation in all cases:
Read, write, erase.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-03-31 18:11:48 -04:00
Jose Alberto Meza
4430aa22ca soc: arm: microchip: mec172x: Fix PWM dependency
Enable PWM_XEC whenever CONFIG_PWM is selected

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-03-31 15:51:56 -04:00
Johan Öhman
5d51fbc8cb mpu: Support for 8 & 16 MB SRAM regions in Cortex M MPU
Added support for 8 MB MPU regions for SRAM sizes between 4 and 8 MB,
and 16 MB MPU regions for SRAM sizes between 8 and 16 MB.

Signed-off-by: Johan Öhman <johan.ohman@softube.com>
2022-03-31 12:04:00 -05:00
Ruibin Chang
43213a16a8 ITE drivers/timer: customize busy wait timer
Customize busy wait timer for micro-seconds accuracy.

Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
west build -p auto -b it8xxx2_evb tests/drivers/adc/adc_api

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-03-30 11:31:06 +02:00
Sylvio Alves
d2ea3e715d soc: esp32: linker: exclude smp source from rom area
SMP support might not work if esp_mp.c initialization code
is placed in ROM area. This fix that scenario.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-03-29 10:28:23 -05:00
Kai Vehmanen
199048b2ed soc/intel_adsp: boot: simplify the ifdef rules for cAVS versions
Only cAVS15 is different in terms of definitions, so the ifdef logic can
be simplified quite a bit. Also reorder some of the definitions to
improve readability. No functional change.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-03-28 14:03:41 -04:00
Kai Vehmanen
3cead66939 soc/intel_adsp: fetch HPSRAM bank count from devicetree
Replace the Kconfig ifdefs with direct query from devicetree.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-03-28 14:03:41 -04:00
Kamil Piszczek
cb0d8c262f soc: arm: nordic_nrf: enable shared memory reset for nRF53 App Core
Enabled the Shared Memory Reset feature for nRF5340 Application Core
when the RPMsg backend for IPC Service is enabled.

Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
2022-03-28 12:46:32 +02:00
Erwan Gouriou
48039bc555 drivers/pinctrl: stm32: Allow plain GPIO configuration
Based on introduction of plain GPIO configurations in STM32 pinctrl
bindings, update STM32 pinctrl/gpio drivers to make this functionality
available.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-25 15:52:02 -07:00
Erwan Gouriou
7b9a00a074 soc/arm/st_stm32: pinctrl: Prepare pinmux removal
Some pinctrl related definitions are still defined
in pinmux related files.
Duplicate definitions to prepare pinmux removal.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-03-25 15:52:02 -07:00
Ruibin Chang
a21d043f5b ITE drivers/sensor: add voltage comparator driver
Add voltage comparator driver for ITE it8xxx2 chip.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-03-25 15:00:35 -07:00
Daniel DeGrasse
8c115a26e0 soc: nxp_imx: rt: remove unnecessary pinmux callbacks
All iMX RT 1xxx boards are now expected to use pin control, so the USDHC
pinmuxing callbacks can be removed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 15:47:54 -05:00
Daniel DeGrasse
8fd1b54a82 soc: nxp_imx: rt: enable ethernet ref clock output
Enable soc ethernet ref clock output at the SOC level instead of board
level, since it is required for all iMX.RT SOCs

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 15:47:54 -05:00