Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
1.Declare the member type to match the kscan_it8xxx2_regs, so
we needn't to transform the local structure in the function.
2.Stop using DRV_CONFIG, DRV_DATA, DRV_REG macros.
3.Delete unused register defines.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Zephyr kernel will always execute WFI in k_cpu_idle(), so access to TCM
will be gated. Keep the AHB clock enabled in sleep unless CONFIG_PM is
selected, to avoid this error.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Platform specific functions necessary to enable this feature were
implemented (z_xtensa_ptr_executable() and
z_xtensa_stack_ptr_is_sane() for Intel ADSP platforms.
Current implementation just ensures stack pointer and program counter
are within relevant areas defined in the linker scripts, without going
too fine grained.
Also, `.iram1` section, used by the backtrace code, also added to
Intel ADSP linker script.
Finally, update west manifest to use up-to-date SOF, which contains a
patch to fix build issues related to the linker changes.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add MPU REGION_FLASH_SIZE definitions for 128M-512M flash sizes, to handle
arm SOCs with large flash regions.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When we use a third-party or custom bootloader, there is also
need to remove the boot header. Change the select to imply,
so that the boot header can be removed by configuration when
MCUBoot is not used.
Signed-off-by: Frank Li <lgl88911@163.com>
Align definitions with definitions used in SOF upstream and define
CONFIG_XTENSA_WAITI_BUG for cAVS1.8, cAVS2.0 and cAVS2.5 platforms. On
these platforms, a workaround is needed with waiti.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
DBGMCU register, which is used for SWO pin configuration,
may not have TRACE_MODE bits in some STM32 MCUs.
Replace register access with LL functions selected based on SoC family.
Fixes#44584
Signed-off-by: Alexander Vasiliev <alex.m.vasil@gmail.com>
Due to a wide range of variuation in the LSI RC oscillator
characteristics given by the datasheet of the soc,
It is necessary to add a delay for hardware watchdog.
This is done by the CONFIG_TASK_WDT_HW_FALLBACK_DELAY
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add soc_secure_mem_read implementation for secure.
This simplifies users code so that ifdefs are not required.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The limitation on HWINFO_NRF depending on not nonsecure was removed in
52be3030aa.
This caused problems when TF-M was not enabled.
This happens on the thingy53_nrf5340_cpuapp_ns board since this board
is not supported by TF-M.
Introduce proper dependency handling for the soc secure functions
to make HWINFO_NRF unavailable when no secure services exist in
nonsecure.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
This reverts commit b1ad97bc26 since it
causes the following build failure:
cc1: error: requested ABI requires '-march' to subsume the 'F'
extension
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Add pinctrl definition header, to parse pinctrl groups in board level
DTS into pinctrl_soc_pin_t values.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.
This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
IT8xxx2 supports the standard 'F' extension for single-precision
floating point: select the relevant Kconfig option for the SoC so
users can build floating-point code.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ie6da1d38d5654061553cb1ce13b0a0a96aa71ce0
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently the only way for a BOARD/SOC to configure at compile time the
MPU regions is to add, in a soc-specific file, the 'mpu_config' struct
adding static entries for the new regions with the needed attributes
(cacheable, non-cacheable, etc...). This exported struct is then read by
the MPU driver at boot time and used to properly setup the MPU regions.
At the same time it is now possible to introduce new memory regions in
the DT using the newly introduced 'zephyr,memory-region' attribute.
What is missing is the link between these two solutions: that is how to
declare the memory regions in the DT and automatically configure these
regions in the MPU with the correct attributes.
This patch is trying to address exactly this problem.
It is now possible to declare the memory regions in the DT and define
the MPU attributes for the regions using the 'zephyr,memory-region-mpu'
property. When this new property is present together with the
'zephyr,memory-region' property and a the 'zephyr,memory-region'
compatible, the 'mpu_config' struct is automatically extended at
compile-time to host the DT defined regions with the correct MPU
attributes.
So for example in the DT we can now have:
sram_cache: memory@20200000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20200000 0x100000>;
zephyr,memory-region = "SRAM_CACHE";
zephyr,memory-region-mpu = "RAM";
};
and a new region will be created called "SRAM_CACHE" and a new MPU
region will be configure at boot time with the attribute
"REGION_RAM_ATTR".
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This macro conflicts with C++'s std::condition_variable::wait_for
and makes it very difficult to use Zephyr with C++. Replace it with
an all uppercase name which fits the naming standard better.
Signed-off-by: Yuval Peress <peress@google.com>
Add soc_secure_read_deviceid function for reading the device ID from
FICR when executing in non-secure processing environment.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Refactor soc_secure handling to not use TF-M directly in the header.
Move from nRF53 to common since nRF91 also supports TF-M.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Instead of selecting appropriate HAS_HW_NRF_* options for particular
nRF SoCs (and simulated nRF52 target), set their values basing on
information from devicetree.
Correct also semantics of those options so that they are set only when
a corresponding DT node is enabled. This allows using them directly in
Kconfig dependencies of Zephyr drivers for nRF peripherals. Update
appropriately these dependencies.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing devicetree nodes representing the following peripherals
in nRF SoCs:
- ACL
- BPROT
- CCM
- COMP/LPCOMP
- CTRLAP
- DCNF
- MPU (nRF MPU peripheral in nRF51 Series, not ARM MPU)
- MUTEX
- MWU
- NFCT
- OSCILLATORS
- POWER (in nRF51 and nRF52 Series)
- PPI
- RESET
- SWI
- USBREG
Add also corresponding bindings and validation of base addresses of
these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The NXP SDK defines CodeQuickAccess and DataQuickAccess sections
for locating critical items that need faster access. Centralize
the handling of these sections instead of doing it per SOC.
Fixes#44453
Signed-off-by: David Leach <david.leach@nxp.com>
Don't leave idle state if soc isn't waked-up by an interrupt.
(We change to check interrupt controller register)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
When run the test_mutex_lock_timeout(), we need more time (>300us)
for the testing thread to finish the job, or we will get a fail
(we didn't run the test before).
Because our event timer doesn't handle the float part, and 32768 is
divisible by 8192 which is closest to kernel tick default 10000, I add
CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192 for all board of it8xxx2 series.
If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 32768,
the 10 tick of timeout = 300us.
If the CONFIG_SYS_CLOCK_TICKS_PER_SEC = 8192,
the 10 tick of timeout = 1200us.
So we can get more time to finish the job.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/sleep
west build -p auto -b it8xxx2_evb tests/subsys/portability/cmsis_rtos_v2
fixes#43513fixes#42847
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Rather than defining them in the header, require a set of defines
be provided to cavs_hda.h as part of the expected input to the API.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Adds a header only low level driver for HDA streams along with smoke
tests to ensure basic host in and out stream functionality.
The tests require host side interaction. In cavstool a new HDAStream
class encapsulates somewhat a single stream and its registers. This
is manipulated in the tests using IPC with the Host ensuring that a
specific order of operations is done.
This low level driver allows testing certain hardware configurations
and flows with easy to use register dump debugging. It is not
intended to be the end API an application might use. That would be
a DMA driver using this.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The IPC enum definition and WAIT_FOR macro are useful outside of
the board smoke tests for intel_adsp. They can be commonly used
by other board tests for a variety of peripherals that require
DSP and Host interaction (using cavstool).
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Correct eSPI flash macro so it not always results in zero,
leading to eSPI flash read operation in all cases:
Read, write, erase.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Added support for 8 MB MPU regions for SRAM sizes between 4 and 8 MB,
and 16 MB MPU regions for SRAM sizes between 8 and 16 MB.
Signed-off-by: Johan Öhman <johan.ohman@softube.com>
Customize busy wait timer for micro-seconds accuracy.
Verified by follow test pattern:
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_error_case
west build -p auto -b it8xxx2_evb tests/kernel/timer/timer_monotonic
west build -p auto -b it8xxx2_evb tests/kernel/timer/starve
west build -p auto -b it8xxx2_evb tests/kernel/context
west build -p auto -b it8xxx2_evb tests/drivers/adc/adc_api
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
SMP support might not work if esp_mp.c initialization code
is placed in ROM area. This fix that scenario.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Only cAVS15 is different in terms of definitions, so the ifdef logic can
be simplified quite a bit. Also reorder some of the definitions to
improve readability. No functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Enabled the Shared Memory Reset feature for nRF5340 Application Core
when the RPMsg backend for IPC Service is enabled.
Signed-off-by: Kamil Piszczek <Kamil.Piszczek@nordicsemi.no>
Based on introduction of plain GPIO configurations in STM32 pinctrl
bindings, update STM32 pinctrl/gpio drivers to make this functionality
available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some pinctrl related definitions are still defined
in pinmux related files.
Duplicate definitions to prepare pinmux removal.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
All iMX RT 1xxx boards are now expected to use pin control, so the USDHC
pinmuxing callbacks can be removed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable soc ethernet ref clock output at the SOC level instead of board
level, since it is required for all iMX.RT SOCs
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
