Commit graph

5973 commits

Author SHA1 Message Date
Henrik Brix Andersen
f0fc59f0a2 soc: arm: atmel: same70: enable the UPLL clock
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-05-09 09:27:40 +02:00
Gerard Marull-Paretas
741e838a62 soc: arc: snps_nsim: delete C file with no code
soc_config.c for snps_nsim had no actual code, just a bunch of includes.
Deleting as it has no value (and triggered a compliance warning because
file had no newline at EOF).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Gerard Marull-Paretas
0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Gerard Marull-Paretas
4616056283 soc: riscv: riscv-ite: fix include
<zephyr/zephyr/types.h> is no longer available, <zephyr/types.h> should
be used instead.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:49:17 +09:00
Daniel DeGrasse
58a2b15972 drivers: hwinfo: implemented hardware info support for RT11xx SOC
RT11xx SOC uses same system reset controller as RT10xx series. Add
support for SRC on RT11xx

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-06 11:33:26 +02:00
Peter McShane
635f7ec536 soc: riscv: Add Microchip mpfs soc
Adding soc support for Microchip PolarFire SoC soc

Signed-off-by: Peter McShane <peter.mcshane@microchip.com>
2022-05-06 11:32:54 +02:00
Tim Lin
4cf45f4770 ITE: drivers/pinmux: Remove it8xxx2 pinmux driver
Remove the driver related it8xxx2 pinmux.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-05-06 11:32:40 +02:00
Tim Lin
efaeed6cb2 ITE: drviers/pinctrl: Add pinctrl driver for IT8XXX2
Add pinctrl driver for ITE IT8XXX2.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-05-06 11:32:40 +02:00
Evgeniy Paltsev
38c24cd5aa ARC: boards: nSIM: memory layout overhaul
Currently we use incorrect memory layout for SMP boards as
we put data (which need do be accessible from all cores) to
DCCM which is private for each CPU core.

This works for nSIM which doesn't simulate CCMs (as we don't pass
corresponding nSIM options for SMP configurations) however
it won't work if we run that code on real HW (we want to achieve
that nSIM configurations are also runnable on HAPS - FPGA platform).

Let's fix that issue by using DDR instead of CCMs for SMP
configurations (nsim_hs_smp and nsim_hs6x_smp).

While I'm at it - switch UP HS6x configuration (nsim_hs6x)
for DDR usage instead of CCMs - to make that configuration closer
to the HAPS config we have.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
2022-05-06 11:31:21 +02:00
Ederson de Souza
ddb779e31d soc/xtensa/intel_adsp/tools: Make cavstwist.sh accept ssh port
Sometimes the remote ssh server is not on default port. This patch makes
cavstwist.sh accept an ssh port in the host address: host[:port].

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-05-05 17:00:31 -04:00
Henrik Brix Andersen
0acb154863 soc: riscv: openisa: rv32m1: remove default pinmux configuration
Remove the default pinmux Kconfig configuration from the OpenISA RV32M1
SoC.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Henrik Brix Andersen
2e9d7dd70d soc: riscv: openisa: rv32m1: add pinctrl header file
Add OpenISA RV32M1 pinctrl header file to define SoC specific pinctrl_soc_t
structure. This is used to store pin configurations for the pinctrl driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-05-05 13:34:39 -05:00
Bradley Bolen
dfc4c3f8a6 soc: arm: xilinx_zynqmp: Enable the VFP
This SoC supports vfpv3-d16 with single and double precision and 16
64-bit registers.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2022-05-05 12:03:27 +09:00
Stephanos Ioannidis
2bd4af44f6 Revert "soc: arm: mps3: Only enable MVE if not QEMU"
This reverts commit 91d4b7766c.

Zephyr SDK 0.14.1 now includes QEMU 6.2, which supports the emulation
of the MVE instructions.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-05 11:58:11 +09:00
Tom Burdick
6913da9ddd logging: cAVS HDA based logger
Adds a log backend that maintains a ringbuffer in coordination
with cAVS HDA.

The DMA channel is expected to be given some time after the logger
starts so a seperate step to initialize the dma channel is required.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-05-04 18:56:13 -04:00
Jan Peters
253cec5c95 drivers: counter: add driver for NXP QTMR counters
The driver is implemented using the MCUXpresso SDK.

Signed-off-by: Jan Peters <peters@kt-elektronik.de>
2022-05-03 20:41:23 -05:00
Jay Vasanth
60a41f6878 drivers: ps2: Microchip XEC PS2 add MEC172x support
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-05-03 14:13:20 -05:00
Matthias Fend
124d751c28 soc: arm: nxp_imx: select IPM_IMX_REV2 driver for mimx8mm6_m4
This will automatically enable the IMX IPM (Rev. 2) driver if IPM is
enabled on this platform.

Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
2022-05-02 20:28:57 -05:00
Matthias Fend
30f827341c soc: mimx8mm6_m4: add .resource_table section to linker script
This is required to include the resource table in the build output.

Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
2022-05-02 20:28:57 -05:00
Daniel DeGrasse
d5b719e084 drivers: pinctrl: add pin control driver for NXP RT600/RT500 SOCs
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-02 13:28:10 -05:00
Sylvio Alves
6c6b688b91 driver: spi: esp32: update flash driver to use hal
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-05-02 10:30:24 -05:00
Daniel DeGrasse
19cc2f6ec2 drivers: pinctrl: update pin control driver for lpc54xxx
update pin control driver with bindings and header for lpc54xxx

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-02 09:41:42 -05:00
Daniel DeGrasse
2fbfed9804 soc: imx_rt: added support for nxp imx_usdhc SDHC driver to RT600/500
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
a18338bf45 soc: rt11xx: Enable USDHC SD host controller on RT1170
Enable SD host controller driver for RT1170, so the EVK can use the new
SD subsystem.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
aef290bb4d boards: Enable USDHC driver for all RT10xx based boards
Enable new USDHC driver for all RT10xx boards, since those will have
the SDHC driver selected by Kconfig

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
32cd207f95 boards: mimxrt1064: Enabled new SDHC driver
Enabled new SDHC driver for mimxrt1064 evk

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Michal Sieron
2e9154a418 soc: litex-vexriscv: Rewrite litex_read/write
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.

This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.

There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.

Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.

Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.

Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.

Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.

This makes it possible to have code, independent of CSR data width.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Michal Sieron
f1e0cb6cb3 soc: litex-vexriscv: Implement universal LiteX HAL
Adds LITEX_CSR_DATA_WIDTH option to Kconfig
Depending on its value appropriate read/write handling is used
for accessing CSR registers.
By using `>=` in preprocessor conditions it is somewhat future-proofed.

Doesn't touch `litex_read` and `litex_write` yet.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Nicolas Pitre
ec9c2ec2d8 riscv: pmp: rename CONFIG_PMP_SLOT
The plural form is clearer.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-04-29 15:30:00 +02:00
Nicolas Pitre
2fece49a14 riscv: pmp: switch over to the new implementation
Add the appropriate hooks effectively replacing the old implementation
with the new one.

Also the stackguard wasn't properly enforced especially with the
usermode combination. This is now fixed.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-04-29 15:30:00 +02:00
Daniel Baluta
c3c026e03c arch/xtensa: adsp: Rename module_init section
.module_init sections is used to keep all components constructor
functions.

Zephyr uses -ffunction-sections option which will create a section for
each function. Unfortunately, this creates a section named .module_init
for the function module_init() used to initialize the processing module
generic layer.

Thus, places module_init() in the constructor area named .module_init
which is wrong.

To avoid this we rename .module_init section for constructors to
.initcall.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2022-04-26 15:54:46 -04:00
Yuval Peress
dd82f91ebd soc: xtensa: fix missing rodata section in intel_s1000
The linker script for the intel_s1000 was missing an include for the
snippets-rodata.ld file which is needed for any applications using the
`zephyr_linker_sources(RODATA <linker_script>)` cmake function.

Signed-off-by: Yuval Peress <peress@google.com>
2022-04-26 14:29:18 -04:00
Yuval Peress
ae5945d7be soc: xtensa: fix missing rodata section in intel_adsp
The common linker script for cavs_v?? was missing an include for the
snippets-rodata.ld file which is needed for any applications using the
`zephyr_linker_source(RODATA <linker_script>)` cmake function.

Signed-off-by: Yuval Peress <peress@google.com>
2022-04-26 14:29:18 -04:00
Sylvio Alves
b9ba894584 soc: esp32c3: linker script clean up
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-04-26 14:26:53 -04:00
Sylvio Alves
cb8c2d740b soc: esp32s2: linker script clean up
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-04-26 14:26:53 -04:00
Sylvio Alves
ac9c14d7d7 soc: esp32: linker script clean up
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-04-26 14:26:53 -04:00
Erwan Gouriou
42627d3e25 soc/arm: stm32: All stm32h7 based socs have a cache
In c5b59282d6, Kconfig option
CPU_CORTEX_M_HAS_CACHE was added only to a subset of stm32h7 soc
descriptions.
There is no reason not to extend to all socs as they all actually
feature a cache.

Fixes #45073

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-26 12:06:48 -04:00
Peter Johanson
4ce42a134f soc: rpi_pico: Fix enabling i2c on rpi_pico
Select HAS_I2C_DW for RP2040 SoC, and include the
i2c dt-bindings header.

Signed-off-by: Peter Johanson <peter@peterjohanson.com>
2022-04-26 09:00:25 +02:00
Mahesh Mahadevan
785da27257 soc: nxp: Do not select CODE_DATA_RELOCATION_SRAM
We no longer need to relocate the SDK power management
source file to SRAM. Instead specific functions from the
SDK file are relocated to the ramfunc section.

This commit fixes Issue#44670

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-04-22 13:33:29 -05:00
Dino Li
4cecbf7a85 soc: it8xxx2: enable extensions by configuration options
CONFIG_RISCV_ATOMICS_ISA enables A extension.
CONFIG_RISCV_MUL_ISA enables M extension.
CONFIG_FLOAT_HARD enables F extension. (FPU)

Since we changed to use configuration options to enable extensions,
we no longer need to specify extensions using zephyr_compile_options.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-04-22 10:21:51 -05:00
Daniel DeGrasse
d800c6684c soc: k8x: select HAS_MCUX_CACHE
k8x SOCs have cache controller, so HAS_MCUX_CACHE should be selected.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-22 09:44:19 +02:00
Christopher Friedt
5a23cfd7bd soc: arm: cc13xx_cc26xx: pinctrl: minor fix for typedef typo
Drop `_t` from struct name in typedef.

Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
2022-04-21 14:32:00 +02:00
Immo Birnbaum
a9e935e01b soc: xilinx_zynq7000: fix VBAR, SCTLR contents when coming from u-boot
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:

- clear the ICache/DCache enable, branch prediction enable and
  strict alignment enforcement enable bits in the SCTLR register.
  By default, u-boot will also set up the MMU prior to Zephyr
  doing so as well, this can be avoided by changing the u-boot
  build configuration. Therefore, the MMU enable bit is not changed
  at this point.

- set the VBAR register to 0. U-boot moves the interrupt vector
  table to a non-standard location using the VBAR register (no
  change is made by u-boot for SCTLR.V, only VBAR is changed
  to a non-zero memory location).

Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.

In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-04-21 13:14:50 +02:00
Glauber Maroto Ferreira
a29d62f64d soc: esp32/s2/c3: make PINCTRL config default
through the selection of PINCTRL config
at the SoC level.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira
00bdbb52c5 esp32c3: drivers: pinctrl: initial support
add initial pinctrl driver support for ESP32C3.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira
2b44028777 drivers: pinctrl: esp32s2: initial support
add initial pinctrl driver support for ESP32S2.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Glauber Maroto Ferreira
135f4f772a drivers: pinctrl: esp32: initial support
add initial pinctrl driver support for ESP32.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-04-20 13:27:47 +02:00
Daniel DeGrasse
c6b05afc92 soc: lpc: make pin control definition LPC55xx specific
pin control definitions present for LPC55xx are not generic to all LPC
IOCON controllers. Make pin control header file LPC55xx specific.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-19 15:53:50 -05:00
Tom Burdick
2f320730a1 dma/cavs_hda: Adds link in/link out compatibles
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-04-18 19:19:40 -04:00
Vaishnav Achath
98f1a98cf5 drivers: pinmux: remove cc13xx_cc26xx pinmux driver
all the consumers of the obsolete pinmux driver is
updated to use pinctrl API, this commit removes
the pinmux driver and assosciated sections.

Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
2022-04-18 18:19:46 -04:00