Commit graph

6301 commits

Author SHA1 Message Date
Jun Lin
a55c9f8ce7 driver: kscan: npcx: add driver support for kscan
Add keyboard scan driver support.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-10-03 10:14:51 +02:00
Thad House
f11e5b77f6 rpi_pico: Mark RTT as supported by RP2XXX Chip
RTT is supported by the RP2XXX series of chips, so it should be marked
as such

Signed-off-by: Thad House <thadhouse1@gmail.com>
2022-10-03 10:12:17 +02:00
Peter Marheine
5eb75b81f7 arm: rename default RAM region from 'SRAM' to 'RAM'
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-10-03 10:09:53 +02:00
Grant Ramsay
897952370e drivers: ethernet: Add ESP32 Ethernet driver
This is to enable ESP32 Ethernet support

Signed-off-by: Grant Ramsay <grant.ramsay@hotmail.com>
2022-10-01 14:51:28 -04:00
Adrian Bonislawski
7eeeff5ce9 dma: hda: trigger link commit at dma_start
This will trigger link commit immediately after start
to fix hda start flow.
Applies to link out only.

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2022-09-30 15:18:20 +00:00
Dino Li
db50a7aca7 drivers: gpio: it8xxx2: add support for GPIO_DISCONNECTED flag
This change was made to support the flag.
fixes: #50681

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-09-29 14:33:53 +00:00
Daniel Leung
e869cff96c soc: intel_adsp/ace: unmask all host IPC functionality
On ACE, there is another layer of interrupt masking where
this masks, in addition to the DesignWare controllers.
So we need to un-mask during IPC init or else we are not
going to get any host IPCs.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-29 10:15:53 +00:00
Daniel Leung
4bbd3c7ef5 interrupt_controller: intc_dw_ace_v1x: fix multi-level IRQs
Zephyr encodes multi-level interrupts in a certain way, and
the driver is not utilizing the encoding correctly. So fix
it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-29 10:15:53 +00:00
Stephanos Ioannidis
ed13880f1d linker: Remove k_mem_pool section
This commit removes the `k_mem_pool` section for the memory pool API,
which was removed in the v2.5.0 release.

Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
2022-09-28 14:24:34 +00:00
Anas Nashif
db75a82b24 intel_adsp: when using ztest, add delay between tests
console can't handle the amount of data coming from many tests, so
introduce a delay beween testcases.

Use ZTEST_TEST_DELAY_MS to delay test execution.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-09-26 10:53:43 +00:00
Tim Lin
3474ba919f ITE: drivers/i2c: FIFO2 can be selected to support channel of B or C
FIFO2 can be selected to support channel of B or C by dtsi.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-09-22 14:58:42 +00:00
Daniel Leung
b820cde7a9 soc: esp32: use Z_KERNEL_STACK_BUFFER instead of...
...Z_THREAD_STACK_BUFFER.

This is currently a symbolic change as Z_THREAD_STACK_BUFFER
is simply an alias to Z_KERNEL_STACK_BUFFER without userspace,
and Xtensa does not support userspace at the moment.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-21 18:47:13 +00:00
Daniel Leung
74df88d8f5 soc: intel_adsp: use Z_KERNEL_STACK_BUFFER instead of...
...Z_THREAD_STACK_BUFFER.

This is currently a symbolic change as Z_THREAD_STACK_BUFFER
is simply an alias to Z_KERNEL_STACK_BUFFER without userspace,
and Xtensa does not support userspace at the moment.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-21 18:47:13 +00:00
Jay Vasanth
64eeef9d57 soc: arm: microchip: update mec1501 soc header
update mec1501 soc.h to include soc_dt.h for pinctrl
related macros

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-09-21 18:05:32 +00:00
Andrey Borisovich
892682dac6 soc: intel_adsp_ace1x: fix for IPC implementation
In commit c75e6cfcb9
("soc: intel_adsp_ace1x: Added IPC/IDC implementation")
definition for INTEL_ADSP_IPC_DONE was modified for ace1x platforms.
This change was not correct as the new definition was also used to
program the IDA register.

Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-21 14:08:38 +00:00
Emilio Benavente
2f149fb653 soc: arm: nxp: lpc55xxx: Added FlexPWM to the SOC Kconfig
Added MCUX_PWM Kconfig dependency;
Added missing pin function definition needed for PWM;
Enabled submodule clocks for FlexPWM

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2022-09-19 10:10:32 +00:00
Mahesh Mahadevan
46eaa81ac0 dts: rt1010: Fix RT1010 IP base addresses
Fix the Base addresses for the IP blocks that are
located at a different address on RT1010

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-16 14:50:06 -05:00
Enjia Mai
ef3e7a5fa6 soc: xtensa: cavstool: add support for logs coming from HDA logging
1) HDA logging seems to be using some padding like '\x00'. Such
string can print well on a terminal but corrupt the string match.
And this can cause false failure if RunID matching is affected.
Remove such padding before checking RunID.

An affected RunID example:
'7aa9ba3c6db12\x00\...\x00\x00\x00\x00d0c7fcf382a4af40ec6'

Expected:
'7aa9ba3c6db12d0c7fcf382a4af40ec6'

2) Use non-displayable chars for live connection check. Otherwise
the log output will have subtle garbage like extra spaces which
locate randomly.

This solution comes from the PR #50071, the author is smrtos.

Signed-off-by: Ming Shao <ming.shao@intel.com>
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-16 13:34:05 -04:00
Enjia Mai
d6cb27ddd8 soc: xtensa: remove the serivce logic in the FW loader
Remove the remote service logic in the FW loader, now
the FW loader is a pure FW loader as it used to be.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-16 13:34:05 -04:00
Enjia Mai
8b97e7b29f soc: xtensa: split the cavs server and the FW loader
Spilt the cavs server and FW loader, to make the cavstool.py
a pure FW loader and runner as it used to be. The reasons is
try to keep the FW loader won't be affected by the client-
server-based HW service as possible, and more easy to debug.

After splitting them, the service program spawns another
process to run the FW loader. The advantage is no matter when
the FW loader is stuck, the service can detect and stop it,
then continue to next test.

Fixes #47652.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-16 13:34:05 -04:00
Enjia Mai
581fc89084 soc: xtensa: tool: duplicate the cavstool.py to remote-fw-service.py
Copy cavstool.py to remote-fw-service.py in order to track changes
for following splitting work of cavstool.py.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-16 13:34:05 -04:00
BJ Chen
e1a2504ac3 soc: riscv: ite: removed redundant definitions
Removed redundant definitions of TRUE/FALSE

Signed-off-by: BJ Chen <bj.chen@ite.com.tw>
2022-09-14 08:31:21 -05:00
Lauren Murphy
85445474f2 boards, dts: fix filenames and dts refs for adsp clock
Changes filenames and DTS references from CAVS clock to
ADSP clock.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Lauren Murphy
1983a4c50c boards, dts: fix namespace for intel adsp cavs, ace
Fixes namespace for Intel ADSP CAVS and ACE boards.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Flavio Ceolin
b10c526352 ace: power: Only define d0i3 stack when needed
If the target is built without CONFIG_PM this stack is not
used and does not need to be defined.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-13 08:45:34 -04:00
Kai Vehmanen
1a6d868400 soc: xtensa: tools: do not interfere with IPC in logs-only mode
The tool has caused some hard to detect failures when used
concurrently with the SOF Linux driver to observe logs. This
has been rootcaused to the code to handle and send IPC messages
that has been active even in logs-only mode. In vast majority
of cases, the SOF kernel driver is faster to act and handles
the IPC interrupts. But occasionally the cavstool.py timing was
just right and it managed to ack a message before Linux driver.

Fix the problem by not handling IPC messages when the tool
is run in logs-only mode.

Reported-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-09-13 08:41:32 -04:00
Daniel Leung
164a1aa95e soc: arm/nxp/imx/rt6xx: add bits to support I3C controller
This adds a few bits to the RT6xx SoC code to support the I3C
bus interface on RT600 series.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-09-09 17:42:33 -04:00
Flavio Ceolin
d80be13791 intel_adsp: Use vectors offset defined in the hal
Do not hardcode vectors offset, instead get this values from the HAL.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
bfdd5a7517 intel_adsp: ace: Remove un-existent vectors
Interrupt vectors level 5 and 6 are not available in ACE. Just remove
them from the linker script.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
d103eee642 intel_adsp: ace: Fix debug vector address
In ace15_mtpm the debug exception vector address is mapped to INTLEVEL4
and not INTLEVEL 6. This can be checked in the core-isa header:

"""
define XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL4_VECTOR_VADDR
"""

in
modules/hal/xtensa/zephyr/soc/intel_ace15_mtpm/xtensa/config/core-isa.h

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
f37e7cdd3d intel_adsp: Do not use hal namespace
Do not define symbols using xtensa hal namespace.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
b5a0567984 intel_adsp: Rename common file
Symbols defined in cavs-vectors.h is also used by ace, just rename it
to avoid confusion.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Andriy Gelman
538477f8b8 soc: arm: infineon: 4xxx: Fix UART comms during sleep
In normal operation the clock for peripheral devices is derived from
the PLL clock.
During sleep, the xmc4xxx can switch its system clock source (f_sys)
from the PLL clock to an f_ofi clock. Switching to the f_ofi clock
is the default behaviour which breaks UART comms.

Use the PLL clock source during sleep instead to fix the issue.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-09 16:30:36 -04:00
Andriy Gelman
5feae0eafc drivers: pinctrl: Add pinctrl driver for xmc4xxx
Add pinctrl driver for infineon xmc4xxx devices.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-09-09 16:28:41 -04:00
Flavio Ceolin
45465708f0 soc: intel_adsp: Add ACE soc series
ACE15_MTPM is one SOC from the ACE series. Organize
it following cavs pattern.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:03:59 -04:00
Mahesh Mahadevan
7f86411ed1 soc: mxrt: Add a compile time define for USB driver
Define DATA_SECTION_IS_CACHEABLE=1, this is used by
the SDK USB driver

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Mahesh Mahadevan
9619b02f9b soc: nxp: Add define needed by the SDK USB driver
1. Add USB_STACK_USE_DEDICATED_RAM=1 define that is
   used by the SDK USB driver
2. Delete unused "config USB_DEDICATED_MEMORY"

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Mahesh Mahadevan
9966181510 drivers: usb: mcux: Restructure driver for SDK updates
1. Move the defines from usb_dc_mcux.h to usb_device_config.h
   and fsl_os_abstraction.h. These headers are used by
   the SDK USB driver. usb_dc_mcux.h header file is not longer
   needed and hence deleted.
2. Delete the Zephyr implementation of the usb_device_struct
   driver and use the one implemented inside the SDK USB
   driver. This requires updating the references to
   usb_device_struct inside the USB driver
3. Move defines and structures used by the driver
   out of the header file that is included by the SDK and
   into the MCUX USB driver.
4. Use end point defines provided by Zephyr instead of adding
   them locally.
5. Add a Kconfig to set the thread stack size
6. Move code to enable interrupts back to usb_attach function.
   Interrupts should be enabled after the init is successful,
   else we see errors of the ISR getting called before the
   init is complete causing Faults
6. Update west.yml to update the NXP HAL to get the updated
   SDK USB driver.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Kumar Gala
318c12d17c timer: remove Kconfig.defconfig* setting of timer drivers
Now that timer drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-09-09 09:58:48 +00:00
Ederson de Souza
cf6bad78c4 soc/xtensa/intel_adsp: Disable L2 cache at boot based on Kconfig
Instead of deciding based on SoC version, add information to Kconfig and
get it from there on code.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
fcdc9c78e2 soc/xtensa/intel_adsp: Get register address from DTS
Instead of hardcoding it where it's used.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
5f4e2f99f0 soc/xtensa/intel_adsp/cavs: Init HP SRAM based on Kconfig
Instead of deciding to init based on SoC version, define that
information in Kconfig and use it from there.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
9b7375d82a soc/xtensa/intel_adsp/common: Power on cache SRAM banks based on Kconfig
Instead of using SoC version to decide to power on or not, add this
information to Kconfig and get it from there.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
c1dc2683b9 drivers/dai/intel/ssp: Get number of SSP ports from Kconfig
Instead of using SoC versions, define the information about base and
extended ports on Kconfig, and use this information from there.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
79980f250c drivers/dai/intel/ssp: Decide about clock gating based on Kconfig
Instead of using version of the SoC, declare on Kconfig the need for it,
and use this information to decide upon enabling the code or not.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Flavio Ceolin
9f13c1bf95 intel_adsp: ace: Fix wrong type assignment
error: assignment to 'void *' from 'unsigned int' makes pointer from int
|         lpsheader->lp_restore_vector = (uint32_t) &dsp_restore_vector;

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-08 17:54:35 -04:00
Flavio Ceolin
2851815c22 intel_adsp: ace: Add missing header on power.c
MEMCTL_L0IBUF_EN is defined in corebits.h

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-08 17:54:35 -04:00
Mateusz Sierszulski
9beb6ab2d6 soc: riscv: telink_b91: Place .init before .vectors section
This commit fixes placing .init sections before .vectors
sections in telink_b91 SoC.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2022-09-08 10:39:31 +02:00
Mateusz Sierszulski
acc39878ff soc: riscv: ae350: Remove redundant .vectors sections
This commit removes doubled .vectors sections in ae350 SoC.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2022-09-08 10:39:31 +02:00
Nikolay Agishev
a56777263e compiler: gcc: add support for tuning mcpu option for ARC targets
ARC processors are highly configurable, so ARC toolchain supports
big amount of mcpu options for all that HW configurations.
As difference in many configurations among the same processor
family usually doesn't affect Zephyr code we don't want
to create Kconfig option for each possible CPU configuration
(just to map Kconfig option to correspondent mcpu value
in 'cmake/gcc-m-cpu.cmake').
Instead we prefer being able to set proper mcpu value
individually for any ARC SoC and using 'cmake/gcc-m-cpu.cmake'
just for reasonable defaults.

To apply SoC-related changes for build-options on early stages of building
'tune_build_ops.cmake' should be created in appropriate SoC directory.
Example:
 ./soc/arc/snps_qemu/tune_build_ops.cmake
File content:
 set(GCC_ARC_TUNED_CPU hs4xd)

Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
2022-09-08 10:39:21 +02:00