Commit graph

5973 commits

Author SHA1 Message Date
Tomasz Leman
8940b9cae5 soc: ace_v1x: pm_state_set implementation
This patch implements pm_state_set function for ACE platforms.

This is initial implementation and only includes the basic handling of
PM_STATE_SOFT_OFF.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Tomasz Leman
cc9f82de44 soc: ace_v1x: soc_adsp_halt_cpu implementation
This patch add soc_adsp_halt_cpu implementation for ace. Function disable
power and check CPA status to report success. Function should be used only
for secondary cores and can be executed only from primary core.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Rafal Redzimski
b49d794966 ace: multiprocessing: add polling for core powered up confirmation
Poll for CPA bit by which HW confirms that the core has been powered up.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Rafal Redzimski
090b01e73c ace: multiprocessing: enable secondary core boot through ROM
Add ace/mtl rom flags definitions.
Set the flags in battr to indicate to rom that it should execute
secondary core procedure.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
b330a05539 intel_adsp: add a new series to support Meteorlake
Meteorlake support as part of the Intel ADSP family.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
782b083686 soc: add mising braces to single line if statements
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 11:00:45 -04:00
Alexandre Duchesne
1561b1046f soc: arm: gigadevice: Initial support for gd32f470
add initial support for gd32f470 SoC

Signed-off-by: Alexandre Duchesne <alexandre.duchesne@rtone.fr>
2022-07-06 13:22:25 +02:00
Ruibin Chang
dc3f29f67f ITE tests/kernel/sleep: tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down
We need more time to run codes because of the performance,
so I tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down to reduce
the times of running k_usleep(1), then it can pass test_usleep().

Verified by follow test pattern:
west build -p always -b it8xxx2_evb tests/kernel/sleep

fixes #46208

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-07-05 11:29:43 +00:00
Christian Taedcke
e71c2d1893 boards: efm32pg_stk3402a: Add minimal pwm support
With this additions samples/basic/blinky_pwm works.
LED0 is used as pwm output.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2022-07-04 15:51:11 +02:00
Alex Sergeev
f7f35af277 soc: gd32: Add HAS_SEGGER_RTT
Enable SEGGER RTT for GigaDevice family.

Signed-off-by: Alex Sergeev <asergeev@carbonrobotics.com>
2022-07-04 09:50:35 +02:00
Enjia Mai
a1e388ea2e soc: xtensa: keep the CAVS old flasher still works
Keep the cavstwist.sh it is still working by specifying an
environment variable when CAVS_OLD_FLASHER is set. Provide
a fallback once the client-server-based tool does not work
well in some conditions.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-02 06:06:19 -04:00
Kumar Gala
287acdbb9d i2c: sam0: Set driver Kconfig default based on devicetree
Change Kconfig default to be based on if the devicetree has the
atmel,i2c-sam0 driver enabled.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-01 15:05:55 -05:00
Kumar Gala
d200321767 video: mcux_csi: Set driver Kconfig default based on devicetree
Change Kconfig default to be based on if the devicetree has the
nxp,imx-csi driver enabled.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-01 14:56:33 -05:00
Daniel Leung
1277c38797 cavs: disable timer interrupt on cpu power off
Since the timer interrupt is delivered to all cores at the same
time, it needs to be disabled (or masked) to prevent it from
waking a suspended CPU core.

Note that there is no need to re-enable (unmask) timer
interrupt separately as it is being taken care of in
smp_timer_init() when the CPU re-inits itself.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-07-01 14:04:50 -04:00
Guennadi Liakhovetski
3748bdcad6 xtensa: return to idle() when booting sporadically
To power down secondary cores on cAVS 2.5 platforms the primary core
enables the power-saving mode for the respective secondary core and
waits until that core enters idle() and executes the waiti
instruction at which point the core should enter a lower-power mode.
However, that core can then also automatically wake up and execute
its reset path if, e.g. an interrupt is delivered to it. However, it
isn't entirely clear which events are able to wake up cores from that
state. Disabling interrupts on the interrupt controller didn't seem
to prevent that from happening completely. In particular a specific
ADL notebook seems to be susceptible to this problem. Checking for
such sporadic boots and returning to idle fixes the problem.

BugLink: https://github.com/zephyrproject-rtos/zephyr/issues/46372
BugLink: https://github.com/thesofproject/sof/issues/5733
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2022-07-01 14:04:50 -04:00
Bartosz Bilas
33a4c78699 soc: select HAS_MCUX_XBARA for MIMXRT1062
Select HAS_MCUX_XBARA Kconfig symbol for MIMXRT1062,
since the XBARA Inter-Peripheral Crossbar Switch peripheral is present
on this SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-07-01 16:23:11 +00:00
Glauber Maroto Ferreira
fb919a75ba soc: esp32/s2/c3: pinctrl: update pin init macros
Updates pin initialization macros to make use
of pin grouping.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-01 16:22:18 +00:00
Jay Vasanth
e74978cc03 microchip: mec: zephyr spi image generation
Added mchp mec zephyr image generator python script. It takes
zephyr.bin as input and produces zephyr.mchp.bin.
The default behavior is to not pad to SPI flash size.
(Enable through CONFIG_MCHP_MEC_UNSIGNED_HEADER=y and
CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y)

zephyr.mchp.bin is composed of:
1. First 4KB contains TAG at offset 0 and header at offset 0x100
2. Offset 0x1000 is the start of zephyr.bin which has been padded
to a multiple of 128 bytes.
3. Boot-ROM EC Info Block (128 bytes)
4. Boot-ROM Co-Signature Block (96 bytes)
5. Boot-ROM trailer (160 bytes) contains the SHA-384 digest of 2-4.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-07-01 11:35:13 +02:00
Bartosz Bilas
091a54202a soc: arm: nxp_imx: rt: add new MIMXRT1062CVJ5B part number
Add missing MIMXRT1062CVJ5B SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-30 19:50:03 +00:00
Bartosz Bilas
dcf2d4d542 soc: arm: nxp_imx: rt: add new MIMXRT1062CVJ5A part number
Add missing MIMXRT1062CVJ5A SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-30 19:50:03 +00:00
Alexandre Duchesne
7109e7dc20 soc: st_stm32f7: Add stm32f750xx SoC
add initial support for STM32F750xx SoC

Signed-off-by: Alexandre Duchesne <alexandre.duchesne@rtone.fr>
2022-06-30 13:41:06 +00:00
Ederson de Souza
afed5e4010 soc/xtensa/intel_adsp/tools: Dial back stream reset sleep
A full second is too much, and since "Ack local interrupt before
processing IPC" patch, it doesn't seem necessary. This whole second
wait would break tests that log too much content, as the firmware
is already running during the reset - and the host script wouldn't read
the contents, thus some of the logs would be overwritten.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-30 06:13:30 -04:00
Jaroslaw Stelter
8632986746 soc: intel_adsp: Add lib_code module type.
External libraries can contain processing module code or common library
code. Library manager need to distinguish between both type of modules
for proper loading.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
2022-06-29 10:41:59 -04:00
Dmytro Firsov
f4cea5da70 xenvm: drivers: xen: add Xen grant table driver
This commit introduces driver for granting access for own grant
table and for mapping/unmapping foreign gref. Grant tables are used
for data exchange between Xen domains via shared memory page(s) (e.g.
for sharing ring buffer with driver data) This functionality is
widely used and needed for implementing PV backend/frontend drivers.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2022-06-28 22:34:26 -04:00
Daniel DeGrasse
69d153cd3d soc: nxp_imx: rt: enable SWO output for iMX RT 10xx series
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-06-28 16:02:09 -05:00
Ederson de Souza
7ab8607e71 soc/xtensa/intel_adsp/tools: Ack local interrupt before processing IPC
It seems a race can happen between the host acknowledging a DONE
interrupt and the DSP being able to mark some IPC as done. To avoid
this, the host script now always acknowledges the DONE interrupt
_before_ processing the IPC message.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-28 14:56:57 -04:00
Henrik Brix Andersen
9d51d9145b soc: arm: xilinx: zynq7000: default to 1 CPU core
Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
Henrik Brix Andersen
e8df5bdf5b soc: arm: xilinx: zynq7000: add pinctrl header file
Add Xilinx Zynq-70000 pinctrl header file to define SoC specific
pinctrl_soc_t structure. This is used to store pin configurations for the
pinctrl driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
Henrik Brix Andersen
982d379808 soc: arm: xilinx: zynq7000: unlock the slcr at boot
Unlock the Xilinx Zynq-7000 System Level Control Registers (SLCR) at boot
to allow write access using the generic syscon driver.

Since the generic syscon driver uses the DEVICE_MMIO_* APIs for
memory-mapped IO we can remove the dedicated SLCR MMU region.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
Jeremy Bettis
6ede43b078 npcx: Set hex_file automatically w/ npcx hex image
When using CONFIG_NPCX_IMAGE_OUTPUT_HEX, set the hex_file
runners_yaml_props_target property, so that west flash will flash the
correct file.

Change the cmake flash rules to populate the hex_file value in the
runners.yaml file if either CONFIG_BUILD_OUTPUT_HEX is enabled or some
cmake file set the runners_yaml_props_target hex_file property.

Update the npcx9m6f_evb instructions now that the filename is implicit.

Signed-off-by: Jeremy Bettis <jbettis@google.com>
2022-06-28 11:09:35 +02:00
Ederson de Souza
4fd8d474ec soc/xtensa/intel_adsp/tools: Do not use grep Perl extensions
They may be disabled in some environments (such as Gentoo based
developer mode on Chromebooks). Use extended regular expressions
instead.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-27 15:41:00 -05:00
Ederson de Souza
0ce9446978 soc/xtensa/intel_adsp: Add cAVS clock driver
Simple driver that allows one to choose the clock speed of xtensa cores.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-27 12:42:04 +02:00
Alex Kolosov
4a52bc22b6 soc: riscv: telink_b91: add dfu related configurations for b91 platform
Modify Telink b91 config files and linker script with necessary config
settings required for DFU.

Signed-off-by: Alex Kolosov <rikorsev@gmail.com>
2022-06-24 20:25:33 +02:00
Bartosz Bilas
63e9fb6190 soc: select HAS_MCUX_SRC for MIMXRT1062
Select missing HAS_MCUX_SRC Kconfig symbol for MIMXRT1062,
that allows using NXP i.MX mcux SRC hwinfo driver.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-24 12:30:11 -05:00
Lauren Murphy
318e6db239 debug: coredump: add xtensa intel adsp, support toolchains
Adds compatibility with Intel ADSP GDB from Zephyr SDK and
from Cadence toolchain to coredump_gdbserver.py.

Adds CAVS 15-25 (APL) register definitions. Implements
handle_register_single_read_packet to serve ADSP GDB
p packets.

Prevents BSA from changing between stack dump printout
and coredump by taking lock. Observed to be necessary for
accurate results on slower simulated platforms.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-06-23 15:44:45 -04:00
Keith Packard
01187b92a2 soc/it8xxx2: Place arithmetic funcs in .text section
Placing these in the __ram_code section generates a relocation error when
building with toolchain version 0.14.1, moving them back to .text fixes
that (presumably with a performance penalty).

Signed-off-by: Keith Packard <keithp@keithp.com>
2022-06-22 13:15:55 +02:00
Sylvio Alves
54ca96f523 soc: esp32: opt to make device handles in dram
ESP32 linker loader needs all sections to be align correctly.
When MCUBoot is enabled, device handles provide by device-handles.ld
does not make the ALIGN(4) at the end, which breaks the loader
initialization. This PR make sure that this particular section
is placed in DRAM instead.

For now this is a workaround until this can be handled in loader script.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-06-22 12:27:43 +02:00
Sylvio Alves
8e04acab3b linker: esp32: fix flash linking reference
Referenced spi_flash_rom_patch.c object was wrongly
linked, which can cause crash due to flash cache disabled
operation.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-06-22 12:27:32 +02:00
Anas Nashif
bc38f25178 intel_adsp: fix typo PLATFORM_INIT_LPRSRAM -> PLATFORM_INIT_LPSRAM
Fix typo in define preventing initialization of LPSRAM.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-22 12:16:41 +02:00
Carlo Caione
741b9dc65d riscv: Rename __irq_wrapper to _isr_wrapper
For some reasons RISCV is the only arch where the vector table entry is
called __irq_wrapper instead of _isr_wrapper. This is not only a
cosmetic change but Zephyr expects the common ISR handler to be called
_isr_wrapper (for example when generating the IRQ vector table).

Change it.

find ./ -type f -exec sed -i 's/__irq_wrapper/_isr_wrapper/g' {} \;

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-21 20:27:20 -04:00
Rafal Redzimski
bd46470167 xtensa: intel_adsp: add rom jump address definition
Add the definition of address which is used by ROM to jump to FW.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-21 14:01:01 -04:00
Anas Nashif
09cd218cde intel_adsp: use arch_proc_id() instead of local function
Use arch_proc_id interface instead of locally defined function.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-06-21 10:48:28 +02:00
Yinfang Wang
4278d69924 test: Enable the GPIO tests on EHL_CRB.
Enable testcases under tests/drivers/gpio/gpio_basic_api
To run in twister, "-X gpio_loopback" parameter is needed.

Signed-off-by: Yinfang Wang <yinfang.wang@intel.com>
2022-06-21 10:47:56 +02:00
Stephanos Ioannidis
c40949a389 soc: esp32s2: Drop IRAM_ATTR from forward declarations
This commit drops the `IRAM_ATTR` macro from the function declarations
because:

1. `IRAM_ATTR` macro makes use of the `__COUNTER__` preprocessor macro,
which increments for every macro invocation and causes the section
specified in the forward declaration to not match that of the
function definition.

2. Section attributes need not be specified for forward declarations.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-06-20 10:28:06 +02:00
Aurelien Jarno
e54224ddab soc: stm32: h7: Generate MPU regions from DT nodes
Commit b91d21d32c added the possibility to define MPU regions from the
device tree, however commit c276088567 removed that possibility for H7
SoC, as it now uses a SoC specific definition of the MPU regions without
the DT-defined regions (probably because the two PRs got developped in
parallel).

Fix that by adding the macro which adds the DT-defined regions to the
STM32H7 specific file.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2022-06-20 10:27:52 +02:00
Dino Li
e1c5222afd soc: it8xxx2: add soc variants
Currently there are two soc variants (IT81202BX and IT81302BX) on
it8xxx2 series. The IT81202BX is 128-pin package (GPIO K and L groups
aren't bonding with pad).
This makes soc variant configurable and apply corresponding configuration
for a soc.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2022-06-20 10:25:08 +02:00
Krzysztof Chruscinski
c5f2cdef09 logging: Remove logging v1 from the logging
Remove v1 implementation from log_core and all references in the tree.
Remove modules used by v1: log_list and log_msg.
Remove Kconfig v1 specific options.
Remove Kconfig flags used for distinction between v1 and v2.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-06-16 10:51:15 -04:00
Gerard Marull-Paretas
416dd6cd36 soc: arch: snps_arc_iot: select UART_NS16550_ACCESS_IOPORT
NS16550 driver no longer relies on definitions found in <soc.h>, SoC can
select UART_NS16550_ACCESS_IOPORT instead.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-16 11:28:13 +02:00
Gerard Marull-Paretas
e928300f90 soc: remove unused UART_DEFAULT_REG_INTERVAL definitions
Information is now provided in Devicetree by each ns16550 instance.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 16:59:02 -05:00
Gerard Marull-Paretas
5a565ece45 soc: riscv-ite: remove redundant <zephyr/zephyr.h> includes
Files including <zephyr/kernel.h> do not have to include
<zephyr/zephyr.h>, a shim to <zephyr/kernel.h>.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-06-15 09:13:11 +02:00