The Xtensa arch has historically had state/user register accessor
macros with bare three-byte symbol names. I think this might have
been in the original Cadence-contributed arch integration, but I'm not
sure. In any case they also exist in the same names in vendor
HAL/toolchain code and are causing collisions. We never should have
had these symbols exposed in our header.
Put them under an XTENSA_ prefix to decollide.
Signed-off-by: Andy Ross <andyross@google.com>
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).
Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
According to RM, there are 2 pins that need a 3 bit mask for daisy chain,
changed it accordingly.
(E.g. IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT for imx6sx)
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Fix NXP MPU configuration for k6x flash region. The previous flash MPU
setting was based around the assumption that the user was executing from
the flash region at 0x0000_0000–0x07FF_FFFF, which may not be case if the
user selects to execute from SRAM, such as running from sram_l
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove description from SOC_FAMILY_SMARTBOND so it's not directly
selectable. Also fix related board configuration.
Fixes#49916
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Place vector sections after ROM_START sections.
Also add init.ld script that will prevent overlapping .init sections
in telink_b91 SoC.
Fixes#49036.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.
Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
- "cavs_host_ipc" node labels to "adsp_ipc" labels.
- compatible "intel,cavs-host-ipc" renamed to
"intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
- "idc" node labels to "adsp_idc" labels.
- compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
so it is suitable for both CAVS and ACE SoC family.
Moved it from ipm bindings to ipc bindings where it belongs.
Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
status of the "adsp-ipc" and "adsp-ipc" node.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
This patch adds core restore vector. FW will restore core context from
memory and then return to the state it was in before power gaiting.
Adding struct of LPSRAM header. ROM during reboot check this struct in
serching for magic value and restore vector address.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch adds initial implementation of dynamic power gating for ace
platforms. The code is limited to enabling PG in HW registers and
disabling all interrupts.
CPU context storing and restoring still needs to be implemented. PG at
this moment will cause FW to halt during reboot.
Patch contains small refractor. Value CORE_POWER_CHECK_DELAY has been
moved to common header so it can be reused in other places.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is renaming primary core power down procedure by removing ACE
prefix. Prefix was added to avoid name conflicts while linking. The
problem is now resolved and name can be revert to the original version.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Similarly to other drivers, use auto generated DT_HAS_<COMPAT> Kconfig
symbol to control use of STM32 lptim driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added code to enable platform specific Virtual Wire GPIOs. With this
change, able to send the USB-C overcurrent Virtual Wire event to
Meterolake SOC.
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Update all esp32 socs to include esp_timer early init, which
is part of hal v4.4.1 update.
Update reboot function to meet proper SoC init/deinit peripherals.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
According to RM the daisy chain mask should include both bit 0 and 1, not
only bit 0.
Updated bitmask accordingly
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The STM32G070 and STM32G0B0 Socs don't have USB power delivery support
but the PINs PD0, PD2, PB15, PA8 pins of these still have the same
pull down on boot configuration options as the SOCs with UCPD support.
This commit skips the check if such a peripheral is enabled,
therefore the configuration will always be applied on these SOCs
and the compile error is resolved.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
On STM32U5 series, when an image is build with mcuboot,
image starts at offset 0x400 instead of default 0x200.
This should be taken into account when calling imgtool by using
dedicated option to set header-size value.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that clock control drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that interrupt controller drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This allows to disable UART peripheral driver and still be able to build
correctly (header is not visible when LPUART driver is not enabled).
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
So far systick frequency was duplicated in 'sysclk' DT nodelabel's
'clock-frequency' property and in per SoC SYS_CLOCK_HW_CYCLES_PER_SEC
default value. Set the latter based on DT configuration.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This adds initial support for Renesas SmartBond(tm) DA1469x series SoC.
Initailly only DA14699 is explicitly supported, however this code should
also run on other SoCs in this series since all of them support the same
core features available initially.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This has been moved to the NXP HAL layer so that all
SDK NonCacheable symbols get placed in the nocache
region
Also pull in the HAL changes associated with this
change.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit replaces API that became deprecated with the release
of nrfx2.9 - see CHANGELOG in zephyrproject-rtos:hal_nordic repository
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Now that crypto drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Consolidate common kconfigs of the CAVS series into the series level and
remove duplication among all supported SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit updates the custom target architecture type specified for
the `SOC_OPENISA_RV32M1_RI5CY` and `SOC_OPENISA_RV32M1_ZERO_RISCY` SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.
Note that the hack overriding the build system-default `-march` flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
