Add support of sys_poweroff API on m46x series.
It could support SPD standby or DPD deep power down mode.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Remove the ‘HAS_MCUX_ACMP’ Kconfig, and also remove it from
driver and soc Kconfig files. It is not needed since we already
depend on 'ACMP' enabled in the dt file, the 'HAS_MCUX_ACMP'
kconfig is a relic of the past before devicetree was stable.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
When not using BT, users may want to enable the cpunet core. Until now,
this has been done at board level (so duplicating unnecessary code)
using CONFIG_BOARD_ENABLE_CPUNET. The board-level options were usually
enabled automatically for BT, however, this was unnecessary as BT driver
already takes care of the setup.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Convert pin control, GPIO and external interrupt controller drivers
based on SIUL2 peripheral to native drivers. This must be done in a
single commit to preserve atomicity, as these drivers depend on each
other.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The total number of IRQs for this chip is 110.
Refer to the reference manual table 46 for IRQs.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
Place zephyr library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libzephyr.a: +16974 bytes -608ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place kernel library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libkernel.a: +8941 bytes -649ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Place serial library in ILM. This can improve performance.
test:
Print the message 10000 times with 1ms sleep interval to compare the
time difference before and after adding RAM code on the it82002bw evb.
RAM code size save time
original: 1954 bytes
libdrivers__serial.a: +2282 bytes -226ms
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Initialize TCM and SRAM contents only after a destructive reset (e.g.
PoR reset). SRAM retains content during functional reset through a
hardware mechanism, therefore accesses do not cause content
corruption errors.
Fixes#75912
Signed-off-by: Manuel Argüelles <marguelles.dev@gmail.com>
In S32K1 devices, Arm Systick clock frequency is equal to the
CPU core clock frequency, and its value can be obtained from
devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Currently the code suggests, that setting the SRAM disabling mask to
0 skips powering off SRAM, whereas in fact it's the address of the
mask variable that's checked for NULL. Make this consistent and let
platforms select whether SRAM power down should be selected.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
The IMR is used by the firmware to hold its own copy for hot-booting
and for an "L3 heap," used for slow large allocations like loadable
libraries. The beginning of the L3 heap is currently hard-coded and
now the firmware has grown too large to fit into the dedicated area
so that it gets overwritten by heap allocations. This is a critical
bug that needs an urgent solution, for which we increase the offset,
but a real fix must calculate the L3 heap offset automatically.
BugLink: https://github.com/thesofproject/sof/issues/9308
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
After recent nsim SoCs & boards reorganization the SOC_SERIES_*
config is missing for vpx5 SoC which leads to cmake errors
when building against nsim/nsim_vpx5 configuration.
Fix that and align soc series name in soc.yml
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
The source files required for this features are not present
in the tree for this SOC.
So if CONFIG_PM or CONFIG_POWEROFF are enabled, there would
be a cmake failure.
Let's just indicate these features are not supported in
kconfig.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
CLIC should be the first level interrupt controller because it replaces
the basic RISC-V local interrupt.
The interrupt level in CLIC controls preemption between IRQs, rather than
specifying the number of nested interrupt controllers.
Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
A recent commit fb53d2ef8d ("ace: power: replace pseudo-assembly
movi") contained a bug: the Xtensa "movi" assembly instruction must
be written with the immediate argument already shifted left by 8, the
compiler doesn't do that automatically. This still somehow worked on
MTL but failed on LNL. Fix both occurrences.
Fixes: #75700
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
SARADC was kept enabled to feed RNG entropy peripheral,
adding instability to Wi-Fi connection. So we disable it
before app runs as RNG driver already got initial entropy values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Getting the required alignment size for memory region node
and device node needs to be handled by a separate macro.
Otherwise alignment of single byte is reported for any region.
Add a test that checks for this particular issue.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The series-specific Kconfig files were not included, leading
to RTT not being considered available.
Fixes#75511.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
risc-v idle call is being fetched from arch/ implementation.
This soc file is not used and can be removed.
Fixes#75540
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Added a flash runner configuration for rw, mcx, lpc, kinetis and imxrt,
used for sysbuild multi-image projects like MCUBoot.
- Solved the mass erase issue.
- The sysbuild project "west flash --erase" command caused
the mass_erase->flash_img1->reset->mass_erase->
flash_img2->reset sequence.
It was fixed to the mass_erase->flash_img1->
flash_img2->reset sequence.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
This removes the prompts for the mt8195 and related kconfigs,
so these cannot be overridden from command line (though
technically they cannot be disabled as they are being selected).
This also prevents them from appearing in the build .config
file as not being set even when we are being for other SoCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit fixes a bug with the declaration of the Kconfig option
MEMC_STM32.
The option is defined in two files:
- `drivers/memc/Kconfig.stm32`, wich depends on
- `MEMC`
- `DT_HAS_ST_STM32_FMC_ENABLED`
-`soc/st/stm32/Kconfig.defconfig`, wich depends on
- `MEMC`
- `SOC_FAMILY_STM32`
So, if you have `CONFIG_MEMC=y` in your Kconfig options and you are on a
STM32 SoC, `CONFIG_MEMC_STM32` will be enabled, even if there is no
STM32 FMC enabled.
This Kconfig option causes the driver for the STM32 FMC to be compiled,
regardless of the presence of an enabled node for the FMC.
However, the driver fails to compile if there is no FMC node in the
devicetree. So, if you compile a project with `CONFIG_MEMC=y` on a board
with an STM32 SoC and no enabled FMC, the build will fail.
This commit deletes the Kconfig declaration in the `Kconfig.defconfig`,
as it isn't useful and is the one provoking the bug.
It also add in the `Kconfig.stm32` the compatible `st,stm32h7-fmc`, wich
use the same driver and so need to be enabled by the same Kconfig
option.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Currently the code in soc.c depends on the MMU of the CPU being enabled,
but this is not enforced. It is thus possible to cause a build error by
manually disabling it (as is required for some LLEXT tests, see #75289).
Make sure this is averted by explicitly selecting ARM_AARCH32_MMU in the
SoC Kconfig.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
When switching off memory banks we cannot use movi with arbitrary
immediate arguments, they will be converted by the compiler to memory
accesses. Only constants within the allowed range should be used.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Only disable TCP/UDP software checksum if the ethernet
driver enabled. This is to avoid interfere with net tests
which don't need the on board driver to function
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This commit makes the RV32M1 SoC rely on the default behavior of relying on
the `CONFIG_RISCV_ISA_EXT_*` config options, and removes the
`zephyr_compile_options` override when the standard toolchain is used.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C
extension, and doesn't support the A extension. Apply fixes accordingly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Fixes an issue whereby multiple boards would be grouped when using
a regex to group them, and adds missing nRF91 entries to the list
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The power_down() function attempts to lock the hpsram_mask on-stack
variable in data cache, which causes an exception. Moving it to .bss
by making it static fixes it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
For SOCs that do not implement a custom `__reset` function,
select `INCLUDE_RESET_VECTOR` so that Zephyr provides a default
implementation that simply jumps to `__initialize`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
cpuppr can only use slow peripherals and uses RAM3 as RAM so
it does not need to use DMM.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
DMM was enforcing cache line alignment all memory regions, including
those which were not cacheable. Fixing it by using memory attribute
from the device tree to determine if alignment needs to be applied.
Because of that memory usage was significantly increased because
even 1 byte buffers (e.g. for uart_poll_out) was consuming 32 bytes
(cache line size).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
SYSTEM_WORKQUEUE_STACK_SIZE increase is required to fix not
only BLE Ext Adv (70935), but also other BLE use cases according
STM32WBA HCI driver
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
ESP32 requires proper alignment between sections. There are some
scenarios, as reported in #74533, that the section can
get shifted, causing runtime failure.
Making sure SECTION_PROLOGUE is used with ALIGN_WITH_INPUT
will guarantee its consistency.
Fixes#74533
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Fix the build issues with the insufficient memory for
the MCUboot.
- Fix the sysbuild with MCUboot tests on all ESP32xx SoCs.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Setting a boolean Kconfig option default to "n" after having set it to "y"
does not make the option disabled. Instead, avoid setting default to "y"
for SoCs known not to have dedicated USB RAM.
Fixes: #73912
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
