Call CMSIS SystemInit at early platform boot, to ensure that registers
are configured correctly on RT10xx series.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch updates ipc response procedure in power down function. New
flow is only limited to the writs into two registers. We need to clear
the IPCxIDD register in case if its contains any leftovers from a
previous responce. And then write a response to the IPCxIDR.
To prepare response we need to copy incoming request and then mark it as
replay. New message with IPC Busy bit set is then send to host.
The reason for this is a change in the behavior of the IPC driver
compared to how it worked when this function was originaly implemented.
The biggest difference are enabled interrupts in register IPCxCTL.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Zephyr maps start/end of rodata section with variables
using __rodata_region namespace. The exception was Xtensa.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add XIP support with MWDT toolchain. To have it proper tested
add separate nsim platforms for XIP (flash + sram) and
non-XIP (sram) memory organization in addition to existing
nsim_hs platfor with CCMs (ICCM + DCCM) memory organization.
This PR also enables MPU for all nsim hs3x based platforms
(like we previously enabled it for qemu_arc_hs) to have proper
memory regions permissions.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Since DTS doesn't contain the BDF anymore (it's looked up at runtime),
hardcode the BDF value for the use of early serial.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Update lpc54114 support to use LMA address offset instead of linking
secondary core image into primary core memory. This will allow support
with sysbuild to be enabled. Additionally, use partitions to select where
the secondary core image will be located in flash
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use LMA adjustment building dual core image with LPC55s69. The load
address adjustment allows the second core image to be flashed onto the chip
by the debugger, into the secure region of the LPC flash.
Additionally, remove the build dependency that was enforced by the SOC.
This requirement to build the secondary core image first can be enforced
by the project itself, instead of the core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move setting soc_num_cpus into its own SYS_INIT function such
that we can ensure it happens as one of the first things. We
need soc_num_cpus set before soc_mp_init is called but also before
interrupt controller init functions might be called.
Also, by having it in its own function, it ensures that
soc_num_cpus gets set regardless of how CONFIG_MP_MAX_NUM_CPUS
is set. Since if CONFIG_MP_MAX_NUM_CPUS=1, we do not call
soc_mp_init().
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
\MTL SOF is not compiling when
8d0eb6ce10
(devicetree: remove deprecated DT_CHOSEN_*_LABEL macros)
is applied
Fix - zephyr/toolchain used to be included by
devicetree/zephyr.h. The file has been removed by 8d0eb6ce10
Include is needed for ALWAYS_INLINE macro
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Move regs configuration from previous pinmux.c to soc layer.
This involves the debug interface, configuring the GPIO bank power
and the test clock out pin.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Only include fsl_flexspi_nor_boot when a boot header is present,
as this is the only case where the boot header data will be required.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use spisc_it8xxx2_regs instead of IT83XX_SPI_*** registers declaration
to fix in cros_shi_it8xxx2.c
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
The `mps2_an521_remote` and `mps2_an521_ns` targets have the same
memory layout for code and ram, meaning that you can't use TF-M
(`mps2_an521_ns`) and the second core (`mps2_an521_remote`) at the
same time.
This commit updates the memory map of the `_ns` build targets as
follows:
- Reduces the code memory region from 1 MB to 512 KB, maintaining the
existing base memory address of `0x0010 0000`
- Maintains the existing 512 KB ram memory at `0x2810 0000`
It updates the `_remote` target as follows:
- Reserves 468 KB code memory at address `0x0038 B000`
- Reserves 512 KB ram memory at address `0x2818 0000`
This ensures that the code region for the `_remote` target doesn't
overlap with the code region used by the single flash image layout
defined upstream in TF-M, which the `_ns` target is based upon.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
When CONFIG_MP_MAX_NUM_CPUS=1, which it does for some tests, we will
get compiler warnings with soc_adsp_halt_cpu(), so only build it
when CONFIG_MP_MAX_NUM_CPUS > 1.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Some SAM0 contains revisions with separated includes for example
SAMC21 and SAMC21N.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
We look at the Intra DSP communications capability register (DFIDCCP)
to determine the number of cores. There might be a better way to
determine the number of cores, but this works for now.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add Kconfig SOC_HAS_RUNTIME_NUM_CPUS symbol that an SoC can
set to specify that it supports determining the number of CPUs
at runtime.
On xtensa add support for SOC_HAS_RUNTIME_NUM_CPUS and expose
soc_num_cpus that the SoC code should set early in boot as the
means to expose the number of cpus.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Basically:
- Name RAMABLE_REGION as "RAM";
- Insert the relocation hooks for gen_relocate_app.py.
Also, to help with "rimage" peculiarities, `fix_elf_addrs.py` changed to
not copy empty sections to output, as this would prevent someone trying
to move all of some section (such as BSS) to a different location and
reuse the platform linker script - which would generate an empty section
anyway.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.
As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.
Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Xtensa is the odd one out by using _data_start/_data_end instead. Using
the Zephyr standard helps avoid ifdefs for common code, like tests.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Fix a bug where an IPC message is sent while the peer/host ack for
the previous message has not yet been processed. There is existing
logic to check 'idr' INTEL_ADSP_IPC_BUSY bit, but this leaves
the following race:
- DSP: msg A sent by DSP to host
- HOST: IRQ, msg A acked, host sets DONE bit -> ADSP_IPC_BUSY cleared
- DSP: msg B sent by DSP to host, IPC_BUSY is clear so proceeding to send
-> e.g. 'devdata->sem' is reset --> BUG!
- DSP: IRQ, msg A done
-> e.g. call to 'sem_give(&devdata->sem)' which is wrong as
the semaphore was just reset in previous step for msg B
Add additional state to track handling of the acks. This allows
to postpone sending message B (in above example), until message A
is fully processed.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
STM32WB Controller supports application to initiate the "PHY Update
Procedure" (BT_USER_PHY_UPDATE) while it doesn't support it to be
automatically triggered on connection establishment (BT_AUTO_PHY_UPDATE).
Default BT_USER_PHY_UPDATE to true, which automatically defaults
BT_AUTO_PHY_UPDATE to false.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update Intel ADSP timer driver to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove setting 'default y' for the timer driver in
Kconfig.defconfig.series as that is now handled in the driver Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Now that IPM drivers are enabled based on devicetree we can
remove any cases of them getting enabled by Kconfig, *defconfig*,
and *.conf files.
We need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x eSPI SAF has significant hardware changes
requiring a new SAF configuration structure. In preparation
for the MEC172x we move the current SAF header out of common
to the MEC1501 subfolder, remove an unused and empty common
header and remove includes of the moved headers from MEC172x.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus(). This is to allow
runtime determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add #ifdef CONFIG_SMP around code that only needs to exist when
SMP is enabled.
Also include ksched.h to get decleration of z_sched_ipi.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Cleanup CMakeLists fixing error message:
...
No SOURCES given to Zephyr library: soc__x86__raptor_lake
...
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
IT8xxx2 uses a relatively slow SPI flash for ROM with a small 4k
I-cache. As a result in large or busy applications, instruction fetch
can be very costly due to I-cache misses. Since exception handling code
is some of the hottest code in most applications, add an option (enabled
by default) causing that code to execute out of RAM in order to improve
performance.
This is very similar to exception section placement on XIP niosii
platforms (which has similar motivation), but can still be disabled by
configuration.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
These functions are small and may be very hot depending on the workload,
so are usually a good choice to execute from RAM.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
