XTENSA_CCOUNT_HZ is no longer common to ACE soc series
This will fix Hz value for ACE30 platform
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The Host Interface Type in the DEVCNT register sets the HIF type
(either eSPI or LPC).
Currently, it is configured in the host-interface-related drivers like
eSPI or SHI. However, some I/O pads sourced from VHIF in the other
modules such as GPIO and I3C also rely on this field. It might be
problematic when using those I/Os without enabling eSPI or SHI drivers.
This commit moves the setting from the specific drivers to the global
system initialization function scfg_init().
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Initial commit to suppor RA8D1 SoC
This is deveop base on RA8M1 so it will have similar stucture and
feature
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Some new Nordic nRF SoCs are based on a common platform, named
'Haltium'. Introduce a selectable Kconfig option available for series to
flag they are part of such common platform. This will allow to easily
enable common code shared across all Haltium based products.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
RA4M1-specific options were being applied system-wide because
conditions were not set properly.
This change fixes this problem.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Instead of forcing users to provide this setting, allow to describe
which signals require CLOCKPIN enablement at device nodes. This is later
captured by the pinctrl macros and applied in the pinctrl driver. Note
that name has been adjusted to nordic,clockpin-enable to avoid confusion
with clock related settings.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
custom arch_cpu_idle and arch_cpu_atomic_idle implementation was done
differently on different architectures. riscv implemented those as weak
symbols, xtensa used a kconfig and all other architectures did not
really care, but this was a global kconfig that should apply to all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add config file to host WiFi specific settings.
Introduce CONFIG_ESP_WIFI_MAX_THREAD_PRIO to be used
as a cap for the LL driver runtime.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The power_down() function will lock dcache for the hpsram_mask
array. On some platforms, the dcache lock will fail if the array
is on cache line that can be used for window register context
saves.
Work around this by aligning and padding the hpsram_mask to cacheline
size.
Link: https://github.com/thesofproject/sof/issues/9268
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
After flashed EC image, we needed to manually press the reset button
on it8xxx2_evb. Now, without pressing the button, we can disable
debug mode and trigger a watchdog hard reset for running tests.
After flash EC, running below tests can pass (without pressing the button):
west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api
west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api
west build -p always -b it8xxx2_evb tests/kernel/fatal/exception
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
For stm32 platforms where the sysclock is less or equal to
32MHz, the Ticks per second is reduced to 8000 (instead of
10000).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Many xtensa target jump from soc code directly into cstart and depend on
architecture code being initialized in arch_kernel_init(). Instead of
jumping to cstart, jump to newly introduced prep_c similar to all other
architectures, where common platfotm initialization will happen.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This change adds the device tree property for specifying oe-override
(output-enable override behavior), as well as defines for possible values
of the property.
RP2040 GPIOs can be configured to automatically invert the output-enable
signal from the selected peripheral function. This is useful for tasks like
writing efficient PIO code, such as in the i2c example in the rp2040
datasheet.
Signed-off-by: Yiding Jia <yiding.jia@gmail.com>
cplusplus-rom linker initialization was wrongly placed
in RAM area when it should be in ROM area.
Fixes#75853
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
In addition to Kconfig options (soon to be deprecated), allow
configuring the regulators using DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Previously, the `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 did not register the log module. This caused build
errors when DEBUG logging was enabled, as the `power.c` file attempted
to access a non-existent SOC log module for debug messages.
This commit fixes the issue by registering the log module in the
`soc.c` files for the specified SoCs, thereby resolving the build
errors.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Fix formatting for `soc.c` files for the IMXRT11xx, IMXRT5xx/CM33, and
IMXRT6xx/CM33 by running 'clang-format'.
Signed-off-by: Apoorv Singh <apoorv.singh@gin.de>
Convert NXP System Timer Module driver to a native driver.
Timer prescaler in tests is updated because short relative alarms
sometimes give false positives.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow developer to use the baremetal Bluetooth functionalities of the
CC13X2 and CC26X2 series SoCs without having to use the full Zephyr
Bluetooth stack.
Signed-off-by: Benedikt Streicher <streicher.b@posteo.de>
Convert NXP SWT watchdog driver to a native driver and extend the
SWT supported functionalities and configuration options.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Convert power management to native drivers retaining existing
functionalities. Presently only SoC reset support and power control
initialization is supported, but these drivers will be extended to
support power management as well.
MC_ME and MC_RGM peripherals are common enough to be reused by other NXP
S32 devices, whereas PMC has specific implementations for each SoC
series.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Allow CONFIG_NRF_APPROTECT_LOCK and
CONFIG_NRF_SECURE_APPROTECT_LOCK with TF-M with all the SOC's
that support TF-M.
Signed-off-by: Markus Lassila <markus.lassila@nordicsemi.no>
Split SIUL2 instance index for the MSCR and IMCR registers as required
by some pins. Pinmux macros definitions in hal_nxp must be updated
accordingly.
Fixes#76147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It seems this SiP variant is not sold by espressif directly, but it is
used by the Odroid Go. The Odroid Go documentation calls this a "custom"
model [1].
There already exists a SiP specific device tree include file:
zephyr/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi
[1] https://wiki.odroid.com/odroid_go/odroid_go#specifications
Signed-off-by: Gero Schwäricke <gero.schwaericke@posteo.de>
DMM shall be initialized as early as possible to allow drivers to
use it. For example, uart may need it early since it starts
RX during initilization in some configurations.
Making dmm_init() public and calling it in soc init function.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
