CC13/26xx's pinctrl_cc13xx_cc26xx.c driver included ioc.h and
(indirectly) pinctrl_soc.h which contained duplicate defines.
This change removes the header conflict and redundant definitions.
This prepares for subsequent changes in this change set that add
additional flags to the pinctrl driver which would otherwise trigger the
header conflict.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add Kconfig RISCV_SOC_HAS_CUSTOM_SYS_IO symbol so that a riscv
SoC can set to specify that it has a custom implementation for
sys_io functions.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
and enabled proper nrfx driver instance; instead, use one option per
peripheral type and include the corresponding shim driver flavor into
compilation basing on that option (not the one that enables the nrfx
driver as it was incorrectly done so far in some cases)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some EFR32 build broke after 3d2194f11e with:
pm.c:152: undefined reference to `pm_state_exit_post_ops'
Add an extra empty function to make this one build again.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
The Keystone 3 (K3) family encompasses a wider variety of SoC's.
This aligns the soc/arm64 naming with the soc/arm directory.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The PM hooks were guarded with CONFIG_PM_POLICY_CUSTOM, however, they
need to be guarded (if file is always compiled) with CONFIG_PM. In fact,
CONFIG_PM_POLICY_CUSTOM requires to implement a custom policy hook,
something this module did not provide.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The clock rates for ACE series of Intel Audio DSP have changed.
The values come from the SOF project in their board configs.
CONFIG_XTENSA_CCOUNT_HZ is also set so the arch timing test
can pass.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Updated the clock init to reflect the sdk also
updated the clock frequencies to reflect the
respective soc clock values, this file originally
contained unexpected clock values, updated comments
to reflect changes and got rid of doxygen style
comments
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle
cache coherency between cache and external non-caching master, such as DMA
controller.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Andes EXEC.IT (Execution on Instruction Table) is supported by Andes
toolchain only. Andes toolchain will replaces suitable 32-bit instructions
with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a
corresponding 32-bit instruction in look up table.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Enable PMP and set PMP granularity to 8 for most of ae350 bitstream.
This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Refine PMA driver and define MPU_ALIGN() to PMA granularity in
RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Synchronize ae350 linker.ld with riscv generic linker.ld and workaround
kernel object address may be 0x0 in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Align `soc/nxp_adsp` with new `WEST_SIGN_OPTS` option added to
`soc/intel_adsp` by recent commit d98a7c2f8d ("soc: xtensa: cmake: add
new WEST_SIGN_OPTS variable").
This allows per-board rimage customization at the CMake level. Example
in `zephyr/boards/xtensa/nxp_adsp_NEWBOARD/board.cmake`:
set(WEST_SIGN_OPTS -- -c rimage/config/special.toml)
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).
Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.
Add only needed driver strength and bias pins to PFC,
e.g. SDx and UART TX/RX pins.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.
Note: some of files copy-pasted from Renesas Arm 32
SoC directory and this commit is a temporary
solution, we need to rework it in order to use
the same source files for both architectures.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.
The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some boards has ESP_SPIRAM enabled by default, which is
causing issues when MCUboot is used as 2nd bootloader.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
