Commit graph

5973 commits

Author SHA1 Message Date
Jeff Daly
e32c362038 Microchip: create DTS and Kconfig definition of MEC172x LJ package.
Define extra pins and IP blocks in DTS and Kconfig for the LJ package of
the MEC172x SoC.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2023-02-27 19:41:11 +01:00
Francois Ramu
25279df662 soc: arm: stm32l4 serie has a stm32l4p5 device
Add the stm32l4p5 device to the list of stm32l4 plus

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-02-27 17:30:12 +01:00
Francois Ramu
74d10f3f27 soc: arm: stm32u5 config for the BackUp SRAM
Add the stm32U5 serie for the support of the STM32_BACKUP_SRAM
The PWR peripheral is enabled by the soc/arm/st_stm32/stm32u5/soc.c

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-02-27 11:35:07 +01:00
Marc Herbert
eead89e7f2 soc: intel_adsp: cavstool.py: simplify asyncio.run() call
Fixes the following warning:

cavstool.py:706: DeprecationWarning: There is no current event loop
  asyncio.get_event_loop().run_until_complete(main())

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-02-26 09:18:24 -05:00
Grant Ramsay
f92dd6d357 drivers: serial: Name the NS16550 variant Kconfig choice
Naming this choice allows setting a default value in defconfig.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-02-24 18:11:56 +01:00
Grant Ramsay
84f92c7bc3 soc: arm64: Add TI AM6234 SoC A53 support
Add minimal SoC support for the TI AM6X series Cortex-A53 Core.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-02-24 18:11:56 +01:00
Andrzej Głąbek
4e197b7c5e soc: nrf53: Warn if workaround for anomaly 160 cannot be applied
This is a follow-up to commit fe3b97a87f.

Add a cmake warning issued when the workaround for the nRF5340 anomaly
160 cannot be applied because the application is configured with no
system clock.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-02-24 09:22:57 +01:00
Gerard Marull-Paretas
d76f4f2c8a drivers: pinmux: mchp_xec: drop driver
Drop Microchip XEC driver in favor of pinctrl.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-23 16:56:04 -05:00
Gerard Marull-Paretas
9ca624eb13 drivers: pinmux: mcux: drop driver
Drop the MCUX driver in favor of Kinetis pinctrl driver.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-23 16:56:04 -05:00
Gerard Marull-Paretas
099012a59f drivers: pinmux: lpc11u6x: drop driver
Drop LPC11U6X pinmux driver in favor of pinctrl.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-23 16:56:04 -05:00
Gerard Marull-Paretas
33372b9e48 drivers: pinmux: mcux_lpc: drop driver
Drop MCUX LPC pinmux driver in favor of pinctrl.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-23 16:56:04 -05:00
Gerard Marull-Paretas
d925c660ed drivers: pinmux: stm32: drop driver
Drop STM32 pinmux driver in favor of pinctrl. Some definitions located
in pinmux headers were used by the pinctrl driver, so they have been
moved there.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-23 16:56:04 -05:00
Daniel DeGrasse
37a5158dc4 soc: arm: nxp_imx: rt5xx: cleanup core if booting from bootloader
Cleanup core if booting from bootloader using RT5xx. This is required
because the call to SystemInit will push data to the stack, and the
bootloader may have configured stack limits or MPU settings. Either
would cause the core to fault if these settings are not first
cleaned up.

Perform this cleanup if the boot header is not present, as in this case
the application was likely kicked off via a bootloader.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-02-23 10:45:02 +01:00
Tim Lin
00e6c19ab5 ITE: drivers/adc: Add config of ADC reference voltage full-scale 3300mV
This option can enable ADC internal reference voltage as
full-scale 3300mV.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-02-23 08:59:54 +01:00
Mikhail Siomin
8310f83726 soc: arm: nxp_imx: rt: Allow to include boot header.
Allow to include boot header for code linked into
not only FlexSPI controlled memory.
Fixes #53867

Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
2023-02-23 08:57:30 +01:00
Daniel Leung
53316d5c8e toolchain: rename xcc-clang to xt-clang
This reflects the actual compiler executable name of the Xtensa
LLVM/Clang compiler.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-02-22 08:35:46 -05:00
Andrzej Głąbek
fe3b97a87f soc: nrf53: Add workaround for anomaly 160
Implement a workaround for the nRF53 anomaly 160. This consist of
a set of writes to certain hardware registers that is done at boot
and a piece of code that is executed when the CPU is made idle and
that prevents the CPU from switching between active and sleep modes
more than five times within a 200 us period.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-02-22 08:50:18 +01:00
Andriy Gelman
8a97da056b drivers: dma: Add infineon xmc4xxx dma support
Adds dma drivers for xmc4xxx SoCs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Siyuan Cheng
b475e1fcbf zdsp: add ARC DSPLIB backend for zdsp
Introduce ARC DSPLIB backend zdsp library for ARC target.
Add agu and restrict attributes to map with ARC DSPLIB

Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-02-21 15:06:06 +01:00
Khor Swee Aun
5b17a6da84 soc: riscv: riscv-privilege: INTEL NIOSV support
Add support for INTEL FPGA NIOSV RISCV based Processors.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
2023-02-20 09:29:13 -05:00
Daniel DeGrasse
24b66b30eb soc: arm: nxp_imx: use CMSIS SystemInit for all NXP iMX.RT SOCs
Use CMSIS SystemInit for all NXP iMX.RT SOCs, to simplify initialization
flow, and remove redundant code where possible.

Introduce Kconfigs to disable Cache at boot, since SystemInit will enable
code cache on these platforms, which may be undesirable behavior.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-02-20 09:47:28 +01:00
Daniel DeGrasse
3b59b495b7 soc: arm: nxp_lpc: convert NXP LPC SOCs to use CMSIS SystemInit
Convert NXP LPC SOCs to use CMSIS SystemInit, and remove redundant code
where it exists. This will enable initialization flows to be more
standardized across all platforms.

Since LPC54xxx and LPC55xxx series enables SRAM banks in SystemInit,
provide Kconfigs to bypass this setting and keep additional SRAM
banks unclocked.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-02-20 09:47:28 +01:00
Daniel DeGrasse
1e83a34164 soc: arm: nxp_kinetis: move NXP Kinetis SOCs to use SystemInit
Add call to SystemInit for all NXP Kinetis SOCs and remove any
redundant code from initialization flow. This allows watchdog
initialization to be removed from all Kinetis SOCs as it is handled
by SystemInit.

Since Kinetis watchdog is enabled by default at boot, allow watchdog
setup to by bypassed with CONFIG_WDOG_ENABLE_AT_BOOT. This
setting requires the user to provide a watchdog configuration hook
using z_arm_watchdog_init, but will allow the watchdog to remain
enabled.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-02-20 09:47:28 +01:00
Hake Huang
c775387e16 usb: add usb device support for lpc55s28 platform
update the endpint in dts to 6 to alignd with RM
enable usb-device for LPC55S28
all USB supported tests/samples PASS

samples:
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T samples/subsys/usb/
...
INFO    - 7 of 25 test configurations passed (100.00%),\
0 failed, 18 skipped with 0 warnings in 73.49 seconds
...

tests
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T tests/subsys/usb/
...
INFO    - 3 of 4 test configurations passed (100.00%),\
0 failed, 1 skipped with 0 warnings in 36.39 seconds
...

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2023-02-19 20:57:40 -05:00
Jay Vasanth
b1cf745828 pm: MEC172x: enable device power mgmt in soc layer
Allow the the SoC to enter deep sleep when CONFIG_PM_DEVICE
is enabled. This will allow to selectively add low power
support for certain drivers like UART and ADC.
The previous checking of ifndef CONFIG_PM_DEVICE was
incorrect. The MEC172x requires the soc power file to perform
some operations when CONFIG_PM_DEVICE is enabled to allow
the hardware to shut down the PLL.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-02-19 20:39:40 -05:00
Adrian Warecki
ddad6226c0 adsp: boot: power: Separate watchdog state from core power
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-02-19 20:36:31 -05:00
Adrian Warecki
da4f20901f adsp: ipc: Emergency ipc message send
Added intel_adsp_ipc_send_message_emergency function that allows to send an
ipc message notifying about emergency event, such as watchdog timeout.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-02-19 20:36:31 -05:00
Adrian Warecki
625f226842 adsp: ace: Non-maskable interrupt handling
The non-maskable interrupt have no corresponding bit in INTERRUPT and
INTENABLE registers so its occurrence cannot be confirmed. Removed the code
that checked if the interrupt flag is set.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-02-19 20:36:31 -05:00
Aastha Grover
8f5bcb2e76 intel_adsp: ace: fix linker script for xcc-clang compiler
rodata section for xtensa overrides the .ctors section
containing the constructor info and the _ZEPHYR_CTOR_LIST_.
Removes the ctor related linker script lines from the rodata
section of the ace linker script to ensure that the .ctors is
properly generated and placed when using the xcc-clang compiler.

Fixes #54730

Signed-off-by: Aastha Grover <aastha.grover@intel.com>
2023-02-10 18:05:14 -06:00
Björn Stenberg
dcbc56cfe7 ethernet: stm32h7: Move DMA buffers from sram3 to sram2
PR #30403 implemented nocache regions for ethernet DMA buffers in sram3 to
fix issue #29915. Unfortunately, some STM32H7 variants do not have any
sram3 so they still suffer from #29915.

All H7 variants have sram2 though, so use that for targets without sram3.

Signed-off-by: Björn Stenberg <bjorn@haxx.se>
2023-02-09 22:14:07 +09:00
Guillaume Gautier
645d91b028 soc: arm: st_stm32: common: Increase the value of HW semaphore retry
When running the blinky example on STM32H747, with the BOOT_CM4 bit set
to 0, the M4 core goes into panic.
Increasing the value of the hardware semaphore retry prevents this.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-02-03 02:22:22 +09:00
Francois Ramu
0262d33478 soc: arm: stm32f3 enable Debug Module during SLEEP mode
This patch allows successive reflashing operation on stm32f3
boards by Enabling the Debug Module during SLEEP mode.
This will especially makes reflahing and debugging possible
with pyocd runner on west commands.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-02-02 10:35:17 +00:00
Tomasz Leman
60a20471b5 intel_adsp: ace: enable interrupts for secondary core
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tomasz Leman
6045eed2f3 intel_adsp: ace: enable core power gating
Allowing the power domain of non-active cores to enter power gating
state.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tomasz Leman
e1dbc2efef intel_adsp: ace: add core power off step
Adding additional core power-off before core is properly power-up after
power domains is wake up from power gaiting state.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tomasz Leman
a99b073392 intel_adsp: ace: d3 exit update
This patch is moving common power configuration code outside of the
section only for the primary core. This should be enabled for all cores
and it was put there probably by mistake.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-02-02 03:29:20 +09:00
Tom Burdick
156c7cd217 intel_adsp: bbzero/bmemcpy with picolibc fix
When building with picolibc and gcc, the loops to do zeroing/copying
get replaced by gcc with calls to memset/memcpy. This fails this early in
the boot process and results in an illegal instruction exception.

Marking the variables being manipulated in the calls as volatile prevents
the compiler from optimizing the loops (replacing them with memset/memcpy).

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2023-02-02 03:09:35 +09:00
Almin Iriskic
0dcd6925d3 soc: stm32: fix rtt on stm32u5 series by enabling GPDMA1 clock
On some STM32 MCUs SEGGER RTT is only working with realtime updates
when DMA is clocked. The STM32U5 series uses a new DMA controller
module called GPDMA.

Refs: #34324
Fixes: #54316

Signed-off-by: Almin Iriskic <almin.iriskic@student.tugraz.at>
2023-02-02 02:43:21 +09:00
Shawn Nematbakhsh
f0e790c66b soc: riscv: riscv-privilege: Add support for OpenTitan SOC
Add support for OpenTitan, an open source silicon root of trust.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-27 19:25:26 +09:00
Stancu Florin
9f6d8c1c23 soc: cc13xx_cc26xx: add Kconfig option for custom radio hwattrs
Useful for implementing board-specific antenna switching using the RF
event callback.

Signed-off-by: Stancu Florin <niflostancu@gmail.com>
2023-01-27 17:44:38 +09:00
Stancu Florin
65039bf287 soc: cc13xx_cc26xx: add P chip variants to Kconfig
Add SOC_CC1352P and SOC_CC2652P chip types to SoC's Kconfig
(with integrated high power amplifiers).

Also requires modifications to HAL TI's family conditions.

Signed-off-by: Stancu Florin <niflostancu@gmail.com>
2023-01-27 17:44:38 +09:00
Stancu Florin
200a0db01a soc: cc13xx_cc26xx: config option to enable boost mode
New KConfig option to set `CCFG_FORCE_VDDR_HH` inside CC13xx/CC26xx
customer configuration file, making it it possible to use 14dBm
TX power (instead of the default 13 dBm limitation).

Signed-off-by: Stancu Florin <niflostancu@gmail.com>
2023-01-27 17:44:38 +09:00
Jamie McCrae
ec7044437e treewide: Disable automatic argparse argument shortening
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-01-26 20:12:36 +09:00
Hein Wessels
3293d8057d soc: posix: inf_clock: add C++ support to NATIVE_TASK
Explicitly define function pointer as (void*)() and not (void*).
In C this cast is done implicitly, but C++ does not allow it.

Also, the const is moved to the correct location. Now it's a constant
pointer to a function(void) that returns void, instead of a pointer
to a function(void) returning (const void).

Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
2023-01-26 09:30:36 +01:00
Alberto Escolar Piedras
8a5273525e nrf52_bsim: Convert from a nRF52832 to a nRF52833
The nRF HW models have been updated to correspond to a 52833 instead
of a 52832. Let's follow them.

The motivation for the change is to enable proper BIS encryption support
(for BT LE Audio ISO).

Changes:

* Point in manifest to latest HW models

* SOC_COMPATIBLE_NRF52832 has been removed, and SOC_COMPATIBLE_NRF52833
added in its place (with no uses at this point)

* Where SOC_COMPATIBLE_NRF52832 was used to set encryption like for a 52832
(to avoid using the MAXPACKETLENGHT), we set the condition to just
SOC_NRF52832.
Note: The MAXPACKETLENGHT register exists in the new simulated nrf52833,
thought it does nothing.

* In the BLE ctrl LLL radio HAL, all macros are renamed accordingly
(timings are NOT changed).

* Board dts definition now refers to the 52833 soc definition. New 52833
features set as not supported by now.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-01-26 09:29:18 +01:00
Jeppe Odgaard
9fb47e43a8 dts: arm: add xbar and qdec nodes and update soc
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2023-01-24 10:21:39 -06:00
Manuel Arguelles
4a3c630f7b boards: s32z270dc2_r52: enable Ethernet support
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2023-01-24 14:37:20 +01:00
Tom Burdick
a684714d5c soc: intel_adsp: Correct HDA parameter docstrings
The parameter doc string for hda was incorrect as the parameters
had been updated to take the IP base address, block size, and stream id
instead. Updates all doc string comments to account for the change.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2023-01-23 11:51:21 -08:00
Tom Burdick
b14296af38 dma: HDA ignore repeated start/stop requests
The DMA API contract specifies that start/stop may be called multiple
times. Prior to adding power management this was perfectly fine as it was.
In adding power management, there are additional side effects that can
cause issues. Instead check the state of the channel prior to start/stop
and do nothing if already in the desired state.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2023-01-23 11:51:21 -08:00
Guennadi Liakhovetski
8ff8834695 xtensa: sparse: fix address space mismatch
Fix remaining sparse address space mismatch warnings.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-01-20 15:01:12 -05:00