Commit graph

5973 commits

Author SHA1 Message Date
Marc Herbert
67f7b43136 soc: xtensa: remote-fw-service.py: fix usage without sudo
It's best practice to run as little code as possible as root (especially
when listening to network ports). When not itself running as root
already, remote-fw-service.py has always tried to invoke cavstool.py
with "sudo". Unfortunately this looks like it never worked; at least not
on Ubuntu 22 where this commit was tested. Moreover it did not fail
immediately but mysteriously timed out without any useful error message.

- The first, most obvious bug was that "sudo" does not propagate
SIGKILL (and a few other signals), see "man sudo". Compare:

```
$ sudo sleep 30 &
$ kill  $! # sudo propagates the TERM signal and sleep is terminated

$ sudo sleep 30 & sudoPID=$!
$ kill -KILL $sudoPID
$  ps  xfao pid,ppid,pgid,sid,comm | grep -C 5 -e PID -e sleep -e sudo
```

Fix this by invoking proc.terminate() first before proc.kill().
proc.terminate() is more "polite" with cavstool even when not using
sudo.

- Second issue: when signals are sent to sudo, strace shows that its
signal handler invokes `getpgid()` and then ignores signals coming from
its own process group. `man sudo` states: "sudo will not relay signals
that were sent by the command it is running...", which seems related.

`start_new_session=True` option moves sudo to a different PGID which
stops sudo from ignoring signals from its remote-fw-service.py parent.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-03-28 16:42:29 -04:00
Francois Ramu
3b1dd7380b soc: arm: stm32h5 new soc serie
Introduce the new stm32h5 soc serie from STMIcroelectronics.
Note that stm32h503x do not have TrustZone nor SAU

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-03-28 15:07:51 +02:00
Luca Fancellu
0deeb5ff65 soc: include: fvp_aemv8r: Define device memory as device tree node
A recent change introduced the possibility to declare MPU memory
regions using the device tree and the framework described in
zephyr/linker/devicetree_regions.h.

So remove the device region declared in mpu_regions[] and the used
defines for the addresses, rename REGION_DEVICE_ATTR to REGION_IO_ATTR
in arm_mpu.h to be compatible with the framework and add a device tree
node to fvp_baser_aemv8r.dts to describe the device memory region.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
2023-03-27 13:20:47 +00:00
Sylvio Alves
10a7baba0e soc: esp32s3: add bluetooth support
This only adds proper HEAP and HCI definition to enable
BLE support to ESP32-S3.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-03-27 13:19:38 +00:00
Hein Wessels
68b9be8381 soc: arm: stm32h7: remove manual linker section
Remove the manually created linker section, because it's already
automatically generated for all sram regions in the DTS with the
"zephyr,memory-region" compatibility.

Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
2023-03-24 17:37:06 +00:00
Pavlo Havrylyuk
e40254a44a soc: infineon_cat1: add HardFp support PSoC 6
Added HardFp support for PSoC 6

Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
2023-03-24 11:34:45 +09:00
Jay Vasanth
b0ce525b90 drivers: espi: Microchip MEC172x eSPI VW initialization update
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-03-23 11:58:26 -04:00
Jay Vasanth
f6619a8688 drivers: espi: Update Microchip MEC172x eSPI virtual wires to use DT
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-03-23 11:58:26 -04:00
Manimaran A
c42a155988 driver: clock control: Microchip XEC fix missing domain parameter
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-03-23 11:55:19 -04:00
Jaska Uimonen
95168e6776 soc: intel_adsp: cavs: start using zephyr power management
Start using zephyr power management in cavs platform in a similar way
that is already done in ace. This commit only addresses the power off/on
sequence. Runtime power management is not implemented.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-03-23 07:57:14 -04:00
Anas Nashif
0f2a352cbd Revert "xtensa: remove ELF section address rewriting"
This reverts commit 7a85983ebc.

This commit was merged prematurely and is causing issues on multiple
platforms.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-03-22 08:35:52 -04:00
Yonatan Schachter
84665de122 soc: rpi_pico: Added panic handler
Some pico-sdk drivers call a panic function, originally implemented
as part of the Pico's C runtime. This commit adds a Zephyr compatible
implementation of panic, so that those drivers could be compiled with
Zephyr.

Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
2023-03-22 09:33:52 +01:00
Gerson Fernando Budke
88cedcf5c5 drivers: clock: Add Atmel SAM PMC driver
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-03-21 14:12:25 -07:00
Vaishnav Achath
cb953a4255 soc: arm: ti_simplelink: Add support for TI CC13X2X7 SoC series
Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf

Features:

Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation

Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h

Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
2023-03-21 16:03:43 -04:00
Krzysztof Chruscinski
9a73b9c80d hal_nordic: Change scheme for RTC and TIMER reservation
In general, RTC and TIMER driver implements counter API but there
are exception when those peripherals are used in a custom way
(e.g. for system timer or bluetooth). In that case, system must
prevent using counter based on a reserved instance. Previously,
it was managed by Kconfig options but that cannot be maintained
when switching to devicetree configuration of the counter driver.

A new approach removes Kconfig options and instead adds static
asserts in the files which are using direct peripherals. Those
asserts check if given node is not enabled in the device tree.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2023-03-20 16:59:40 +01:00
Jamie McCrae
417d704b86 soc: arm: nordic: Add GPREGRET register validation
Adds validation for Nordic nRF GPREGRET registers.

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-03-20 15:02:09 +01:00
Nikolay Agishev
14ec9e9dcb ARC: Add MWDT support into qemu_arc_hs platform
Add Metaware toolchain into qemu_arc_hs* platforms

Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
2023-03-20 11:43:37 +01:00
Yanqin Wei
a1f55c63b3 soc: fvp_aemv8r: add mpu region from device tree
Some platforms need to define multiple memory regions with
various attribute. This patch adds dts defined regions in the mpu
configuration. The memory attribute can be set in the device tree.

Signed-off-by: Yanqin Wei <Yanqin.Wei@arm.com>
2023-03-20 09:54:35 +01:00
Guennadi Liakhovetski
7a85983ebc xtensa: remove ELF section address rewriting
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2023-03-20 09:52:15 +01:00
Marc Desvaux
ba44549ae8 soc: arm: st_stm32: stm32l4: power.c ultra_low_power mode
STM32L4x power management (ultra_low_power) of Standby mode
and shutdown mode ultra_low_power

Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
2023-03-17 14:20:05 +01:00
Marc Desvaux
407216b505 soc: arm: st_stm32: stm32l4: power.c standby shutdownn mode
STM32L4x power management stop mode modification


Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
2023-03-17 14:20:05 +01:00
Manimaran A
2b66410675 soc: configuration: microchip SOC Kconfig bug fix
Removed the EEPROM and ESPI configuration from file
Kconfig.defconfig.mec172xnsz. Since it overrides the
setting present in the Device Tree file.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-03-16 12:03:57 -05:00
Francois Ramu
6199b9175a soc: arm: stm32h7 soc defines the _STM32H7_SOC_H_ flag
Fix the error of the _STM32H7_SOC_H_ flag name
for the stm32h7 serie

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-03-16 16:42:47 +01:00
Felipe
bd705e68b0 soc: xtensa: esp32: increase shared memory region
for esp32 and esp32_net because the default 2048
bytes are not sufficient for rpmsg usage.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
2023-03-16 16:42:13 +01:00
Tim Lin
94ae33c20a ITE: soc/riscv/ite: policy: Add minimum residency time to enter sleep
Adding this condition will limit the minimum residency time to enter
sleep mode. This will fix tests in test\kernel\sleep\usleep.c causing
longer than expected test times due to going into sleep mode with no
time limit.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-03-16 09:16:34 +01:00
Anisetti Avinash Krishna
e454203290 soc: x86: raptor_lake: Add GPIO support for rpl_crb
Enabled GPIO support for rpl_crb board by adding
platform GPIO specific definitions.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-15 22:41:53 +00:00
Artur Rojek
49fa1519df nxp: imx: Derive i.MX8 UARTs from DT bindings
Use Device Tree bindings to configure clock source/frequency for enabled
UARTs only.

Get rid of UART clock ungating from `soc.c`, as that functionality has
been moved to the clock controller.

Signed-off-by: Artur Rojek <artur@conclusive.pl>
2023-03-15 09:13:10 +01:00
Declan Snyder
48214e86b0 soc: rt: Add flash chosen node functionality
Add functionality for changing the code location
based on the flash chosen node for RT devices.

Remove obsolete Kconfigs that used to be used
to set the code location for RT devices.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-03-15 09:12:52 +01:00
Benjamin Björnsson
cc48212875 soc: arm: st_stm32: stm32c0: Add STM32C0 Series support
Add initial support of STM32C0 Series.

Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
2023-03-14 17:35:37 +00:00
Tomasz Leman
9854c915ff intel_adsp: cpu init refactor
Reusing existing code during CPU init at power gating exit.

Additional changes:
- replacing magic value for memctl and atomctl with more readable
  definitions,
- using dedicated macros in place of asm inlines.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-03-14 10:48:38 +01:00
Siyuan Cheng
f9d155b7d5 dts: boards :emsdp: add SPI support
There is a spi-flash fl256s on emsdp board, which can be
contolled by DesignWare SPI driver. Now add DW SPI and
SPI-FLASH support for emsdp board.

Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
2023-03-10 11:39:24 +01:00
Miika Karanki
1f49b5b56c soc: stm32u5: Add simple POWER_SUPPLY_CHOICE configuration
Allow selecting between direct SMPS and LDO on the startup. This
enables selecting to use SMPS regulators which can save bit of power.

Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
2023-03-07 15:49:57 +01:00
Chen Xingyu
7ae7847643 soc: arm: Add support for STM32H730xxQ
The STM32H730 series has a variant built with SMPS. It uses
`stm32h730xxq.h` header file instead of `stm32h730xx.h`, which has the
SMPS macro defined.

This commit adds the `SOC_STM32H730XXQ` configuration option to allow
the build system include the proper header file. With this change,
boards can enable `CONFIG_POWER_SUPPLY_DIRECT_SMPS` to set up the power
supply for the CPU.

Signed-off-by: Chen Xingyu <hi@xingrz.me>
2023-03-07 15:49:47 +01:00
Guillaume Gautier
b19f47d2b1 soc: arm: st_stm32: stm32f0: add kconfig for stm32f042x6
Add Kconfig for STMF042x6 to support the Nucleo F042K6.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-03-07 15:49:30 +01:00
Daniel DeGrasse
676278c0ec soc: arm: nxp_imx: r5xx: add clock initialization for MIPI and LCDIF
Add clock initialization for MIPI and LCIDF to NXP RT5xx SOC.
Note that clock divider properties are used by both initialization
routines, as the required clock divider will vary depending on
attached display.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-03-04 09:19:26 +01:00
Andriy Gelman
33d1792e3d drivers: spi: Add xmc4xxx driver
Adds spi driver for xmc4xxx SoCs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-03-03 17:20:17 +01:00
Andrzej Głąbek
ca9ac5a3e2 soc: nrf53: Restore accidentally removed suppress_message flag check
This is a follow-up to commit 7195db01f4.

Restore the check that was accidentaliy removed in the above commit,
so that the message is again logged only once per detection of the
anomaly 160 conditions.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-03-03 17:19:10 +01:00
Marc Herbert
a8c0123d3c intel_adsp: cmake: add_custom_command(.mod) to fix incremental build
Now building twice back to back does not build anything the second time
when CONFIG_CLEANUP_INTERMEDIATE_FILES (which obviously breaks
incremental builds) is also turned off.

Fixes commit 2906d1aa51 ("soc/intel_adsp: Build bootloader with Zephyr")

Properly implementing custom commands requires BOTH
`add_custom_command()` and an `add_custom_target()` wrapper with some
careful DEPENDS wizardry between them.

https://cmake.org/cmake/help/latest/command/add_custom_target.html
> Use the add_custom_command() command to generate a file with
> dependencies.

The documentation of add_custom_command() also similarly refers to
add_custom_target()

When this is not done properly, the build is cursed in various, very
time-consuming ways which are not officially documented but here
instead:
https://samthursfield.wordpress.com/2015/11/21/cmake-dependencies-between-targets-and-files-and-custom-commands

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-03-02 15:34:55 -05:00
Grant Ramsay
76a4b44227 soc: arm64: ti_sitara: Add pinctrl support for TI AM6X A53 SoC
TI Sitara processors use the K3 architecture

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-03-02 13:50:06 +01:00
Ning Shang
bd240d1fe5 ESP32-S2: fix - use correct storage label
This is a bugfix. It uses the right storage label `slot0_partition` for
esp32s2. Note that this is already the case for esp32 and esp32s3.

This should address
https://github.com/zephyrproject-rtos/zephyr/issues/55286.

Signed-off-by: Ning Shang <syncom.dev@gmail.com>
2023-03-02 09:59:10 +01:00
Andrzej Głąbek
7195db01f4 soc: nrf53: Change logging level of anomaly 160 message to DEBUG
This is a follow-up to commit fe3b97a87f.

This message should not be a warning, as it does not actually indicate
that something potentially bad happened. On the contrary, it informs
that conditions in which the anomaly 160 could occur were detected and
the anomaly was prevented from occurring. There is no need for this
message to appear in the default configuration (INFO level). In fact,
the message would undesirably flood the console in some cases (like
the kernel/mem_protect/stack_random test) and sometimes it would also
require enlarging the stack of the idle thread (the function is called
underneath k_cpu_idle()). Therefore, the logging level of this message
is changed to DEBUG.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-03-02 09:03:10 +01:00
Ruibin Chang
f77f02c032 ITE drivers/sensor/vcmp/it8xxx2: add work queue for voltage comparator
Voltage comparator driver submits notifications into system work queue,
this change will make driver to use dedicated work queue, and priority
of dedicated work queue are configurable as well.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2023-03-01 09:12:49 -06:00
Hein Wessels
e01270793e drivers: dma: stm32: bdma support for H7
Implement STM32H7 BDMA driver.

Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
2023-03-01 15:58:27 +01:00
Nazar Palamar
dcf52fd566 drivers: pinctrl: Add Infineon CAT1 Pin controller driver
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2023-03-01 11:44:57 +01:00
Nazar Palamar
750475f3b8 soc: arm: Introduce Infineon CAT1/PSoC 6 SOC integration
Add initial version of Infineon CAT1/PSoC 6 SOC integration.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2023-03-01 11:44:57 +01:00
Gerard Marull-Paretas
27b73a116f soc: arm: nordic_nrf: replace NRF_DT_CHECK_PIN_ASSIGNMENTS
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-28 08:42:05 -08:00
Sylvio Alves
f18d811c6c soc: esp32c3: fix soc architecture definition
Update ESP32-C3 architecture as IMC instead IMA.

Although not documented, ESP32-S3 supports CSR instructions.
It also needs to be enabled, otherwise build will fail.

Fixes #53555

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-02-28 12:47:56 +01:00
Jonas Otto
60b8773491 arch: riscv enable flash config
For RISCV arch, enable FLASH_SIZE and FLASH_BASE_ADDRESS config.
To avoid duplicated work, remove flash config from RISCV soc.

Signed-off-by: Jonas Otto <jonas@jonasotto.com>
2023-02-28 10:29:03 +01:00
Fabio Baltieri
1751c8f0f5 soc: mec172x: drop non existing option PINMUX_XEC
Drop the non existing option PINMUX_XEC, this has been removed in

d76f4f2c8a drivers: pinmux: mchp_xec: drop driver

And is currently causing build errors.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-02-27 20:52:51 +01:00
Sylvio Alves
bbd40b85c0 soc: esp32s3: add base source content
This brings esp32s3 linker, DTS and all
necessary files to allow the soc support.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-02-27 19:41:33 +01:00