Commit graph

7,339 commits

Author SHA1 Message Date
Declan Snyder
6e7f86ce86 soc: nxp: Move connectivity defaults to common
Move default of monolithic and fw loader, options, etc to the
common kconfig files rather than defaulting in soc file.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
b00d881398 soc: nxp: Consolidate ROM RAMLOADER config
Consolidate the ROM RAMLOADER config to be in one place,
add a new Kconfig file to be included by the SOCs with the feature.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
4e9227641e drivers: usb device: Remove MCUX controller type
The CONFIG_USB_MCUX_CONTROLLER_TYPE choice config
is not necessary, let's just remove it. Theoretically,
if there was an SOC with the EHCI and LPCIP3511, then
it might cause a build error, but there is no SOC
which is supported on this legacy driver that has that.

Remove all settings of it in the SOC files.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
dae9e75e04 soc: nxp: rw: Delete unused configs
Delete some unused kconfigs in RW SOC family.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
a097cdc4fe soc: nxp: Centralize flexspi related configuration
Currently this code related to how to configure the
flash size and address when using flexspi to XIP is copy
pasted in all sort of places and ways all over the tree,
let's clean this up and have single point of control over
this configuration.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
6300dc6aa7 soc: nxp: mcx: Do not use family level config
Move all dependencies of the family config to series level,
and put a disclaimer saying not to use the family config.

Change all occurrences of the family config in code to the
MCXNX4X series config.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
3c5df36dda soc: nxp: Move flexspi log level change to driver
Single point of control over this kconfig's effect.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
1d3864addf soc: nxp: Remove RT1061 and RT1051 refs
NXP is not supporting these derivative parts in the zephyr upstream,
these references to them should therefore be removed in order to avoid
confusion.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
f6bfedf114 soc: nxp: imxrt: Clang format flexspi_nor_config.h
Check compliance is not allowing changes to this file
without running clang-format.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
9d9d2f8178 soc: nxp: mcx: Fix Kconfig files and MFD config
The Kconfig defaults should be in Kconfig.defconfig.

MFD should not be made dependent on the LP flexcomm being
enabled, since MFD can be for other things than just flexcomm.
Change from depends on to an if.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
5360c57dc4 soc: nxp: Do not change driver init priorities
Doesn't seem like there is any reason to be changing the
serial and ADC driver init priorities in the SOC defconfigs.
By default, clock control has priority 30, dma has priority 40,
and serial/adc have priority 50. This seems already to be the order
that is needed, and the original goal of these overrides, which
don't seem necessary anymore.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
5d954917bd soc: nxp: Move kinetis pinctrl to include/
There are some SOCs which use the same pinctrl
device, but are not really overall that similar to the kinetis
family of SOCs, so prepare to reuse this code by other SOC families.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Declan Snyder
e2d3fe91fd soc: imxrt118x: Cleaning up kconfigs
Moving RT118x kconfigs to series level instead of family level,
and cleaning up redundant declarations, and adding missing
HAS_MCUX_FLEXSPI selection.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-22 09:14:24 +02:00
Tu Nguyen Van
ee6620e15f dts: arm: nxp: add Flexcan support for S32Z27x
Add FlexCan nodes to S32Z27x devices

Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
2024-08-21 11:03:44 +02:00
TOKITA Hiroshi
0877b3a354 soc: renesas: ra: Add RA2A1 SoC support
Add Support for Renesas RA2A1 SoC.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2024-08-21 08:58:17 +02:00
Flavio Ceolin
32cf0e0f9f intel_adsp: ace: Fix undefined reference
/zephyr/soc/intel/intel_adsp/ace/power.c:46:9: warning: implicit
declaration of function 'cache_data_flush_range'; did you mean
'sys_cache_data_flush_range'? [-Wimplicit-function-declaration]
   46 |         cache_data_flush_range((__sparse_force void *)
      |         ^~~~~~~~~~~~~~~~~~~~~~
      |         sys_cache_data_flush_range

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-08-20 19:43:37 -04:00
Flavio Ceolin
8fb592dfff soc: intel_adsp: DCACHE_LINE_SIZE was not defined
The symbol DCACHE_LINE_SIZE was not being defined in Intel ADSP
targets.

It fixes the following problem:

/zephyr/soc/intel/intel_adsp/ace/power.c:30:29: error:
'CONFIG_DCACHE_LINE_SIZE' undeclared here (not in a function); did you
mean 'XCHAL_DCACHE_LINESIZE'?  30 | uint8_t
adsp_pending_buffer[CONFIG_DCACHE_LINE_SIZE]
__aligned(CONFIG_DCACHE_LINE_SIZE);

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-08-20 19:43:37 -04:00
Marcio Ribeiro
f86314ecb6 logging: startup: esp32: startup log messages format unification
Unification of startup log messages format while using SIMPLEBOOT.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-08-20 14:53:42 -04:00
Pisit Sawangvonganan
daae40811e style: soc: comply with MISRA C:2012 Rule 15.6
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-08-20 10:33:51 +02:00
Peter Ujfalusi
85758444f7 intel_adsp: clk: Configure correct cardinal clock divider for PTL
The Audio integration PLL is faster on PTL compared to earlier ACE
platforms: 442.368 MHz instead 393.216 MHz, however the default
divider remained 16, which will result incorrect cardinal clock speed.

Change the divider to 18 in order to get correct 24.576 MHz cardinal
clock.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2024-08-20 10:33:04 +02:00
Zhengwei Wang
1eb831efc3 soc: ambiq: Add power management support for Apollo3 SoCs
This commit adds support for the power management for
Apollo3/Apollo3P SoCs

Signed-off-by: Zhengwei Wang <zwang@ambiq.com>
2024-08-20 10:32:52 +02:00
Joseph Liu
3fb70c677a soc: arm: add nuvoton npcm400 support
Add initial support for nuvoton npcm400, which is a chip
family of Satellite Management Controller(SMC).

Add ecst python scripts to append the header used by ROM Code

Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
2024-08-20 10:32:43 +02:00
Thao Luong
4cebe5354f drivers: adc: initialize to add ADC driver
Add minimal ADC driver code for EK-RA8M1 board

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
2024-08-20 10:31:43 +02:00
Anke Xiao
df2858944a soc: nxp: kinetis: ke1xz: add support cpu power states
Enable the NXP Kinetis Low Power Timer (LPTMR) timer driver when
power management is enabled.
When the NXP KE1xZ SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
2024-08-19 15:18:33 -04:00
Fin Maaß
c3752bf442 soc: riscv: litex: soc.h: add litex_write64
add function for a 64-bit write in litex.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-19 10:02:01 -04:00
Mike Banducci
5a8e60b12e soc: stm32: Add support for the stm32h755
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.

Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
2024-08-19 10:01:39 -04:00
Chun-Chieh Li
3b1d2bb286 soc: nuvoton: numaker: m46x: fix hirc48m typo
Fix typo on HIRC48M. This clock source is required by:
- USB 1.1 OTG PHY
- USBD
- USBH
- OTG

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
2024-08-19 10:00:07 -04:00
Thao Luong
8a475e5431 soc: renesas: ra: Sort MCU in soc.yml
Sort RA MCU follow device series.

Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
2024-08-19 09:59:27 -04:00
Quy Tran
370bd31d2a dts: bindings: clock: Change clock control binding for Renesas RA
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
5f4b9bb0d9 soc: renesas: Add initial support for RA6M4 SoC
- Initial support for RA6M4 SoC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
5f53861508 soc: renesas: Add initial support for RA6M2 SoC
- Initial support for RA6M2 SoC

Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
26159f4ad7 soc: renesas: Add initial support for RA6M1 SOC
- Initial commit to support RA6M1 SOC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
5f454da371 soc: renesas: Add initial support for RA6E2 SOC
Initial support for Renesas RA6E2 SOC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
ed0bdfbee6 soc: renesas: Add initial support for RA6E1 SoC
Initial commit to support RA6E1 SoC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: default avatarQuy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
300382aab2 soc: renesas: Add initial support for RA6M3 SoC
Initial commit to support RA6M3 SoC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
c9ba4bf234 soc: renesas: Add initial support for RA6M5 SoC
Initial commit to support RA6M5 SoC

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
2024-08-19 09:59:27 -04:00
Duy Phuong Hoang. Nguyen
ffad404a6a drivers: pinctrl: Update pinctrl driver name for Renesas RA series
Update pinctrl driver which used for Renesas RA series with
PFS secure register

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
2024-08-19 09:59:27 -04:00
Maxime Vincent
a08335b317 soc: arm: nxp: add lpc55x26 SCTimer support
Add support for the LPC55x26 SCTimer peripheral

Signed-off-by: Maxime Vincent <maxime@veemax.be>
2024-08-19 09:57:28 -04:00
Maxime Vincent
af5aabf245 soc: arm: nxp: add lpc55x26 support
Add basic support for the LPC55x26 SoCs

Signed-off-by: Maxime Vincent <maxime@veemax.be>
2024-08-19 09:57:28 -04:00
Raffael Rostagno
fad55d18ad soc: esp32c2: Add support to ESP32C2 and ESP8684
Files for SoC support: ESP32C2 and ESP8684 (same core).
Basic device tree configuration.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-16 14:08:22 -04:00
Krzysztof Chruscinski
cd3dae7c2c soc: arm: nordic_nrf: timing: Fix wrapping
Fix wrapping case for SoC with 32 bit TIMER.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-08-16 08:50:13 -04:00
cyliang tw
5025487dd0 soc: nuvoton: numaker: add poweroff for m2l31x
Add support of sys_poweroff API on m2l31x series.
It could support SPD0~2 standby or DPD0~1 deep power down mode.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2024-08-16 11:20:26 +01:00
Gerard Marull-Paretas
8e7919cf65 drivers: mbox: nrfx_ipc: enable based on DT status
Enable the driver using the standard mechanism used everywhere else in
the tree. It is possible here as it is a singleton, so there's no
dependency on nrfx instantiation magic.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-08-16 11:20:08 +01:00
Lucien Zhao
d7c9bd88ca soc: nxp: imxrt: add imxrt118x series and update related files
Add new RT118x device, due to structure is different from rt11xx series.
Boot header also differ from rt10xx and rt11xx, so add support for boot
container.

define new container name and new container tag

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-08-15 14:51:02 -04:00
Raffael Rostagno
3ee2a62a55 pm: esp32c6: Power management support
Power management support (light/deep sleep) for ESP32C6

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2024-08-15 11:59:08 -04:00
Alberto Escolar Piedras
50145bbf61 Kconfig: Link to deprecation instructions
Let's link from the deprecated instructions.
To increase visibility and hopefully avoid developers forgetting to
do so.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2024-08-15 12:40:16 +02:00
Declan Snyder
96d25bf903 MAINTAINERS: Remove DT bindings area
Now that the dts/bindings filter has been removed from
Devicetree Binding area, this area serves no real purpose.

Move the include/dt-bindings files to their respective areas.

Fix some of the orphaned dts/bindings paths.

Add regex filter for any binding with "zephyr" in the name to be
in the devicetree area.

Fix the imx_spc.h file being in it's own pm/ folder instead of
power/ like the other power related headers.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-08-15 10:16:21 +01:00
Mahesh Mahadevan
d27facff57 soc: rw6xx: Add support to wakeup from an external pin
Add support to wakeup from an external pin

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2024-08-15 10:15:28 +01:00
Neil Chen
007499ac41 soc: mcxn23x: add SOC support for MCXN23x
Change mcx series to "mcxn" and add MCXN23x support

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2024-08-15 10:15:12 +01:00
Maochen Wang
05d5044a38 soc: rw6xx: Enable NXP_WIFI_MONOLITHIC feature
The monolithic feature allows to link the binary blobs with
the application during the build.

Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
2024-08-14 15:54:50 -05:00