Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The STM32 G4 series has a built-in Arm Instrumentation Trace
Macrocell. Set CONFIG_HAS_SWO to enable this.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Configure the SYS_CLOCK_TICKS_PER_SEC directly from the
DTS st-prescaler property of the lptim node
aka stm32_lp_tick_source
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.
Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Use the already available in the tree mechanism of adding assembly
instructions right after WFI/WFE to implement the workaround for
nRF5340 anomaly 168 (replace the 4 NOP solution used on the network
core as it turned out to be insufficient) and provide two related
Kconfig options so that users are able to adjust the workaround to
their actual needs (disable it entirely or use it in the extended
version).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Enable the TF-M NS storage partition for nordic boards.
This partition is otherwise not used, and configured as secure.
Fixes: #59376
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Currently Code Cache cannot be enabled because its initialization is
guarded by Kconfig options which depend on CPU core cache support,
but S32K14x devices has a SoC specific L1 cache controller. Hence,
introduce a SoC-specific symbol to enable Code Cache.
Note that the cache controller is not available for S32K11x devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update the Kconfig for the npcx eSPI driver so it's automatically
enabled if the devicetree node is enabled.
Signed-off-by: Keith Short <keithshort@google.com>
Microchip's PolarFire SoC (MPFS) has 186 available interrupts.
Fix the Kconfig symbols.
While we're at at: remove commented out code
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
GCLK Gen 2 was dedicated to USB, but never setup... this patch
configures it for 48 MHz, derrived from DFLL.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Following changes in #64978, align CPU_HAS_xCACHE symbols with
the CMSIS feature definitions in the device headers so that
both have the same value.
Fixes#66147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Some SoC have missing feature selections in their Kconfig.
Some others are missing includes of CMSIS-Core headers.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7
definition renders them mandatory.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This changes remove extraneous includes causing issues with cycles in
includes subsequently having code requiring definitions from CMSIS
while it’s configuration hasn’t completed yet.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Kconfig parameters, header’s default & silicon vendor’s SDK configuration
for CMSIS Core, must be consistent. Depending on the inclusion order of
the headers, this is currently not always the case.
This change introduces consistency checks & enusers defaults match their
Kconfig settings.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Introduce support for NXP S32K1 family of 32-bit MCUs, and
particularly for S32K146 devices. S32K1 share a fair amount of
similarities with Kinetis family, so most of the peripheral drivers
can be reused.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is a part of introduction of new WTD instances.
It adds new Kconfig symbols that can be used in WDT shim and
nrfx driver.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
In an earlier commit, the riscv-privileged level implementation of
`arch_cpu_idle()` is not included unless `CONFIG_RISCV_HAS_CPU_IDLE` is
enabled.
This commit ensures the option is enabled on all the existing CPUs, thereby
maintaining the existing behavior.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
The current configuration comes with a common implementation of
`arch_cpu_idle()` for the whole riscv-privileged family, utilizing the
`WFI` instruction to place the CPU into a light sleep state, with the
assumption that it will be awakened later by interrupts such as SYSTICK.
However, this approach is not always effective, particularly in scenarios
where the SYSTICK is not a valid wake source.
This commit uses `CONFIG_RISCV_HAS_CPU_IDLE` as the build condition of the
family-level `idle.c`, allowing CPUs that do not enable this option to
fallback to a generic arch-level implementation in
`arch/riscv/core/cpu_idle.c`.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Change makes EGU instance used for anomaly 109 workaround configurable.
The default EGU instance (5) may be used for other purpose.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Reset cause reason was not initalized properly, making
hwinfo feature not to work as expected.
Fixes#65634
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There are symbols are both defined by the NXP S32 HAL and
the CMSIS RTOS V2 wrapper, to avoid interference between
them, redefine the symbols under an enum.
Also this is may a common issue for all NXP S32 platforms,
move to common place to be reused
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
introduce global DSP_SHARING and CPU_HAS_DSP to be used by all
architectures and change existing usage in ARC to use those global
configs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
r8a779f0 SoC is part of the Renesas R-Car Gen4 SoC series.
This SoC has a dual core lockstep Cortex-R52 CPU.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas R-Car Gen4 is different from Gen3 regarding pinmux.
While Gen3 had only one base address to manage all pins,
Gen4 has one set of pinmux registers per GPIO banks.
We could expose one pinmux register per GPIO controllers,
but that would break potential compatibility with Linux
Device tree.
Instead create a reg_base array to parse all reg base from
device tree and identify proper base address based on the pin
definition.
This imply to add a pfc_base parameter to most of the pfc_rcar
function.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The original SHI module only has one output FIFO buffer. It costs a lot
when the driver has to send/change the protocol control code because it
must fill out all 128 bytes of output FIFO. In npcx4, we introduce
another output buffer in 1-byte depth. These two buffers can switch back
and forth during the transaction. We can use the single-byte buffer
to send the control code and the 128-byte FIFO to send the data payload.
It helps improve the SHI driver's efficiency.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
