soc: stm32: add support for stm32h757
Add support for STM32H757 SoC, which shares its design with STM32H747 with added cryptography peripherals. Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>
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8 changed files with 120 additions and 1 deletions
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@ -109,7 +109,8 @@
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defined(CONFIG_SOC_STM32H747XX_M7) || defined(CONFIG_SOC_STM32H747XX_M4) ||\
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defined(CONFIG_SOC_STM32H750XX) ||\
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defined(CONFIG_SOC_STM32H753XX) ||\
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defined(CONFIG_SOC_STM32H755XX_M7) || defined(CONFIG_SOC_STM32H755XX_M4)
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defined(CONFIG_SOC_STM32H755XX_M7) || defined(CONFIG_SOC_STM32H755XX_M4) ||\
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defined(CONFIG_SOC_STM32H757XX_M7) || defined(CONFIG_SOC_STM32H757XX_M4)
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/* All h7 SoC with maximum 480MHz SYSCLK */
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#define SYSCLK_FREQ_MAX 480000000UL
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#define AHB_FREQ_MAX 240000000UL
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21
dts/arm/st/h7/stm32h757.dtsi
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21
dts/arm/st/h7/stm32h757.dtsi
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@ -0,0 +1,21 @@
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/*
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* Copyright (C) 2024 Grinn sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h747.dtsi>
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/ {
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soc {
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compatible = "st,stm32h757", "st,stm32h7", "simple-bus";
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cryp: cryp@48021000 {
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compatible = "st,stm32-cryp";
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reg = <0x48021000 0x400>;
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clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
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interrupts = <79 0>;
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status = "disabled";
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};
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};
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};
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29
dts/arm/st/h7/stm32h757Xi_m4.dtsi
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29
dts/arm/st/h7/stm32h757Xi_m4.dtsi
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@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2024 Grinn sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/h7/stm32h757.dtsi>
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/delete-node/ &flash0;
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/ {
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cpus {
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/delete-node/ cpu@0;
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};
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soc {
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flash-controller@52002000 {
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flash1: flash@8100000 {
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reg = <0x08100000 DT_SIZE_K(1024)>;
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bank2-flash-size = <1024>;
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};
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};
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mailbox@58026400 {
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interrupts = <126 0>;
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};
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};
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};
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34
dts/arm/st/h7/stm32h757Xi_m7.dtsi
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34
dts/arm/st/h7/stm32h757Xi_m7.dtsi
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@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2024 Grinn sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/h7/stm32h757.dtsi>
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/delete-node/ &flash1;
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/ {
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cpus {
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/delete-node/ cpu@1;
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};
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "DTCM";
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};
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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};
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mailbox@58026400 {
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interrupts = <125 0>;
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};
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};
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};
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@ -133,6 +133,10 @@ family:
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cpuclusters:
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- name: m7
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- name: m4
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- name: stm32h757xx
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cpuclusters:
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- name: m7
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- name: m4
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- name: stm32l0x
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socs:
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- name: stm32l010x4
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@ -59,6 +59,12 @@ config SOC_STM32H755XX_M7
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config SOC_STM32H755XX_M4
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select CPU_CORTEX_M4
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config SOC_STM32H757XX_M7
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select CPU_CORTEX_M7
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config SOC_STM32H757XX_M4
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select CPU_CORTEX_M4
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config SOC_STM32H7A3XX
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select CPU_CORTEX_M7
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15
soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h757xx
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15
soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h757xx
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@ -0,0 +1,15 @@
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# ST STM32H757X MCU configuration options
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#
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# Copyright (c) 2024 Grinn sp. z o.o.
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_STM32H757XX_M7 || SOC_STM32H757XX_M4
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config STM32H7_DUAL_CORE
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default y
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config NUM_IRQS
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default 150
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endif # SOC_STM32H757XX_M7 || SOC_STM32H757XX_M4
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@ -68,6 +68,14 @@ config SOC_STM32H755XX_M7
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bool
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select SOC_SERIES_STM32H7X
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config SOC_STM32H757XX_M4
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bool
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select SOC_SERIES_STM32H7X
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config SOC_STM32H757XX_M7
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bool
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select SOC_SERIES_STM32H7X
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config SOC_STM32H7A3XX
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bool
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select SOC_SERIES_STM32H7X
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@ -110,3 +118,4 @@ config SOC
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default "stm32h750xx" if SOC_STM32H750XX
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default "stm32h753xx" if SOC_STM32H753XX
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default "stm32h755xx" if SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4
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default "stm32h757xx" if SOC_STM32H757XX_M7 || SOC_STM32H757XX_M4
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