soc: stm32: add support for stm32h757

Add support for STM32H757 SoC, which shares its design
with STM32H747 with added cryptography peripherals.

Signed-off-by: Grzegorz Runc <g.runc@grinn-global.com>

drivers/clock_control/clock_stm32_ll_h7.c

@@ -109,7 +109,8 @@
 	defined(CONFIG_SOC_STM32H747XX_M7) || defined(CONFIG_SOC_STM32H747XX_M4) ||\
 	defined(CONFIG_SOC_STM32H750XX) ||\
 	defined(CONFIG_SOC_STM32H753XX) ||\
-	defined(CONFIG_SOC_STM32H755XX_M7) || defined(CONFIG_SOC_STM32H755XX_M4)
+	defined(CONFIG_SOC_STM32H755XX_M7) || defined(CONFIG_SOC_STM32H755XX_M4) ||\
+	defined(CONFIG_SOC_STM32H757XX_M7) || defined(CONFIG_SOC_STM32H757XX_M4)
 /* All h7 SoC with maximum 480MHz SYSCLK */
 #define SYSCLK_FREQ_MAX		480000000UL
 #define AHB_FREQ_MAX		240000000UL

dts/arm/st/h7/stm32h757.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2024 Grinn sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h747.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32h757", "st,stm32h7", "simple-bus";
+
+		cryp: cryp@48021000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x48021000 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
+			interrupts = <79 0>;
+			status = "disabled";
+		};
+	};
+};

dts/arm/st/h7/stm32h757Xi_m4.dtsi

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Grinn sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h757.dtsi>
+
+/delete-node/ &flash0;
+
+/ {
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash1: flash@8100000 {
+				reg = <0x08100000 DT_SIZE_K(1024)>;
+				bank2-flash-size = <1024>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <126 0>;
+		};
+	};
+};

dts/arm/st/h7/stm32h757Xi_m7.dtsi

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 Grinn sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h757.dtsi>
+
+/delete-node/ &flash1;
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "zephyr,memory-region", "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		mailbox@58026400 {
+			interrupts = <125 0>;
+		};
+	};
+};

soc/st/stm32/soc.yml

@@ -133,6 +133,10 @@ family:
       cpuclusters:
       - name: m7
       - name: m4
+    - name: stm32h757xx
+      cpuclusters:
+      - name: m7
+      - name: m4
   - name: stm32l0x
     socs:
     - name: stm32l010x4

soc/st/stm32/stm32h7x/Kconfig

@@ -59,6 +59,12 @@ config SOC_STM32H755XX_M7
 config SOC_STM32H755XX_M4
 	select CPU_CORTEX_M4
 
+config SOC_STM32H757XX_M7
+	select CPU_CORTEX_M7
+
+config SOC_STM32H757XX_M4
+	select CPU_CORTEX_M4
+
 config SOC_STM32H7A3XX
 	select CPU_CORTEX_M7
 

soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h757xx

@@ -0,0 +1,15 @@
+# ST STM32H757X MCU configuration options
+#
+# Copyright (c) 2024 Grinn sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H757XX_M7 || SOC_STM32H757XX_M4
+
+config STM32H7_DUAL_CORE
+	default y
+
+config NUM_IRQS
+	default 150
+
+endif # SOC_STM32H757XX_M7 || SOC_STM32H757XX_M4

soc/st/stm32/stm32h7x/Kconfig.soc

@@ -68,6 +68,14 @@ config SOC_STM32H755XX_M7
 	bool
 	select SOC_SERIES_STM32H7X
 
+config SOC_STM32H757XX_M4
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H757XX_M7
+	bool
+	select SOC_SERIES_STM32H7X
+
 config SOC_STM32H7A3XX
 	bool
 	select SOC_SERIES_STM32H7X
@@ -110,3 +118,4 @@ config SOC
 	default "stm32h750xx" if SOC_STM32H750XX
 	default "stm32h753xx" if SOC_STM32H753XX
 	default "stm32h755xx" if SOC_STM32H755XX_M7 || SOC_STM32H755XX_M4
+	default "stm32h757xx" if SOC_STM32H757XX_M7 || SOC_STM32H757XX_M4