soc: rp2350: Add initial support for the Raspberry Pi RP2350

RP2350 is Raspberry Pi's newest SoC. From the datasheet:

"RP2350 is a new family of microcontrollers from Raspberry Pi that
offers significant enhancements over RP2040. Key features include:
• Dual Cortex-M33 or Hazard3 processors at 150 MHz
• 520 kB on-chip SRAM, in 10 independent banks
• 8 kB of one-time-programmable storage (OTP)
• Up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus
...
"

This commit introduces some changes to support the existing RP2040 and
what is describe by Raspberry Pi as the "RP2350 family". Currently there
are 4 published products in the family: RP2350A, RP2350B, RP2354A, and
RP2354A. Within Zephyr's taxonomy, split the configuration as follows:
Family: Raspberry Pi Pico. This contains all RP2XXX SoCs,
SoC Series: RP2040 and RP2350.
SoC: RP2040 and, for now, just the RP2350A, which is present on the Pico
2, where the A suffix indicates  QFN-60 package type. This structure is
reflected in `soc/raspberrypi/soc.yml`, and somewhat assumes that there
won't be a RP2050, for example, as a RP2040 with more RAM.

This is foundation work ahead of introducing support for Raspberry Pi's
Pico 2 board, which is fitted with a RP2350A and 4MB of flash.

Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>

Kconfig.zephyr

@@ -793,7 +793,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID
 	default "0xada52840" if SOC_NRF52840_QIAA
 	default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
 	default "0x2abc77ec" if SOC_SERIES_LPC55XXX
-	default "0xe48bff56" if SOC_SERIES_RP2XXX
+	default "0xe48bff56" if SOC_SERIES_RP2040
 	default "0x68ed2b88" if SOC_SERIES_SAMD21
 	default "0x55114460" if SOC_SERIES_SAMD51
 	default "0x647824b6" if SOC_SERIES_STM32F0X

drivers/hwinfo/Kconfig

@@ -130,7 +130,7 @@ config HWINFO_IMXRT
 config HWINFO_RPI_PICO
 	bool "Raspberry Pi Pico hwinfo driver"
 	default y
-	depends on SOC_SERIES_RP2XXX
+	depends on SOC_FAMILY_RPI_PICO
 	select HWINFO_HAS_DRIVER
 	select PICOSDK_USE_FLASH
 	help

dts/arm/raspberrypi/rpi_pico/m33.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+
+/* Model in the device tree a Cortex-M33 core being 'plugged' into each
+ * 'socket' within the SoC. Within the datasheet these are core 0 and core 1.
+ */
+&cpu0 {
+	compatible = "arm,cortex-m33";
+};
+
+&cpu1 {
+	compatible = "arm,cortex-m33";
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/arm/raspberrypi/rpi_pico/rp2350.dtsi

@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/regulator/rpi_pico.h>
+#include <zephyr/dt-bindings/reset/rp2350_reset.h>
+#include <mem.h>
+
+#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY
+#define RPI_PICO_DEFAULT_IRQ_PRIORITY 7
+#endif
+
+/ {
+	aliases {
+		die-temp0 = &die_temp;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* There are two CPU sockets in the RP2350-series SoCs.
+		 * Represent the sockets in the device tree as these two
+		 * partially-defined CPU instances. Use a separate DTSI file to
+		 * define what kind of CPU cores they are.
+		 */
+		cpu0: cpu@0 {
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			reg = <1>;
+		};
+	};
+
+	clocks {
+		clk_gpout0: clk-gpout0 {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_sys>;
+			clock-names = "pll_sys";
+			clock-frequency = <150000000>;
+			#clock-cells = <0>;
+			#address-cells = <0>;
+		};
+
+		clk_gpout1: clk-gpout1 {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_sys>;
+			clock-names = "pll_sys";
+			clock-frequency = <150000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_gpout2: clk-gpout2 {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_sys>;
+			clock-names = "pll_sys";
+			clock-frequency = <150000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_gpout3: clk-gpout3 {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_sys>;
+			clock-names = "pll_sys";
+			clock-frequency = <150000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_hstx: clk-hstx {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_sys>;
+			clock-names = "pll_sys";
+			clock-frequency = <150000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_ref: clk-ref {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&xosc>;
+			clock-names = "xosc";
+			clock-frequency = <12000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_sys: clk-sys {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_sys>;
+			clock-names = "pll_sys";
+			clock-frequency = <150000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_usb: clk-usb {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_usb>;
+			clock-names = "pll_usb";
+			clock-frequency = <48000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_adc: clk-adc {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&pll_usb>;
+			clock-names = "pll_usb";
+			clock-frequency = <48000000>;
+			#clock-cells = <0>;
+		};
+
+		clk_peri: clk-peri {
+			compatible = "raspberrypi,pico-clock";
+			clocks = <&clk_sys>;
+			clock-names = "clk_sys";
+			clock-frequency = <150000000>;
+			#clock-cells = <0>;
+		};
+
+		pll_sys: pll-sys {
+			compatible = "raspberrypi,pico-pll";
+			clocks = <&xosc>;
+			clock-names = "xosc";
+			clock-div= <1>;
+			fb-div= <125>;
+			post-div1 = <5>;
+			post-div2 = <2>;
+			#clock-cells = <0>;
+		};
+
+		pll_usb: pll-usb {
+			compatible = "raspberrypi,pico-pll";
+			clocks = <&xosc>;
+			clock-names = "xosc";
+			clock-div= <1>;
+			fb-div = <100>;
+			post-div1 = <5>;
+			post-div2 = <5>;
+			#clock-cells = <0>;
+		};
+
+		rosc: rosc {
+			compatible = "raspberrypi,pico-rosc";
+			clock-frequency = <6500000>;
+			range = <RPI_PICO_ROSC_RANGE_RESET>;
+			stage-drive-strength = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+			clock-div = <16>;
+			phase = <0>;
+			#clock-cells = <0>;
+		};
+
+		rosc_ph: rosc-ph {
+			compatible = "raspberrypi,pico-clock";
+			clock-frequency = <6500000>;
+			clocks = <&rosc>;
+			clock-names = "rosc";
+			#clock-cells = <0>;
+		};
+
+		xosc: xosc {
+			compatible = "raspberrypi,pico-xosc";
+			clock-frequency = <12000000>;
+			#clock-cells = <0>;
+		};
+
+		gpin0: gpin0 {
+			compatible = "raspberrypi,pico-clock";
+			status = "disabled";
+			clock-frequency = <0>;
+			#clock-cells = <0>;
+		};
+
+		gpin1: gpin1 {
+			compatible = "raspberrypi,pico-clock";
+			status = "disabled";
+			clock-frequency = <0>;
+			#clock-cells = <0>;
+		};
+	};
+
+	soc {
+		compatible = "raspberrypi,rp2350", "simple-bus";
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(520)>;
+		};
+
+		qmi: flash-controller@400d0000 {
+			compatible = "raspberrypi,pico-flash-controller";
+			reg = <0x400d0000 0xfc>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@10000000 {
+				compatible = "soc-nv-flash";
+				write-block-size = <1>;
+				erase-block-size = <DT_SIZE_K(4)>;
+			};
+			status = "disabled";
+		};
+
+		reset: reset-controller@40020000 {
+			compatible = "raspberrypi,pico-reset";
+			reg = <0x40020000 DT_SIZE_K(4)>;
+			reg-width = <4>;
+			active-low = <0>;
+			#reset-cells = <1>;
+		};
+
+		clocks: clock-controller@40010000 {
+			compatible = "raspberrypi,pico-clock-controller";
+			reg = <0x40010000 DT_SIZE_K(4)
+			       0x40048000 DT_SIZE_K(4)
+			       0x40050000 DT_SIZE_K(4)
+			       0x40058000 DT_SIZE_K(4)
+			       0x400e8000 DT_SIZE_K(4)>;
+			reg-names = "clocks", "xosc", "pll_sys", "pll_usb", "rosc";
+			#clock-cells = <1>;
+			status = "okay";
+			clocks = <&clk_gpout0>, <&clk_gpout1>, <&clk_gpout2>, <&clk_gpout3>,
+				 <&clk_hstx>, <&clk_ref>, <&clk_sys>, <&clk_peri>,
+				 <&clk_usb>, <&clk_adc>,
+				 <&pll_sys>, <&pll_usb>, <&xosc>, <&rosc>, <&rosc_ph>,
+				 <&gpin0>, <&gpin1>;
+			clock-names = "clk_gpout0", "clk_gpout1", "clk_gpout2", "clk_gpout3",
+				 "clk_hstx", "clk_ref", "clk_sys", "clk_peri",
+				 "clk_usb", "clk_adc",
+				 "pll_sys", "pll_usb", "xosc", "rosc", "rosc_ph",
+				 "gpin0", "gpin1";
+		};
+
+		gpio0: gpio@40028000 {
+			compatible = "raspberrypi,pico-gpio";
+			reg = <0x40028000 DT_SIZE_K(4)>;
+			interrupts = <21 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		uart0: uart@40070000 {
+			compatible = "raspberrypi,pico-uart", "arm,pl011";
+			reg = <0x40070000 DT_SIZE_K(4)>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>;
+			resets = <&reset RPI_PICO_RESETS_RESET_UART0>;
+			interrupts = <33 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "uart0";
+			status = "disabled";
+		};
+
+		uart1: uart@40078000 {
+			compatible = "raspberrypi,pico-uart", "arm,pl011";
+			reg = <0x40078000 DT_SIZE_K(4)>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>;
+			resets = <&reset RPI_PICO_RESETS_RESET_UART1>;
+			interrupts = <34 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "uart1";
+			status = "disabled";
+		};
+
+		spi0: spi@40080000 {
+			compatible = "raspberrypi,pico-spi", "arm,pl022";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40080000 DT_SIZE_K(4)>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>;
+			resets = <&reset RPI_PICO_RESETS_RESET_SPI0>;
+			interrupts = <31 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "spi0";
+			status = "disabled";
+		};
+
+		spi1: spi@40088000 {
+			compatible = "raspberrypi,pico-spi", "arm,pl022";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40088000 DT_SIZE_K(4)>;
+			resets = <&reset RPI_PICO_RESETS_RESET_SPI1>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>;
+			interrupts = <32 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "spi1";
+			status = "disabled";
+		};
+
+		i2c0: i2c@40090000 {
+			compatible = "raspberrypi,pico-i2c", "snps,designware-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40090000 DT_SIZE_K(4)>;
+			resets = <&reset RPI_PICO_RESETS_RESET_I2C0>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>;
+			interrupts = <36 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "i2c0";
+			status = "disabled";
+		};
+
+		i2c1: i2c@40098000 {
+			compatible = "raspberrypi,pico-i2c", "snps,designware-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40098000 DT_SIZE_K(4)>;
+			resets = <&reset RPI_PICO_RESETS_RESET_I2C1>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>;
+			interrupts = <37 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "i2c1";
+			status = "disabled";
+		};
+
+		adc: adc@400a0000 {
+			compatible = "raspberrypi,pico-adc";
+			reg = <0x400a0000 DT_SIZE_K(4)>;
+			resets = <&reset RPI_PICO_RESETS_RESET_ADC>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_ADC>;
+			interrupts = <35 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "adc0";
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		pwm: pwm@400a8000 {
+			compatible = "raspberrypi,pico-pwm";
+			reg = <0x400a8000 DT_SIZE_K(4)>;
+			resets = <&reset RPI_PICO_RESETS_RESET_PWM>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>;
+			interrupts = <8 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
+					<9 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "PWM_IRQ_WRAP_0",
+						"PWM_IRQ_WRAP_1";
+			status = "disabled";
+			#pwm-cells = <3>;
+		};
+
+		timer0: timer@400b0000 {
+			compatible = "raspberrypi,pico-timer";
+			reg = <0x400b0000 DT_SIZE_K(4)>;
+			resets = <&reset RPI_PICO_RESETS_RESET_TIMER0>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_REF>;
+			interrupts = <0 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
+				     <1 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
+				     <2 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
+				     <3 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "TIMER0_IRQ_0",
+					  "TIMER0_IRQ_1",
+					  "TIMER0_IRQ_2",
+					  "TIMER0_IRQ_3";
+			status = "disabled";
+		};
+
+		timer1: timer@400b8000 {
+			compatible = "raspberrypi,pico-timer";
+			reg = <0x400b8000 DT_SIZE_K(4)>;
+			resets = <&reset RPI_PICO_RESETS_RESET_TIMER1>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_REF>;
+			interrupts = <4 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
+				     <5 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
+				     <6 RPI_PICO_DEFAULT_IRQ_PRIORITY>,
+				     <7 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "TIMER1_IRQ_0",
+					  "TIMER1_IRQ_1",
+					  "TIMER1_IRQ_2",
+					  "TIMER1_IRQ_3";
+			status = "disabled";
+		};
+
+		wdt0: watchdog@400d8000 {
+			compatible = "raspberrypi,pico-watchdog";
+			reg = <0x400d8000 DT_SIZE_K(4)>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_REF>;
+			status = "disabled";
+		};
+
+		usbd: usbd@50100000 {
+			compatible = "raspberrypi,pico-usbd";
+			reg = <0x50100000 0x10000>;
+			resets = <&reset RPI_PICO_RESETS_RESET_USBCTRL>;
+			clocks = <&clocks RPI_PICO_CLKID_CLK_USB>;
+			interrupts = <14 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
+			interrupt-names = "usbctrl";
+			num-bidir-endpoints = <16>;
+			status = "disabled";
+		};
+
+	};
+
+	pinctrl: pin-controller {
+		compatible = "raspberrypi,pico-pinctrl";
+		status = "okay";
+	};
+
+	die_temp: dietemp {
+		compatible = "raspberrypi,pico-temp";
+		status = "disabled";
+	};
+};

dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi

@@ -0,0 +1,9 @@
+#include <arm/raspberrypi/rpi_pico/rp2350.dtsi>
+
+&gpio0 {
+	ngpios = <30>;
+};
+
+&die_temp {
+	io-channels = <&adc 4>;
+};

include/zephyr/dt-bindings/reset/rp2350_reset.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_
+
+#define RPI_PICO_RESETS_RESET_ADC        0
+#define RPI_PICO_RESETS_RESET_BUSCTRL    1
+#define RPI_PICO_RESETS_RESET_DMA        2
+#define RPI_PICO_RESETS_RESET_HSTX       3
+#define RPI_PICO_RESETS_RESET_I2C0       4
+#define RPI_PICO_RESETS_RESET_I2C1       5
+#define RPI_PICO_RESETS_RESET_IO_BANK0   6
+#define RPI_PICO_RESETS_RESET_IO_QSPI    7
+#define RPI_PICO_RESETS_RESET_JTAG       8
+#define RPI_PICO_RESETS_RESET_PADS_BANK0 9
+#define RPI_PICO_RESETS_RESET_PADS_QSPI  10
+#define RPI_PICO_RESETS_RESET_PIO0       11
+#define RPI_PICO_RESETS_RESET_PIO1       12
+#define RPI_PICO_RESETS_RESET_PIO2       13
+#define RPI_PICO_RESETS_RESET_PLL_SYS    14
+#define RPI_PICO_RESETS_RESET_PLL_USB    15
+#define RPI_PICO_RESETS_RESET_PWM        16
+#define RPI_PICO_RESETS_RESET_SHA256     17
+#define RPI_PICO_RESETS_RESET_SPI0       18
+#define RPI_PICO_RESETS_RESET_SPI1       19
+#define RPI_PICO_RESETS_RESET_SYSCFG     20
+#define RPI_PICO_RESETS_RESET_SYSINFO    21
+#define RPI_PICO_RESETS_RESET_TBMAN      22
+#define RPI_PICO_RESETS_RESET_TIMER0     23
+#define RPI_PICO_RESETS_RESET_TIMER1     24
+#define RPI_PICO_RESETS_RESET_TRNG       25
+#define RPI_PICO_RESETS_RESET_UART0      26
+#define RPI_PICO_RESETS_RESET_UART1      27
+#define RPI_PICO_RESETS_RESET_USBCTRL    28
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ */

modules/hal_rpi_pico/CMakeLists.txt

@@ -6,9 +6,9 @@ if(CONFIG_HAS_RPI_PICO)
   zephyr_library()
 
   set(rp2_common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2_common)
-  set(rp2040_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2040)
+  set(rp2xxx_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/${CONFIG_SOC_SERIES})
   set(common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/common)
-  set(boot_stage_dir ${rp2040_dir}/boot_stage2)
+  set(boot_stage_dir ${rp2xxx_dir}/boot_stage2)
 
   # The Second Stage Bootloader is only linked to the app that resides
   # at 0x100. Therefore, only if the app's offset is 0x100, the second
@@ -46,7 +46,11 @@ if(CONFIG_HAS_RPI_PICO)
       zephyr_library_sources(${rp2_bootloader_asm})
   endif()
 
-  zephyr_compile_definitions(PICO_RP2040)
+  if(CONFIG_SOC_SERIES_RP2040)
+    zephyr_compile_definitions(PICO_RP2040)
+  elseif(CONFIG_SOC_SERIES_RP2350)
+    zephyr_compile_definitions(PICO_RP2350)
+  endif()
 
   # Pico sources and headers necessary for every build.
   # These contain definitions and implementation used mostly for
@@ -57,8 +61,9 @@ if(CONFIG_HAS_RPI_PICO)
     ${rp2_common_dir}/hardware_pll/pll.c
     ${rp2_common_dir}/hardware_xosc/xosc.c
     ${rp2_common_dir}/hardware_watchdog/watchdog.c
+    ${rp2_common_dir}/hardware_sync_spin_lock/sync_spin_lock.c
     ${rp2_common_dir}/pico_bootrom/bootrom.c
-    ${rp2040_dir}/pico_platform/platform.c
+    ${rp2xxx_dir}/pico_platform/platform.c
   )
 
   zephyr_include_directories(
@@ -81,9 +86,9 @@ if(CONFIG_HAS_RPI_PICO)
     ${rp2_common_dir}/pico_platform_panic/include
     ${common_dir}/boot_picoboot_headers/include
     ${common_dir}/boot_picobin_headers/include
-    ${rp2040_dir}/hardware_regs/include
-    ${rp2040_dir}/hardware_structs/include
-    ${rp2040_dir}/pico_platform/include
+    ${rp2xxx_dir}/hardware_regs/include
+    ${rp2xxx_dir}/hardware_structs/include
+    ${rp2xxx_dir}/pico_platform/include
     ${CMAKE_CURRENT_LIST_DIR}
   )
 
@@ -145,4 +150,10 @@ if(CONFIG_HAS_RPI_PICO)
   zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_CLAIM
           ${common_dir}/hardware_claim/include)
 
+  zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_RP2350
+          ${rp2_common_dir}/pico_runtime_init/runtime_init.c)
+  zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RP2350
+          ${rp2_common_dir}/pico_runtime/include
+          ${rp2_common_dir}/pico_runtime_init/include)
+
 endif()

soc/raspberrypi/rpi_pico/CMakeLists.txt

@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
+add_subdirectory(common)
 add_subdirectory(${SOC_SERIES})

soc/raspberrypi/rpi_pico/common/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Andrew Featherstone
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+	soc.c
+)

soc/raspberrypi/rpi_pico/common/soc.c

@@ -1,28 +1,23 @@
 /*
  * Copyright (c) 2021 Nordic Semiconductor ASA
  * Copyright (c) 2021 Yonatan Schachter
+ * Copyright (c) 2024 Andrew Featherstone
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
  * @file
- * @brief System/hardware module for Raspberry Pi RP2040 family processor
+ * @brief System/hardware module for Raspberry Pi RP2xxx family of processors
  *
  * This module provides routines to initialize and support board-level hardware
- * for the Raspberry Pi RP2040 family processor.
+ * for the Raspberry Pi RP2xxx family of processors (RP2040, RP235x).
  */
 
 #include <stdio.h>
 
-#include <zephyr/kernel.h>
-#include <zephyr/init.h>
-#include <zephyr/logging/log.h>
 #include <zephyr/fatal.h>
-
-#include <hardware/regs/resets.h>
-#include <hardware/clocks.h>
-#include <hardware/resets.h>
+#include <zephyr/logging/log.h>
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 

soc/raspberrypi/rpi_pico/common/soc.h

@@ -9,9 +9,9 @@
  * @file SoC configuration macros for the Raspberry Pi RP2040 family processors
  */
 
-#ifndef _RPI_PICO_RP2040_SOC_H_
-#define _RPI_PICO_RP2040_SOC_H_
+#ifndef _RPI_PICO_COMMON_SOC_H_
+#define _RPI_PICO_COMMON_SOC_H_
 
 #include <cmsis_core_m_defaults.h>
 
-#endif /* _RPI_PICO_RP2040_SOC_H_ */
+#endif /* _RPI_PICO_COMMON_SOC_H_ */

soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 Yonatan Schachter
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/raspberrypi/rpi_pico/rp2040/Kconfig

@@ -4,7 +4,7 @@
 # Copyright (c) 2021 Yonatan Schachter
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_RP2XXX
+config SOC_SERIES_RP2040
 	select ARM
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
@@ -14,7 +14,9 @@ config SOC_SERIES_RP2XXX
 	select XIP
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 	help
-	  Enable support for Raspberry Pi RP2 MCU series
+	  Enable support for Raspberry Pi RP2040 MCU series
+
+if SOC_SERIES_RP2040
 
 config RP2_REQUIRES_SECOND_STAGE_BOOT
 	bool
@@ -51,3 +53,5 @@ config RP2_FLASH_AT25SF128A
 	help
 	  Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected
 	  by the board definition, not the user.
+
+endif

soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig

@@ -1,14 +1,14 @@
-# Raspberry Pi RP2XXX MCU line
+# Raspberry Pi RP2040 MCU line
 
 # Copyright (c) 2021 Nordic Semiconductor ASA
 # Copyright (c) 2021 Yonatan Schachter
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_RP2XXX
+if SOC_SERIES_RP2040
 
 rsource "Kconfig.defconfig.rp2*"
 
 config NUM_IRQS
 	default 26
 
-endif # SOC_SERIES_RP2XXX
+endif # SOC_SERIES_RP2040

soc/raspberrypi/rpi_pico/rp2040/Kconfig.soc

@@ -1,19 +1,19 @@
-# Raspberry Pi RP2XXX MCU line
+# Raspberry Pi RP2040 MCU line
 
 # Copyright (c) 2021 Nordic Semiconductor ASA
 # Copyright (c) 2021 Yonatan Schachter
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_RP2040
-	bool
-	select SOC_SERIES_RP2XXX
+config SOC_SERIES
+	default "rp2040" if SOC_SERIES_RP2040
 
-config SOC_SERIES_RP2XXX
+config SOC_SERIES_RP2040
 	bool
 	select SOC_FAMILY_RPI_PICO
 
-config SOC_SERIES
-	default "rp2xxx" if SOC_SERIES_RP2XXX
+config SOC_RP2040
+	bool
+	select SOC_SERIES_RP2040
 
 config SOC
 	default "rp2040" if SOC_RP2040

soc/raspberrypi/rpi_pico/rp2350/Kconfig

@@ -0,0 +1,29 @@
+# Raspberry Pi RP235XX MCU line
+
+# Copyright (c) 2024 Andrew Featherstone
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RP2350
+	select HAS_RPI_PICO
+	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+	select SOC_RESET_HOOK
+	select XIP
+
+config SOC_RP2350A_M33
+	select ARM
+	select ARM_TRUSTZONE_M
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
+
+config RP2_REQUIRES_IMAGE_DEFINITION_BLOCK
+	bool
+	default y
+	# Currently the IDF only supports using the Cortex-M33 cores. Enforce
+	# this at build configuration time.
+	depends on SOC_SERIES_RP2350 && CPU_CORTEX_M33
+	help
+	  Include an Image Definition Block (IMAGE_DEF) to enable the bootroom in
+	  RP23XX devices to consider this a valid image in flash.

soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# Raspberry Pi RP2350 MCU line
+
+# Copyright (c) 2024 Andrew Featherstone
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RP2350
+
+config NUM_IRQS
+	default 52
+
+endif # SOC_SERIES_RP2350

soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc

@@ -0,0 +1,24 @@
+# Raspberry Pi RP2350 MCU line
+
+# Copyright (c) 2024 Andrew Featherstone
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RP2350
+	bool
+	select SOC_FAMILY_RPI_PICO
+
+config SOC_SERIES
+	default "rp2350" if SOC_SERIES_RP2350
+
+config SOC_RP2350A
+	bool
+	select SOC_SERIES_RP2350
+
+config SOC_RP2350A_M33
+	bool
+	select SOC_RP2350A
+	help
+	  Use the RP2350A with a Cortex-M33 core in both 'sockets'.
+
+config SOC
+	default "rp2350a" if SOC_RP2350A

soc/raspberrypi/rpi_pico/rp2350/linker.ld

@@ -0,0 +1,27 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+MEMORY
+{
+	IMAGE_DEF_FLASH (r) : ORIGIN = 0x10000000, LENGTH = 128
+}
+
+SECTIONS
+{
+	.image_def : {
+		LONG(0xffffded3) /* PICOBIN_BLOCK_MARKER_START */
+		LONG(0x10210142) /* IMAGE_DEF Item */
+		LONG(0x00000203) /* VECTOR_TABLE Item */
+		LONG(ABSOLUTE(_vector_start)) /* - Address of the vector table in flash */
+		LONG(0x000003ff) /* Last Item in Block */
+		LONG(0x00000000) /* End of block loop */
+		LONG(0xab123579) /* PICOBIN_BLOCK_MARKER_END */
+	} > IMAGE_DEF_FLASH
+}
+
+#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>

soc/raspberrypi/rpi_pico/rp2350/soc.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Raspberry Pi RP235xx MCUs
+ *
+ * This module provides routines to initialize and support board-level hardware
+ * for the Raspberry Pi RP235xx (RP2350A, RP2350B, RP2354A, RP2354B).
+ */
+
+#if CONFIG_SOC_RESET_HOOK
+#include <pico/runtime_init.h>
+
+
+void soc_reset_hook(void)
+{
+	runtime_init_per_core_enable_coprocessors();
+}
+
+#endif /* CONFIG_SOC_RESET_HOOK */

soc/raspberrypi/rpi_pico/soc.yml

@@ -0,0 +1,11 @@
+family:
+- name: rpi_pico
+  series:
+  - name: rp2040
+    socs:
+    - name: rp2040
+  - name: rp2350
+    socs:
+    - name: rp2350a
+      cpuclusters:
+      - name: m33

soc/raspberrypi/soc.yml

@@ -1,6 +0,0 @@
-family:
-- name: rpi_pico
-  series:
-  - name: rp2xxx
-    socs:
-    - name: rp2040