drivers: clock_control: silabs: Add clock control driver
Add clock control driver for Silicon Labs Series 2 and newer. Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit is contained in:
parent
46367ff15a
commit
bda8ae8c3f
23 changed files with 711 additions and 0 deletions
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@ -15,4 +15,5 @@ supported:
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- uart
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- i2c
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- spi
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- clock_control
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vendor: silabs
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@ -13,6 +13,7 @@ supported:
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- gpio
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- uart
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- watchdog
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- clock_control
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testing:
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ignore_tags:
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- pm
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@ -13,4 +13,5 @@ supported:
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- counter
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- gpio
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- uart
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- clock_control
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vendor: silabs
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@ -25,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clo
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SERIES clock_control_silabs_series.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_PLL clock_control_si32_pll.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_AHB clock_control_si32_ahb.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_APB clock_control_si32_apb.c)
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@ -98,4 +98,6 @@ source "drivers/clock_control/Kconfig.nrf_auxpll"
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source "drivers/clock_control/Kconfig.arm_scmi"
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source "drivers/clock_control/Kconfig.silabs"
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endif # CLOCK_CONTROL
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9
drivers/clock_control/Kconfig.silabs
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9
drivers/clock_control/Kconfig.silabs
Normal file
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@ -0,0 +1,9 @@
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_SILABS_SERIES
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bool "Silicon Labs Series 2+ clock control driver"
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default y
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depends on DT_HAS_SILABS_SERIES_CLOCK_ENABLED
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help
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Enable Silicon Labs Series 2+ Clock Management Unit clock control driver.
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127
drivers/clock_control/clock_control_silabs_series.c
Normal file
127
drivers/clock_control/clock_control_silabs_series.c
Normal file
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@ -0,0 +1,127 @@
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/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT silabs_series_clock
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/clock_control_silabs.h>
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#include <zephyr/sys/util.h>
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#include <soc.h>
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#include "sl_clock_manager.h"
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#include "sl_status.h"
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struct silabs_clock_control_config {
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CMU_TypeDef *cmu;
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};
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static enum clock_control_status silabs_clock_control_get_status(const struct device *dev,
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clock_control_subsys_t sys);
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static int silabs_clock_control_on(const struct device *dev, clock_control_subsys_t sys)
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{
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const struct silabs_clock_control_cmu_config *cfg = sys;
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sl_status_t status;
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if (silabs_clock_control_get_status(dev, sys) == CLOCK_CONTROL_STATUS_ON) {
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return -EALREADY;
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}
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status = sl_clock_manager_enable_bus_clock(&cfg->bus_clock);
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if (status != SL_STATUS_OK) {
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return -ENOTSUP;
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}
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return 0;
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}
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static int silabs_clock_control_off(const struct device *dev, clock_control_subsys_t sys)
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{
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const struct silabs_clock_control_cmu_config *cfg = sys;
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sl_status_t status;
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status = sl_clock_manager_disable_bus_clock(&cfg->bus_clock);
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if (status != SL_STATUS_OK) {
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return -ENOTSUP;
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}
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return 0;
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}
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static int silabs_clock_control_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct silabs_clock_control_cmu_config *cfg = sys;
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sl_status_t status;
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status = sl_clock_manager_get_clock_branch_frequency(cfg->branch, rate);
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if (status != SL_STATUS_OK) {
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return -ENOTSUP;
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}
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return 0;
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}
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static enum clock_control_status silabs_clock_control_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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const struct silabs_clock_control_cmu_config *cfg = sys;
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__maybe_unused const struct silabs_clock_control_config *reg = dev->config;
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uint32_t clock_status = 0;
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if (cfg->bus_clock == 0xFFFFFFFFUL) {
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return CLOCK_CONTROL_STATUS_UNKNOWN;
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}
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switch (FIELD_GET(CLOCK_REG_MASK, cfg->bus_clock)) {
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#if defined(_CMU_CLKEN0_MASK)
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case 0:
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clock_status = reg->cmu->CLKEN0;
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break;
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#endif
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#if defined(_CMU_CLKEN1_MASK)
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case 1:
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clock_status = reg->cmu->CLKEN1;
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break;
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#endif
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#if defined(_CMU_CLKEN2_MASK)
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case 2:
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clock_status = reg->cmu->CLKEN2;
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break;
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#endif
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default:
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__ASSERT(false, "Invalid bus clock: %x\n", cfg->bus_clock);
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break;
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}
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if (clock_status & BIT(FIELD_GET(CLOCK_BIT_MASK, cfg->bus_clock))) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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}
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static int silabs_clock_control_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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sl_clock_manager_runtime_init();
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return 0;
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}
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static const struct clock_control_driver_api silabs_clock_control_api = {
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.on = silabs_clock_control_on,
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.off = silabs_clock_control_off,
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.get_rate = silabs_clock_control_get_rate,
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.get_status = silabs_clock_control_get_status,
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};
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static const struct silabs_clock_control_config silabs_clock_control_config = {
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.cmu = (CMU_TypeDef *)DT_INST_REG_ADDR(0),
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};
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DEVICE_DT_INST_DEFINE(0, silabs_clock_control_init, NULL, NULL, &silabs_clock_control_config,
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &silabs_clock_control_api);
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@ -5,8 +5,13 @@
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*/
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#include "efr32bg2x.dtsi"
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#include <dt-bindings/clock/silabs/xg22-clock.h>
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#include <mem.h>
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&cmu {
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interrupts = <46 0>;
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};
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&msc {
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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@ -22,28 +27,35 @@
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&gpio {
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interrupts = <10 2 18 2>;
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clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
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};
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&i2c0 {
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interrupts = <27 0>;
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clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
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};
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&i2c1 {
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interrupts = <28 0>;
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clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
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};
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&usart0 {
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interrupts = <13 0>, <14 0>;
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clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
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};
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&usart1 {
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interrupts = <15 0>, <16 0>;
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clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
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};
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&burtc0 {
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interrupts = <18 0>;
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clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
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};
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&stimer0 {
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interrupts = <12 0>;
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clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
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};
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*/
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#include "efr32bg2x.dtsi"
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#include <dt-bindings/clock/silabs/xg27-clock.h>
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#include <mem.h>
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&cmu {
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interrupts = <52 0>;
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};
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&msc {
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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&gpio {
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interrupts = <30 2 31 2>;
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clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
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};
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&i2c0 {
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interrupts = <32 0>;
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clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
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};
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&i2c1 {
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interrupts = <33 0>;
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clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
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};
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&usart0 {
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interrupts = <16 0>, <17 0>;
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clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
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};
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&usart1 {
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interrupts = <18 0>, <19 0>;
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clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
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};
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&burtc0 {
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interrupts = <23 0>;
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clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
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};
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&stimer0 {
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interrupts = <15 0>;
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clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
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};
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&adc0 {
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interrupts = <54 0>;
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clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
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};
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@ -93,6 +93,14 @@
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};
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soc {
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cmu: clock@50008000 {
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compatible = "silabs,series-clock";
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reg = <0x50008000 0x4000>;
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interrupt-names = "cmu";
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status = "okay";
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#clock-cells = <2>;
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};
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msc: flash-controller@50030000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x50030000 0xC69>;
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@ -8,6 +8,7 @@
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <dt-bindings/clock/silabs/xg21-clock.h>
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#include "gpio_gecko.h"
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/ {
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};
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soc {
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cmu: clock@50008000 {
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compatible = "silabs,series-clock";
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reg = <0x50008000 0x4000>;
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interrupts = <48 0>;
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interrupt-names = "cmu";
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status = "okay";
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#clock-cells = <2>;
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};
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msc: flash-controller@50030000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x50030000 0x31a4>;
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interrupts = <11 0>, <12 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
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status = "disabled";
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};
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interrupts = <13 0>, <14 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <1>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
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status = "disabled";
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};
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interrupts = <15 0>, <16 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <2>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
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status = "disabled";
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};
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#size-cells = <0>;
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reg = <0x5a010000 0x400>;
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interrupts = <27 0>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_LSPCLK>;
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status = "disabled";
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};
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#size-cells = <0>;
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reg = <0x50068000 0x400>;
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interrupts = <28 0>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
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status = "disabled";
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};
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interrupts = <10 0>;
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clock-frequency = <32768>;
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prescaler = <1>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_RTCCCLK>;
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status = "disabled";
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};
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reg = <0x5003c300 0x3c00>;
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interrupts = <26 2>, <25 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
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ranges;
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#address-cells = <1>;
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reg = <0x5a018000 0x2C>;
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peripheral-id = <0>;
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interrupts = <43 0>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG0CLK>;
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status = "disabled";
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};
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reg = <0x5a01c000 0x2C>;
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peripheral-id = <1>;
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interrupts = <44 0>;
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clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG1CLK>;
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status = "disabled";
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};
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@ -10,6 +10,7 @@
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/pinctrl/gecko-pinctrl.h>
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#include <dt-bindings/adc/adc.h>
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#include <dt-bindings/clock/silabs/xg24-clock.h>
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#include <freq.h>
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/ {
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};
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soc {
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cmu: clock@50008000 {
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compatible = "silabs,series-clock";
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reg = <0x50008000 0x4000>;
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interrupts = <47 0>;
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interrupt-names = "cmu";
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status = "okay";
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#clock-cells = <2>;
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};
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msc: flash-controller@50030000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x50030000 0x3148>;
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interrupts = <9 0>, <10 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
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status = "disabled";
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};
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compatible = "silabs,gecko-burtc";
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reg = <0x50064000 0x3034>;
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interrupts = <17 0>;
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clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
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status = "disabled";
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};
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#size-cells = <0>;
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reg = <0x5b000000 0x3044>;
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interrupts = <27 0>;
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clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
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status = "disabled";
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};
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interrupts = <67 0>;
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clock-frequency = <32768>;
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prescaler = <1>;
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clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>;
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status = "disabled";
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};
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reg = <0x5003c000 0x4000>;
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interrupts = <26 2>, <25 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
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ranges;
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#address-cells = <1>;
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reg = <0x5b004000 0x2C>;
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peripheral-id = <0>;
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interrupts = <42 0>;
|
||||
clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -202,6 +218,7 @@
|
|||
reg = <0x5b008000 0x2C>;
|
||||
peripheral-id = <1>;
|
||||
interrupts = <43 0>;
|
||||
clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -209,6 +226,7 @@
|
|||
compatible = "silabs,gecko-iadc";
|
||||
reg = <0x59004000 0x4000>;
|
||||
interrupts = <49 0>;
|
||||
clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
|
19
dts/bindings/clock/silabs,series-clock.yaml
Normal file
19
dts/bindings/clock/silabs,series-clock.yaml
Normal file
|
@ -0,0 +1,19 @@
|
|||
# Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Silicon Labs Series 2+ clock control node
|
||||
|
||||
compatible: "silabs,series-clock"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
clock-cells:
|
||||
- enable
|
||||
- branch
|
39
include/zephyr/drivers/clock_control/clock_control_silabs.h
Normal file
39
include/zephyr/drivers/clock_control/clock_control_silabs.h
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_
|
||||
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_
|
||||
|
||||
#include <zephyr/drivers/clock_control.h>
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_EFR32MG21)
|
||||
#include <zephyr/dt-bindings/clock/silabs/xg21-clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_EFR32BG22)
|
||||
#include <zephyr/dt-bindings/clock/silabs/xg22-clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_EFR32MG24)
|
||||
#include <zephyr/dt-bindings/clock/silabs/xg24-clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_EFR32BG27)
|
||||
#include <zephyr/dt-bindings/clock/silabs/xg27-clock.h>
|
||||
#endif
|
||||
|
||||
struct silabs_clock_control_cmu_config {
|
||||
uint32_t bus_clock;
|
||||
uint8_t branch;
|
||||
};
|
||||
|
||||
#define SILABS_DT_CLOCK_CFG(node_id) \
|
||||
{ \
|
||||
.bus_clock = DT_CLOCKS_CELL(node_id, enable), \
|
||||
.branch = DT_CLOCKS_CELL(node_id, branch), \
|
||||
}
|
||||
|
||||
#define SILABS_DT_INST_CLOCK_CFG(inst) \
|
||||
{ \
|
||||
.bus_clock = DT_INST_CLOCKS_CELL(inst, enable), \
|
||||
.branch = DT_INST_CLOCKS_CELL(inst, branch), \
|
||||
}
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ */
|
54
include/zephyr/dt-bindings/clock/silabs/common-clock.h
Normal file
54
include/zephyr/dt-bindings/clock/silabs/common-clock.h
Normal file
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_
|
||||
|
||||
/*
|
||||
* DT macros for clock branches.
|
||||
* Must stay in sync with the enum sl_clock_branch_t in the Silicon Labs HAL to be
|
||||
* interpreted correctly by the clock control driver.
|
||||
*/
|
||||
#define CLOCK_BRANCH_SYSCLK 0
|
||||
#define CLOCK_BRANCH_HCLK 1
|
||||
#define CLOCK_BRANCH_HCLKRADIO 2
|
||||
#define CLOCK_BRANCH_PCLK 3
|
||||
#define CLOCK_BRANCH_LSPCLK 4
|
||||
#define CLOCK_BRANCH_TRACECLK 5
|
||||
#define CLOCK_BRANCH_ADCCLK 6
|
||||
#define CLOCK_BRANCH_EXPORTCLK 7
|
||||
#define CLOCK_BRANCH_EM01GRPACLK 8
|
||||
#define CLOCK_BRANCH_EM01GRPBCLK 9
|
||||
#define CLOCK_BRANCH_EM01GRPCCLK 10
|
||||
#define CLOCK_BRANCH_EM01GRPDCLK 11
|
||||
#define CLOCK_BRANCH_EM23GRPACLK 12
|
||||
#define CLOCK_BRANCH_EM4GRPACLK 13
|
||||
#define CLOCK_BRANCH_QSPISYSCLK 14
|
||||
#define CLOCK_BRANCH_IADCCLK 15
|
||||
#define CLOCK_BRANCH_WDOG0CLK 16
|
||||
#define CLOCK_BRANCH_WDOG1CLK 17
|
||||
#define CLOCK_BRANCH_RTCCCLK 18
|
||||
#define CLOCK_BRANCH_SYSRTCCLK 19
|
||||
#define CLOCK_BRANCH_EUART0CLK 20
|
||||
#define CLOCK_BRANCH_EUSART0CLK 21
|
||||
#define CLOCK_BRANCH_DPLLREFCLK 22
|
||||
#define CLOCK_BRANCH_I2C0CLK 23
|
||||
#define CLOCK_BRANCH_LCDCLK 24
|
||||
#define CLOCK_BRANCH_PIXELRZCLK 25
|
||||
#define CLOCK_BRANCH_PCNT0CLK 26
|
||||
#define CLOCK_BRANCH_PRORTCCLK 27
|
||||
#define CLOCK_BRANCH_SYSTICKCLK 28
|
||||
#define CLOCK_BRANCH_LESENSEHFCLK 29
|
||||
#define CLOCK_BRANCH_VDAC0CLK 30
|
||||
#define CLOCK_BRANCH_VDAC1CLK 31
|
||||
#define CLOCK_BRANCH_USB0CLK 32
|
||||
#define CLOCK_BRANCH_FLPLLREFCLK 33
|
||||
#define CLOCK_BRANCH_INVALID 34
|
||||
|
||||
#define CLOCK_BIT_MASK 0x03FUL
|
||||
#define CLOCK_REG_MASK 0x1C0UL
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ */
|
26
include/zephyr/dt-bindings/clock/silabs/xg21-clock.h
Normal file
26
include/zephyr/dt-bindings/clock/silabs/xg21-clock.h
Normal file
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
|
||||
* Do not manually edit.
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_
|
||||
|
||||
#include <zephyr/dt-bindings/dt-util.h>
|
||||
#include "common-clock.h"
|
||||
|
||||
/*
|
||||
* DT macros for clock tree nodes.
|
||||
* Defined as:
|
||||
* 0..5 - Bit within CLKEN register
|
||||
* 6..8 - CLKEN register number
|
||||
* Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
|
||||
* interpreted correctly by the clock control driver.
|
||||
*/
|
||||
#define CLOCK_AUTO 0xFFFFFFFFUL
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ */
|
76
include/zephyr/dt-bindings/clock/silabs/xg22-clock.h
Normal file
76
include/zephyr/dt-bindings/clock/silabs/xg22-clock.h
Normal file
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
|
||||
* Do not manually edit.
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_
|
||||
|
||||
#include <zephyr/dt-bindings/dt-util.h>
|
||||
#include "common-clock.h"
|
||||
|
||||
/*
|
||||
* DT macros for clock tree nodes.
|
||||
* Defined as:
|
||||
* 0..5 - Bit within CLKEN register
|
||||
* 6..8 - CLKEN register number
|
||||
* Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
|
||||
* interpreted correctly by the clock control driver.
|
||||
*/
|
||||
#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
|
||||
#define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
|
||||
#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_EUART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24))
|
||||
#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26))
|
||||
#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25))
|
||||
#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
|
||||
#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30))
|
||||
#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ */
|
86
include/zephyr/dt-bindings/clock/silabs/xg23-clock.h
Normal file
86
include/zephyr/dt-bindings/clock/silabs/xg23-clock.h
Normal file
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
|
||||
* Do not manually edit.
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_
|
||||
|
||||
#include <zephyr/dt-bindings/dt-util.h>
|
||||
#include "common-clock.h"
|
||||
|
||||
/*
|
||||
* DT macros for clock tree nodes.
|
||||
* Defined as:
|
||||
* 0..5 - Bit within CLKEN register
|
||||
* 6..8 - CLKEN register number
|
||||
* Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
|
||||
* interpreted correctly by the clock control driver.
|
||||
*/
|
||||
#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
|
||||
#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
|
||||
#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27))
|
||||
#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_EUSART2 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 24))
|
||||
#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26))
|
||||
#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
#define CLOCK_LCD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_LESENSE (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25))
|
||||
#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
|
||||
#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25))
|
||||
#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26))
|
||||
#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30))
|
||||
#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24))
|
||||
#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_ */
|
85
include/zephyr/dt-bindings/clock/silabs/xg24-clock.h
Normal file
85
include/zephyr/dt-bindings/clock/silabs/xg24-clock.h
Normal file
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
|
||||
* Do not manually edit.
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_
|
||||
|
||||
#include <zephyr/dt-bindings/dt-util.h>
|
||||
#include "common-clock.h"
|
||||
|
||||
/*
|
||||
* DT macros for clock tree nodes.
|
||||
* Defined as:
|
||||
* 0..5 - Bit within CLKEN register
|
||||
* 6..8 - CLKEN register number
|
||||
* Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
|
||||
* interpreted correctly by the clock control driver.
|
||||
*/
|
||||
#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
|
||||
#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
|
||||
#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27))
|
||||
#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26))
|
||||
#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15))
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||||
#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_MVP (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 30))
|
||||
#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
|
||||
#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25))
|
||||
#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26))
|
||||
#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30))
|
||||
#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24))
|
||||
#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_VDAC1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 29))
|
||||
#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_ */
|
78
include/zephyr/dt-bindings/clock/silabs/xg27-clock.h
Normal file
78
include/zephyr/dt-bindings/clock/silabs/xg27-clock.h
Normal file
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
|
||||
* Do not manually edit.
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_
|
||||
|
||||
#include <zephyr/dt-bindings/dt-util.h>
|
||||
#include "common-clock.h"
|
||||
|
||||
/*
|
||||
* DT macros for clock tree nodes.
|
||||
* Defined as:
|
||||
* 0..5 - Bit within CLKEN register
|
||||
* 6..8 - CLKEN register number
|
||||
* Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
|
||||
* interpreted correctly by the clock control driver.
|
||||
*/
|
||||
#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
|
||||
#define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
|
||||
#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_ETAMPDET (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26))
|
||||
#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25))
|
||||
#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
|
||||
#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30))
|
||||
#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ */
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "device_subsys.h"
|
||||
#include <zephyr/drivers/clock_control/clock_control_silabs.h>
|
||||
|
||||
struct silabs_clock_control_cmu_config i2c0_clock = {
|
||||
.bus_clock = CLOCK_I2C0,
|
||||
.branch = CLOCK_BRANCH_LSPCLK,
|
||||
};
|
||||
|
||||
struct silabs_clock_control_cmu_config wdog0_clock = {
|
||||
.bus_clock = CLOCK_WDOG0,
|
||||
.branch = CLOCK_BRANCH_WDOG0CLK,
|
||||
};
|
||||
|
||||
static const struct device_subsys_data subsys_data[] = {
|
||||
{.subsys = (void *)&i2c0_clock},
|
||||
{.subsys = (void *)&wdog0_clock},
|
||||
};
|
||||
|
||||
static const struct device_data devices[] = {
|
||||
{
|
||||
.dev = DEVICE_DT_GET_ONE(silabs_series_clock),
|
||||
.subsys_data = subsys_data,
|
||||
.subsys_cnt = ARRAY_SIZE(subsys_data)
|
||||
}
|
||||
};
|
|
@ -12,6 +12,8 @@ LOG_MODULE_REGISTER(test);
|
|||
#include "nrf_device_subsys.h"
|
||||
#elif DT_HAS_COMPAT_STATUS_OKAY(espressif_esp32_rtc)
|
||||
#include "esp32_device_subsys.h"
|
||||
#elif DT_HAS_COMPAT_STATUS_OKAY(silabs_series_clock)
|
||||
#include "silabs_device_subsys.h"
|
||||
#else
|
||||
#error "Unsupported board"
|
||||
#endif
|
||||
|
|
|
@ -10,6 +10,9 @@ tests:
|
|||
- esp32c3_devkitm
|
||||
- esp32s2_saola
|
||||
- esp32s3_devkitm/esp32s3/procpu
|
||||
- sltb010a@0
|
||||
- xg24_dk2601b
|
||||
- xg27_dk2602a
|
||||
drivers.clock.clock_control_nrf5:
|
||||
platform_allow:
|
||||
- nrf51dk/nrf51822
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue