boards: antmicro: add support for the Myra SiP Baseboard
Add support for the Antmicro's Myra SiP Baseboard. The board uses Antmicro's Myra SiP which integrates STM32G491XX MCU and its SoC configuration. Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com> Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Jakub Wasilewski
Benjamin Cabé
parent
1ce3898832
commit
3a8c954021
18 changed files with 717 additions and 0 deletions
10
boards/antmicro/index.rst
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10
boards/antmicro/index.rst
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.. _boards-antmicro:
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Antmicro
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###
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.. toctree::
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:maxdepth: 1
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:glob:
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**/*
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10
boards/antmicro/myra_sip_baseboard/Kconfig.defconfig
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boards/antmicro/myra_sip_baseboard/Kconfig.defconfig
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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_MYRA_SIP_BASEBOARD
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config SPI_STM32_INTERRUPT
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default y
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depends on SPI
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endif # BOARD_MYRA_SIP_BASEBOARD
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@ -0,0 +1,5 @@
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# Copyright (c) 2024 Antmicro
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MYRA_SIP_BASEBOARD
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select SOC_MYRA
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10
boards/antmicro/myra_sip_baseboard/board.cmake
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boards/antmicro/myra_sip_baseboard/board.cmake
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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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set(SUPPORTED_EMU_PLATFORMS renode)
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set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/myra_sip_baseboard.resc)
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set(RENODE_UART sysbus.lpuart1)
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board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_myra_sip_baseboard.cfg")
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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6
boards/antmicro/myra_sip_baseboard/board.yml
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6
boards/antmicro/myra_sip_baseboard/board.yml
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board:
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name: myra_sip_baseboard
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full_name: Myra SiP Baseboard
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vendor: antmicro
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socs:
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- name: myra
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Binary file not shown.
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After Width: | Height: | Size: 34 KiB |
260
boards/antmicro/myra_sip_baseboard/doc/index.rst
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boards/antmicro/myra_sip_baseboard/doc/index.rst
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.. zephyr:board:: myra_sip_baseboard
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Overview
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********
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The Myra SiP Baseboard features Antmicro's **Myra** SiP, which integrates the **STM32G491REI6** MCU,
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128kB FRAM, and FTDI FT231XQ USB to UART converter. The board is equipped with temperature,
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humidity, and pressure sensors, designed to help monitor conditions in server rooms.
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The sensors are placed on a separate island that is detachable from the main PCB and can be
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installed directly in the required place. It provides local storage for data logging and a battery
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backup for protection against data loss. The board can be used as a building block for PoC solutions
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for monitoring environmental parameters.
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Key features include:
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- STM32G491REI6 MCU (Cortex-M4, 170 MHz)
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- 128 KB Fujitsu FRAM
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- FTDI FT231XQ USB to UART converter
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- 50 mm x 26.5 mm PCB
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- USB-C Connector for data and power
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- SHT45 temperature + humidity sensor
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- BME280 temperature + humidity + pressure sensor
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- QWIIC connectors for peripheral expansion
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- RTC with battery backup
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More information about the board can be found on `Antmicro's Open Hardware Portal <https://openhardware.antmicro.com/boards/environment-sensor-sip-baseboard>`_.
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Hardware
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********
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Myra SiP provides the following hardware:
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- **STM32G491REI6 MCU**:
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- ARM Cortex-M4 CPU with FPU, up to 170 MHz
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- Clock Sources:
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- 4 to 48 MHz external crystal oscillator (HSE)
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- 32 kHz crystal oscillator for RTC (LSE)
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- Internal 16 MHz RC (±1%)
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- Internal low-power 32 kHz RC (±5%)
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- 2 PLLs for system clock, USB, audio, ADC
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- RTC: Real-time clock with hardware calendar, alarms, and calibration
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- Timers:
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- 1x 32-bit timer and 2x 16-bit timers with up to 4x IC/OC/PWM or pulse counter and quadrature
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(incremental) encoder input
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- 3x 16-bit advanced motor control timers with up to 8x PWM channels, dead time generation,
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emergency stop
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- 1x 16-bit timer with 2x IC/OC, one OCN/PWM, dead time generation, emergency stop
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- 2x watchdog timers (independent, window)
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- 2x 16-bit basic timers
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- SysTick timer
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- 1x low-power timer
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- I/Os: Up to 86 fast I/Os, most 5V tolerant
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- Memory:
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- 512 KB Flash memory with ECC and PCROP protection
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- 96 KB SRAM including 32 KB with hardware parity check
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- Analog peripherals:
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- 3x 16-bit ADCs with up to 36 channels, hardware oversampling, and resolution up to 16-bit
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- 4x 12-bit DAC channels
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- 4x ultra-fast rail-to-rail analog comparators
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- 4x operational amplifiers with built-in PGA
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- Internal temperature sensor and voltage reference with support for three output voltages
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(2.048 V, 2.5 V, 2.9 V)
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- Communication Interfaces:
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- 2x FDCAN controllers supporting flexible data rate
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- 3x I2C Fast Mode Plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus support
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- 5x USART/UART (ISO 7816, LIN, IrDA, modem control)
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- 1x LPUART
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- 3x SPI interfaces (2x with multiplexed half-duplex I²S)
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- 1x SAI (serial audio interface)
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- USB 2.0 full-speed with LPM and BCD support
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- IRTIM (infrared interface)
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- USB Type-C™ / USB Power Delivery (UCPD)
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- Other Peripherals:
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- 16-channel DMA controller
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- True Random Number Generator (RNG)
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- CRC calculation unit, 96-bit unique ID
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- Development support: SWD, JTAG, Embedded Trace Macrocell™
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- ECOPACK2® compliant packages
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- **128 KB Fujitsu MB85RS1MT FRAM**: Local storage for data logging, allowing non-volatile memory storage.
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- **FTDI FT231XQ USB to UART converter**: Provides a reliable USB to UART interface.
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More information about STM32G491RE can be found here:
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- `STM32G491RE on www.st.com`_
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Other board's peripherals:
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--------------------------
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- USB-C Connector: For data and power.
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- SHT45 sensor:
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- Relative humidity accuracy: ±1.0% RH
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- Operating humidity range: 0-100% RH
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- Temperature accuracy: ±0.1°C
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- Operating temperature range: -40°C to 125°C
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- BME280 sensor:
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- Relative humidity accuracy: ±3% RH
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- Temperature accuracy: ±1°C
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- Pressure accuracy: ±1 hPa
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- Operating temperature range: -40°C to 85°C
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- Pressure range: 300-1100 hPa
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- QWIIC connectors: For easy peripheral expansion.
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Supported Features
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------------------
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The Zephyr ``myra_sip_baseboard`` board target supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; serial |
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| | | port-interrupt |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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+-----------+------------+-------------------------------------+
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| WATCHDOG | on-chip | independent watchdog |
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+-----------+------------+-------------------------------------+
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| PWM | on-chip | pwm |
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+-----------+------------+-------------------------------------+
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| ADC | on-chip | adc |
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+-----------+------------+-------------------------------------+
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| DAC | on-chip | dac controller |
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+-----------+------------+-------------------------------------+
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| FLASH | on-chip | flash memory |
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+-----------+------------+-------------------------------------+
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| EEPROM | on-chip | eeprom |
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+-----------+------------+-------------------------------------+
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| NVS | on-chip | nvs |
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+-----------+------------+-------------------------------------+
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| COUNTER | on-chip | rtc |
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| die-temp | on-chip | die temperature sensor |
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+-----------+------------+-------------------------------------+
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| FDCAN1 | on-chip | can controller |
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+-----------+------------+-------------------------------------+
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| RTC | on-chip | rtc |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on this Zephyr port.
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Connections and IOs
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-------------------
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Antmicro's Myra SiP Baseboard provides the following default pin mappings for peripherals:
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.. rst-class:: rst-columns
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- LPUART_1_TX : PA2
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- LPUART_1_RX : PA3
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- I2C_1_SCL : PB8
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- I2C_1_SDA : PB9
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- SPI_CS2 : PB2
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- SPI_CS3 : PA7
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- SPI_2_SCK : PB13
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- SPI_2_MISO : PB14
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- SPI_2_MOSI : PB15
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- PWM_2_CH1 : PA5
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- USER_PB : PC13
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- LD2 : PA5
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- ADC1_IN1 : PA0
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- DAC1_OUT1 : PA4
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- USB_MCU_N : PA11
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- USB_MCU_P : PA12
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- SWDIO-JMTS : PA13
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- SWCLK-JTCK : PA14
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- JTDI : PA15
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- JTDO : PB3
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- JTRST : PB4
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- FRAM_HOLD (ACTIVE LOW) : PB10
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- FRAM_WP (ACTIVE LOW) : PB11
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- FRAM_CS (ACTIVE LOW) : PB12
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- GPIO_PC10 : PC10
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- GPIO_PC11 : PC11
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- GPIO_PC12 : PC12
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- PF0_OSC : PF0
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System Clock
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------------
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System clock can be driven by an internal or an external oscillator, as well as by the main PLL
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clock. By default, system clock is driven by PLL clock at 170MHz (boost mode selected), which in
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turn, is driven by the 8MHz high speed external oscillator (HSE). While the HSE oscillator is
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capable of operating at frequencies up to 48 MHz by default, in this configuration, it is
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specifically set to 8 MHz.
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Serial Port
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-----------
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The Myra SiP Baseboard has 5 U(S)ARTs. The Zephyr console output is assigned to LPUART1. The default
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settings are 115200 8N1.
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Programming and Debugging
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*************************
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Applications for the ``myra_sip_baseboard`` board target can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details).
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Flashing
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********
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This board has a USB-JTAG interface and can be used with OpenOCD.
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Connect the Myra SiP Baseboard to your host computer using the USB port, then build and flash
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the application. Here is an example for :zephyr:code-sample:`hello_world`.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: myra_sip_baseboard
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:goals: build flash
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Then run a serial host program to connect with the Myra SiP Baseboard, e.g. using picocom:
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.. code-block:: console
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$ picocom /dev/ttyUSB0 -b 115200
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.. warning::
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The board has only one port that is used for both programming and the console. For this reason, it is
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recommended to set ``CONFIG_BOOT_DELAY`` to an arbitrary value. This is especially important when
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running twister tests on the device. You should then also use the ``--flash-before`` and
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``--device-flash-timeout=120`` options:
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.. code-block:: console
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$ scripts/twister --device-testing --device-serial /dev/ttyUSB0 --device-serial-baud 115200 -p myra_sip_baseboard --flash-before --device-flash-timeout=120 -v
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Debugging
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*********
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You can debug an application in the usual way. Here is an example for the
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:zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: myra_sip_baseboard
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:maybe-skip-config:
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:goals: debug
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.. _STM32G491RE on www.st.com:
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https://www.st.com/en/microcontrollers-microprocessors/stm32g491re.html
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219
boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts
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219
boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts
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@ -0,0 +1,219 @@
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/*
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* Copyright (c) 2024 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <antmicro/myra.dtsi>
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/ {
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compatible = "antmicro,myra-sip-baseboard";
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model = "Myra SiP Baseboard";
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chosen {
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zephyr,console = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,canbus = &fdcan1;
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zephyr,code-partition = &slot0_partition;
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};
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leds: leds {
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compatible = "gpio-leds";
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green_led: led_0 {
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gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
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label = "User LD2";
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};
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};
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pwmleds {
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compatible = "pwm-leds";
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green_pwm_led: green_pwm_led {
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pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button: button {
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label = "User";
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gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
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zephyr,code = <INPUT_KEY_0>;
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};
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};
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aliases {
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led0 = &green_led;
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mcuboot-led0 = &green_led;
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pwm-led0 = &green_pwm_led;
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sw0 = &user_button;
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watchdog0 = &iwdg;
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volt-sensor0 = &vref;
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volt-sensor1 = &vbat;
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rtc = &rtc;
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};
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};
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&clk_lse {
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status = "okay";
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};
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&clk_lsi {
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status = "okay";
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};
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&clk_hsi48 {
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status = "okay";
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};
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&clk_hse {
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clock-frequency = <DT_FREQ_M(8)>;
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status = "okay";
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};
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&pll {
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div-m = <2>;
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mul-n = <85>;
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div-p = <7>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(170)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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};
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&lpuart1 {
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pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
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pinctrl-1 = <&analog_pa2 &analog_pa3>;
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pinctrl-names = "default", "sleep";
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current-speed = <115200>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
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pinctrl-names = "default";
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status = "okay";
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bme280@76 {
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compatible = "bosch,bme280";
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reg = <0x76>;
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};
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sht4x@44 {
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compatible = "sensirion,sht4x";
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repeatability = <2>;
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reg = <0x44>;
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};
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};
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&timers2 {
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status = "okay";
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pwm2: pwm {
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status = "okay";
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pinctrl-0 = <&tim2_ch1_pa5>;
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pinctrl-names = "default";
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};
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};
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stm32_lp_tick_source: &lptim1 {
|
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
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<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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status = "okay";
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};
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&rtc {
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
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<&rcc STM32_SRC_LSE RTC_SEL(1)>;
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status = "okay";
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
boot_partition: partition@0 {
|
||||
label = "mcuboot";
|
||||
reg = <0x00000000 DT_SIZE_K(34)>;
|
||||
};
|
||||
slot0_partition: partition@8800 {
|
||||
label = "image-0";
|
||||
reg = <0x00008800 DT_SIZE_K(240)>;
|
||||
};
|
||||
slot1_partition: partition@44800 {
|
||||
label = "image-1";
|
||||
reg = <0x00044800 DT_SIZE_K(234)>;
|
||||
};
|
||||
/* Set 4Kb of storage at the end of the 512Kb of flash */
|
||||
storage_partition: partition@7f000 {
|
||||
label = "storage";
|
||||
reg = <0x0007f000 DT_SIZE_K(4)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&adc1 {
|
||||
pinctrl-0 = <&adc1_in1_pa0>;
|
||||
pinctrl-names = "default";
|
||||
st,adc-clock-source = "SYNC";
|
||||
st,adc-prescaler = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&die_temp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dac1 {
|
||||
pinctrl-0 = <&dac1_out1_pa4>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fdcan1 {
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>,
|
||||
<&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
|
||||
pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vref {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vbat {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timers6 {
|
||||
status = "okay";
|
||||
st,prescaler = <1>;
|
||||
};
|
||||
|
||||
&timers7 {
|
||||
status = "okay";
|
||||
st,prescaler = <1>;
|
||||
};
|
||||
27
boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml
Normal file
27
boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
identifier: myra_sip_baseboard
|
||||
name: Myra SiP Baseboard
|
||||
type: mcu
|
||||
arch: arm
|
||||
toolchain:
|
||||
- zephyr
|
||||
- gnuarmemb
|
||||
ram: 128
|
||||
flash: 512
|
||||
supported:
|
||||
- nvs
|
||||
- pwm
|
||||
- i2c
|
||||
- gpio
|
||||
- usb device
|
||||
- spi
|
||||
- watchdog
|
||||
- dma
|
||||
- can
|
||||
- rtc
|
||||
- sensors
|
||||
testing:
|
||||
timeout_multiplier: 3
|
||||
renode:
|
||||
uart: sysbus.lpuart1
|
||||
resc: boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.resc
|
||||
vendor: antmicro
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2024 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_GPIO=y
|
||||
CONFIG_CLOCK_CONTROL=y
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_ARM_MPU=y
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
flash0: Memory.MappedMemory @ sysbus 0x8000000
|
||||
size: 0x80000
|
||||
|
||||
sram0: Memory.MappedMemory @ sysbus 0x20000000
|
||||
size: 0x1c000
|
||||
|
||||
timers2: Timers.STM32_Timer @ sysbus <0x40000000, +0x400>
|
||||
frequency: 10000000
|
||||
initialLimit: 0xffffffff
|
||||
->nvic0@28
|
||||
|
||||
timers6: Timers.STM32_Timer @ sysbus <0x40001000, +0x400>
|
||||
frequency: 10000000
|
||||
initialLimit: 0xffffffff
|
||||
->nvic0@54
|
||||
|
||||
timers7: Timers.STM32_Timer @ sysbus <0x40001400, +0x400>
|
||||
frequency: 10000000
|
||||
initialLimit: 0xffffffff
|
||||
->nvic0@55
|
||||
|
||||
clk_lse: Python.PythonPeripheral @ sysbus 0x40007000
|
||||
size: 0x4
|
||||
initable: true
|
||||
filename: "scripts/pydev/rolling-bit.py"
|
||||
|
||||
gpioa: GPIOPort.STM32_GPIOPort @ sysbus <0x48000000, +0x400>
|
||||
|
||||
gpiob: GPIOPort.STM32_GPIOPort @ sysbus <0x48000400, +0x400>
|
||||
|
||||
gpioc: GPIOPort.STM32_GPIOPort @ sysbus <0x48000800, +0x400>
|
||||
|
||||
gpiod: GPIOPort.STM32_GPIOPort @ sysbus <0x48000c00, +0x400>
|
||||
|
||||
gpioe: GPIOPort.STM32_GPIOPort @ sysbus <0x48001000, +0x400>
|
||||
|
||||
gpiof: GPIOPort.STM32_GPIOPort @ sysbus <0x48001400, +0x400>
|
||||
|
||||
gpiog: GPIOPort.STM32_GPIOPort @ sysbus <0x48001800, +0x400>
|
||||
|
||||
greenled: Miscellaneous.LED @ gpioa 0x5
|
||||
|
||||
gpioa:
|
||||
5 -> greenled@0
|
||||
|
||||
nvic0: IRQControllers.NVIC @ {
|
||||
sysbus new Bus.BusPointRegistration { address: 0xe000e000; cpu: cpu0 }
|
||||
}
|
||||
-> cpu0@0
|
||||
|
||||
cpu0: CPU.CortexM @ sysbus
|
||||
cpuType: "cortex-m4f"
|
||||
nvic: nvic0
|
||||
|
||||
i2c1: I2C.STM32F7_I2C @ sysbus 0x40005400
|
||||
EventInterrupt->nvic0@31
|
||||
ErrorInterrupt->nvic0@32
|
||||
|
||||
sht4x: I2C.SHT45 @ i2c1 0x44
|
||||
|
||||
adc1: Analog.STM32_ADC @ sysbus 0x50000000
|
||||
IRQ->nvic0@18
|
||||
|
||||
lpuart1: UART.STM32F7_USART @ sysbus 0x40008000
|
||||
frequency: 200000000
|
||||
lowPowerMode: true
|
||||
IRQ->nvic0@91
|
||||
|
||||
rcc: Python.PythonPeripheral @ sysbus 0x40021000
|
||||
size: 0x400
|
||||
initable: true
|
||||
filename: "scripts/pydev/flipflop.py"
|
||||
|
||||
rng: Miscellaneous.STM32F4_RNG @ sysbus 0x50060800
|
||||
->nvic0@90
|
||||
|
||||
rtc: Timers.STM32F4_RTC @ sysbus 0x40002800
|
||||
AlarmIRQ->nvic0@41
|
||||
|
||||
spi2: SPI.STM32SPI @ sysbus 0x40003800
|
||||
IRQ->nvic0@36
|
||||
|
||||
iwdg: Timers.STM32_IndependentWatchdog @ sysbus 0x40003000
|
||||
frequency: 32000
|
||||
|
||||
dwt: Miscellaneous.DWT @ sysbus 0xE0001000
|
||||
frequency: 72000000
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
:name: Myra SiP Baseboard
|
||||
:description: This script is prepared to run Zephyr on the Myra SiP Baseboard.
|
||||
|
||||
$name?="Myra SiP Baseboard"
|
||||
|
||||
using sysbus
|
||||
mach create $name
|
||||
machine LoadPlatformDescription $ORIGIN/myra_sip_baseboard.repl
|
||||
|
||||
showAnalyzer lpuart1
|
||||
|
||||
macro reset
|
||||
"""
|
||||
sysbus LoadELF $elf
|
||||
cpu0 VectorTableOffset `sysbus GetSymbolAddress "_vector_table"`
|
||||
"""
|
||||
runMacro $reset
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
adapter driver ft232r
|
||||
adapter speed 1000
|
||||
|
||||
ft232r vid_pid 0x0403 0x6015
|
||||
ft232r tck_num RTS
|
||||
ft232r tms_num DTR
|
||||
ft232r tdi_num RI
|
||||
ft232r tdo_num CTS
|
||||
ft232r trst_num DSR
|
||||
ft232r srst_num DCD
|
||||
|
||||
ft232r restore_serial 0x0015
|
||||
source [find target/stm32g4x.cfg]
|
||||
17
dts/arm/antmicro/myra.dtsi
Normal file
17
dts/arm/antmicro/myra.dtsi
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/g4/stm32g491Xe.dtsi>
|
||||
#include <st/g4/stm32g491r(c-e)tx-pinctrl.dtsi>
|
||||
#include <mem.h>
|
||||
#include <freq.h>
|
||||
|
||||
&spi2 {
|
||||
pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
|
||||
&spi2_miso_pb14 &spi2_mosi_pb15>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -57,6 +57,7 @@ ams AMS AG
|
|||
amstaos AMS-Taos Inc.
|
||||
analogix Analogix Semiconductor, Inc.
|
||||
andestech Andes Technology Corporation
|
||||
antmicro Antmicro
|
||||
anvo Anvo-Systems Dresden GmbH
|
||||
aosong Guangzhou Aosong Electronic Co., Ltd.
|
||||
ap Angst+Pfister
|
||||
|
|
|
|||
5
soc/antmicro/myra/Kconfig
Normal file
5
soc/antmicro/myra/Kconfig
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
# Copyright (c) 2024 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_MYRA
|
||||
select SOC_STM32G491XX
|
||||
18
soc/antmicro/myra/Kconfig.soc
Normal file
18
soc/antmicro/myra/Kconfig.soc
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
# Copyright (c) 2024 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# The Myra is technically a SiP (System-in-Package) that consists of
|
||||
# the STM32G491REI6 MCU and additional components like FRAM. So for
|
||||
# Antmicro Myra SiP Baseboard the STM32G491XX SoC is to be indicated as
|
||||
# the build target, but since the Myra SiP is what a user can actually
|
||||
# see on a board, using only STM32G491XX in the Zephyr build
|
||||
# infrastructure might be confusing. That's why in the top level of SoC
|
||||
# definitions (for user-configurable options in Kconfig, for example)
|
||||
# the Myra term is used and STM32G491XX underneath.
|
||||
config SOC_MYRA
|
||||
bool
|
||||
help
|
||||
Antmicro Myra System-in-Package
|
||||
|
||||
config SOC
|
||||
default "myra" if SOC_MYRA
|
||||
2
soc/antmicro/myra/soc.yml
Normal file
2
soc/antmicro/myra/soc.yml
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
socs:
|
||||
- name: myra
|
||||
Loading…
Add table
Add a link
Reference in a new issue