michaelh/zephyr
1
0
Fork 0
Code Releases Activity

driver: clock_control: Add clock controller initial version of RTS5912.

Browse source 
Add clock controller driver for Realtek RTS5912.

Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
This commit is contained in:
Lin Yu-Cheng 2024-11-22 17:01:05 +08:00 • committed by Benjamin Cabé
commit 6ea7560ce2
9 changed files with 1001 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
drivers/clock_control/CMakeLists.txt
View file

@ -38,6 +38,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_cont
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO clock_control_rpi_pico.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL clock_control_nrf2_global_hsfll.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RTS5912_SCCON clock_control_rts5912_sccon.c)
if(CONFIG_CLOCK_CONTROL_NRF2)
zephyr_library_sources(clock_control_nrf2_common.c)

2
drivers/clock_control/Kconfig
View file

@ -56,6 +56,8 @@ source "drivers/clock_control/Kconfig.npcx"
source "drivers/clock_control/Kconfig.rv32m1"
source "drivers/clock_control/Kconfig.rts5912"
source "drivers/clock_control/Kconfig.esp32"
source "drivers/clock_control/Kconfig.litex"

10
drivers/clock_control/Kconfig.rts5912 Normal file
View file

@ -0,0 +1,10 @@
# SPDX-License-Identifier: Apache-2.0
#
# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
#
config CLOCK_CONTROL_RTS5912_SCCON
bool "Realtek RTS5912 system clock controller driver"
default y if DT_HAS_REALTEK_RTS5912_SCCON_ENABLED
help
Enable support for RTS5912 system clock controller driver

247
drivers/clock_control/clock_control_rts5912_sccon.c Normal file
View file

@ -0,0 +1,247 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
*/
#define DT_DRV_COMPAT realtek_rts5912_sccon
#include <zephyr/logging/log.h>
#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/rts5912_clock.h>
#include <reg/reg_system.h>
LOG_MODULE_REGISTER(sccon, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
#define RC25M_FREQ DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rc25m), clock_frequency)
#define PLL_FREQ DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), clock_frequency)
struct rts5912_sccon_config {
uint32_t reg_base;
uint8_t sysclk_src;
uint8_t sysclk_div;
};
static int rts5912_periph_clock_control(const struct device *dev, clock_control_subsys_t sub_system,
bool on_off)
{
const struct rts5912_sccon_config *const config = dev->config;
struct rts5912_sccon_subsys *subsys = (struct rts5912_sccon_subsys *)sub_system;
SYSTEM_Type *sys_reg = (SYSTEM_Type *)config->reg_base;
uint32_t clk_grp = subsys->clk_grp;
uint32_t clk_idx = subsys->clk_idx;
uint32_t module_idx;
switch (clk_grp) {
case RTS5912_SCCON_I2C:
module_idx = (clk_idx - I2C0_CLKPWR) >> 2;
if (on_off) {
sys_reg->I2CCLK |= BIT(clk_idx);
} else {
sys_reg->I2CCLK &= ~BIT(clk_idx);
}
LOG_DBG("Turn I2C%d clock <%s>", module_idx, on_off ? "ON" : "OFF");
break;
case RTS5912_SCCON_UART:
if (on_off) {
sys_reg->UARTCLK = BIT(clk_idx);
} else {
sys_reg->UARTCLK &= ~BIT(clk_idx);
}
LOG_DBG("Turn UART0 clock <%s>", on_off ? "ON" : "OFF");
break;
case RTS5912_SCCON_ADC:
if (on_off) {
sys_reg->ADCCLK = BIT(clk_idx);
} else {
sys_reg->ADCCLK &= ~BIT(clk_idx);
}
LOG_DBG("Turn ADC clock <%s>", on_off ? "ON" : "OFF");
break;
case RTS5912_SCCON_PERIPH_GRP0:
if (on_off) {
sys_reg->PERICLKPWR0 |= BIT(clk_idx);
} else {
sys_reg->PERICLKPWR0 &= ~BIT(clk_idx);
}
LOG_DBG("Turn GRP0-%d clock <%s>", clk_idx, on_off ? "ON" : "OFF");
break;
case RTS5912_SCCON_PERIPH_GRP1:
if (on_off) {
sys_reg->PERICLKPWR1 |= BIT(clk_idx);
} else {
sys_reg->PERICLKPWR1 &= ~BIT(clk_idx);
}
LOG_DBG("Turn GRP1-%d clock <%s>", clk_idx, on_off ? "ON" : "OFF");
break;
case RTS5912_SCCON_PERIPH_GRP2:
if (on_off) {
sys_reg->PERICLKPWR2 |= BIT(clk_idx);
} else {
sys_reg->PERICLKPWR2 &= ~BIT(clk_idx);
}
LOG_DBG("Turn GRP2-%d clock <%s>", clk_idx, on_off ? "ON" : "OFF");
break;
case RTS5912_SCCON_SYS:
LOG_ERR("Not support peripheral group #%d-%d", clk_grp, clk_idx);
return -ENOTSUP;
default:
LOG_ERR("Unknown peripheral group #%d", clk_grp);
return -EINVAL;
}
return 0;
}
static int rts5912_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
{
return rts5912_periph_clock_control(dev, sub_system, true);
}
static int rts5912_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
{
return rts5912_periph_clock_control(dev, sub_system, false);
}
static int rts5912_clock_control_get_rate(const struct device *dev,
clock_control_subsys_t sub_system, uint32_t *rate)
{
const struct rts5912_sccon_config *const config = dev->config;
struct rts5912_sccon_subsys *subsys = (struct rts5912_sccon_subsys *)sub_system;
SYSTEM_Type *sys_reg = (SYSTEM_Type *)config->reg_base;
uint32_t clk_grp = subsys->clk_grp;
uint32_t clk_idx = subsys->clk_idx;
uint32_t module_idx;
uint32_t offset;
uint32_t src, divide, freq = 0;
switch (clk_grp) {
case RTS5912_SCCON_I2C:
module_idx = (clk_idx - I2C0_CLKPWR) >> 2;
offset = (SYSTEM_I2CCLK_I2C1CLKSRC_Pos - SYSTEM_I2CCLK_I2C0CLKSRC_Pos) * module_idx;
src = ((sys_reg->I2CCLK >> offset) & SYSTEM_I2CCLK_I2C0CLKSRC_Msk) ? PLL_FREQ
: RC25M_FREQ;
offset = SYSTEM_I2CCLK_I2C0CLKDIV_Pos;
offset += (SYSTEM_I2CCLK_I2C1CLKDIV_Pos - SYSTEM_I2CCLK_I2C0CLKDIV_Pos) *
module_idx;
divide = (sys_reg->I2CCLK >> offset) & SYSTEM_I2CCLK_I2C0CLKDIV_Msk;
freq = src >> divide;
LOG_DBG("I2C%d: src<%s> divide<%ld> freq<%d>", module_idx,
(src == PLL_FREQ) ? "PLL" : "RC25M", BIT(divide), freq);
break;
case RTS5912_SCCON_UART:
src = (sys_reg->UARTCLK & SYSTEM_UARTCLK_SRC_Msk) ? PLL_FREQ : RC25M_FREQ;
divide = (sys_reg->UARTCLK & SYSTEM_UARTCLK_DIV_Msk) >> SYSTEM_UARTCLK_DIV_Pos;
freq = src >> divide;
LOG_DBG("UART0: src<%s> divide<%ld> freq<%d>", (src == PLL_FREQ) ? "PLL" : "RC25M",
BIT(divide), freq);
break;
case RTS5912_SCCON_ADC:
src = (sys_reg->ADCCLK & SYSTEM_ADCCLK_SRC_Msk) ? RC25M_FREQ : PLL_FREQ;
divide = (sys_reg->ADCCLK & SYSTEM_ADCCLK_DIV_Msk) >> SYSTEM_ADCCLK_DIV_Pos;
switch (divide) {
case 0:
__fallthrough;
case 1:
__fallthrough;
case 2:
__fallthrough;
case 3:
divide += 1;
freq = src / divide;
break;
case 4:
freq = src / 6;
divide = 6;
break;
case 5:
freq = src / 8;
divide = 8;
break;
case 6:
freq = src / 12;
divide = 12;
break;
case 7:
freq = src / 16;
divide = 16;
break;
default:
return -EINVAL;
}
LOG_DBG("ADC0: src<%s> divide<%d> freq<%d>", (src == PLL_FREQ) ? "PLL" : "RC25M",
divide, freq);
break;
case RTS5912_SCCON_SYS:
src = (sys_reg->SYSCLK & SYSTEM_SYSCLK_SRC_Msk) ? PLL_FREQ : RC25M_FREQ;
divide = (sys_reg->SYSCLK & SYSTEM_SYSCLK_DIV_Msk) ? 0x01ul : 0x00ul;
freq = src >> divide;
LOG_DBG("System Clock: src<%s> divide<%d> freq<%d>",
(src == PLL_FREQ) ? "PLL" : "RC25M", divide, freq);
break;
case RTS5912_SCCON_PERIPH_GRP0:
__fallthrough;
case RTS5912_SCCON_PERIPH_GRP1:
__fallthrough;
case RTS5912_SCCON_PERIPH_GRP2:
LOG_ERR("Not support peripheral group #%d-%d", clk_grp, clk_idx);
return -ENOTSUP;
default:
LOG_ERR("Unknown peripheral group #%d", clk_grp);
return -EINVAL;
}
*rate = freq;
return 0;
}
static DEVICE_API(clock_control, rts5912_clock_control_api) = {
.on = rts5912_clock_control_on,
.off = rts5912_clock_control_off,
.get_rate = rts5912_clock_control_get_rate,
};
static int rts5912_clock_control_init(const struct device *dev)
{
const struct rts5912_sccon_config *const config = dev->config;
SYSTEM_Type *sys_reg = (SYSTEM_Type *)config->reg_base;
/* Setup system clock */
sys_reg->SYSCLK = (config->sysclk_src << SYSTEM_SYSCLK_SRC_Pos) |
(config->sysclk_div << SYSTEM_SYSCLK_DIV_Pos);
return 0;
}
const struct rts5912_sccon_config rts5912_sccon_config = {
.reg_base = DT_INST_REG_ADDR_BY_IDX(0, 0),
.sysclk_src = 1,
.sysclk_div = 0,
};
DEVICE_DT_INST_DEFINE(0, &rts5912_clock_control_init, NULL, NULL, &rts5912_sccon_config,
PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &rts5912_clock_control_api);

22
dts/arm/realtek/ec/rts5912.dtsi
View file

@ -44,12 +44,34 @@
reg = <0x20050000 0x8000>;
};
clocks {
rc25m: rc25m {
compatible = "fixed-clock";
clock-frequency = <25000000>;
#clock-cells = <0>;
};
pll: pll {
compatible = "fixed-clock";
clock-frequency = <100000000>;
#clock-cells = <0>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&nvic>;
ranges;
sccon: clock-controller@40020000 {
compatible = "realtek,rts5912-sccon";
reg = <0x40020000 0xf0>;
#clock-cells = <2>;
clocks = <&rc25m>, <&pll>;
clock-names = "rc25m", "pll";
};
};
};

21
dts/bindings/clock/realtek,rts5912-sccon.yaml Normal file
View file

@ -0,0 +1,21 @@
# SPDX-License-Identifier: Apache-2.0
#
# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
#
description: Realtek RTS5912 System Clock Controller (SCCON)
compatible: "realtek,rts5912-sccon"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 2
clock-cells:
- clk-grp
- clk-idx

20
include/zephyr/drivers/clock_control/clock_control_rts5912.h Normal file
View file

@ -0,0 +1,20 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
*/
#include <stdint.h>
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RTS5912_H_
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RTS5912_H_
struct rts5912_sccon_subsys {
uint32_t clk_grp;
uint32_t clk_idx;
uint32_t clk_src;
uint32_t clk_div;
};
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RTS591X_H_ */

343
include/zephyr/dt-bindings/clock/rts5912_clock.h Normal file
View file

@ -0,0 +1,343 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_
/* ====================================================================================== */
/* ===================================== I2CCLK ======================================= */
#define I2CCLK_I2C0CLKPWR_Pos (0) /*!< I2C0CLKPWR (Bit 0) */
#define I2CCLK_I2C0CLKPWR_Msk (0x1) /*!< I2C0CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C0CLKSRC_Pos (1) /*!< I2C0CLKSRC (Bit 1) */
#define I2CCLK_I2C0CLKSRC_Msk (0x2) /*!< I2C0CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C0CLKDIV_Pos (2) /*!< I2C0CLKDIV (Bit 2) */
#define I2CCLK_I2C0CLKDIV_Msk (0xc) /*!< I2C0CLKDIV (Bitfield-Mask: 0x03) */
#define I2CCLK_I2C1CLKPWR_Pos (4) /*!< I2C1CLKPWR (Bit 4) */
#define I2CCLK_I2C1CLKPWR_Msk (0x10) /*!< I2C1CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C1CLKSRC_Pos (5) /*!< I2C1CLKSRC (Bit 5) */
#define I2CCLK_I2C1CLKSRC_Msk (0x20) /*!< I2C1CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C1CLKDIV_Pos (6) /*!< I2C1CLKDIV (Bit 6) */
#define I2CCLK_I2C1CLKDIV_Msk (0xc0) /*!< I2C1CLKDIV (Bitfield-Mask: 0x03) */
#define I2CCLK_I2C2CLKPWR_Pos (8) /*!< I2C2CLKPWR (Bit 8) */
#define I2CCLK_I2C2CLKPWR_Msk (0x100) /*!< I2C2CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C2CLKSRC_Pos (9) /*!< I2C2CLKSRC (Bit 9) */
#define I2CCLK_I2C2CLKSRC_Msk (0x200) /*!< I2C2CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C2CLKDIV_Pos (10) /*!< I2C2CLKDIV (Bit 10) */
#define I2CCLK_I2C2CLKDIV_Msk (0xc00) /*!< I2C2CLKDIV (Bitfield-Mask: 0x03) */
#define I2CCLK_I2C3CLKPWR_Pos (12) /*!< I2C3CLKPWR (Bit 12) */
#define I2CCLK_I2C3CLKPWR_Msk (0x1000) /*!< I2C3CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C3CLKSRC_Pos (13) /*!< I2C3CLKSRC (Bit 13) */
#define I2CCLK_I2C3CLKSRC_Msk (0x2000) /*!< I2C3CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C3CLKDIV_Pos (14) /*!< I2C3CLKDIV (Bit 14) */
#define I2CCLK_I2C3CLKDIV_Msk (0xc000) /*!< I2C3CLKDIV (Bitfield-Mask: 0x03) */
#define I2CCLK_I2C4CLKPWR_Pos (16) /*!< I2C4CLKPWR (Bit 16) */
#define I2CCLK_I2C4CLKPWR_Msk (0x10000) /*!< I2C4CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C4CLKSRC_Pos (17) /*!< I2C4CLKSRC (Bit 17) */
#define I2CCLK_I2C4CLKSRC_Msk (0x20000) /*!< I2C4CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C4CLKDIV_Pos (18) /*!< I2C4CLKDIV (Bit 18) */
#define I2CCLK_I2C4CLKDIV_Msk (0xc0000) /*!< I2C4CLKDIV (Bitfield-Mask: 0x03) */
#define I2CCLK_I2C5CLKPWR_Pos (20) /*!< I2C5CLKPWR (Bit 20) */
#define I2CCLK_I2C5CLKPWR_Msk (0x100000) /*!< I2C5CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C5CLKSRC_Pos (21) /*!< I2C5CLKSRC (Bit 21) */
#define I2CCLK_I2C5CLKSRC_Msk (0x200000) /*!< I2C5CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C5CLKDIV_Pos (22) /*!< I2C5CLKDIV (Bit 22) */
#define I2CCLK_I2C5CLKDIV_Msk (0xc00000) /*!< I2C5CLKDIV (Bitfield-Mask: 0x03) */
#define I2CCLK_I2C6CLKPWR_Pos (24) /*!< I2C6CLKPWR (Bit 24) */
#define I2CCLK_I2C6CLKPWR_Msk (0x1000000) /*!< I2C6CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C6CLKSRC_Pos (25) /*!< I2C6CLKSRC (Bit 25) */
#define I2CCLK_I2C6CLKSRC_Msk (0x2000000) /*!< I2C6CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C6CLKDIV_Pos (26) /*!< I2C6CLKDIV (Bit 26) */
#define I2CCLK_I2C6CLKDIV_Msk (0xc000000) /*!< I2C6CLKDIV (Bitfield-Mask: 0x03) */
#define I2CCLK_I2C7CLKPWR_Pos (28) /*!< I2C7CLKPWR (Bit 28) */
#define I2CCLK_I2C7CLKPWR_Msk (0x10000000) /*!< I2C7CLKPWR (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C7CLKSRC_Pos (29) /*!< I2C7CLKSRC (Bit 29) */
#define I2CCLK_I2C7CLKSRC_Msk (0x20000000) /*!< I2C7CLKSRC (Bitfield-Mask: 0x01) */
#define I2CCLK_I2C7CLKDIV_Pos (30) /*!< I2C7CLKDIV (Bit 30) */
#define I2CCLK_I2C7CLKDIV_Msk (0xc0000000) /*!< I2C7CLKDIV (Bitfield-Mask: 0x03) */
/* =================================== PERICLKPWR0 ==================================== */
#define PERICLKPWR0_GPIOCLKPWR_Pos (0) /*!< GPIOCLKPWR (Bit 0) */
#define PERICLKPWR0_GPIOCLKPWR_Msk (0x1) /*!< GPIOCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_TACHO0CLKPWR_Pos (1) /*!< TACHO0CLKPWR (Bit 1) */
#define PERICLKPWR0_TACHO0CLKPWR_Msk (0x2) /*!< TACHO0CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_TACHO1CLKPWR_Pos (2) /*!< TACHO1CLKPWR (Bit 2) */
#define PERICLKPWR0_TACHO1CLKPWR_Msk (0x4) /*!< TACHO1CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_TACHO2CLKPWR_Pos (3) /*!< TACHO2CLKPWR (Bit 3) */
#define PERICLKPWR0_TACHO2CLKPWR_Msk (0x8) /*!< TACHO2CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_TACHO3CLKPWR_Pos (4) /*!< TACHO3CLKPWR (Bit 4) */
#define PERICLKPWR0_TACHO3CLKPWR_Msk (0x10) /*!< TACHO3CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PS2CLKPWR_Pos (5) /*!< PS2CLKPWR (Bit 5) */
#define PERICLKPWR0_PS2CLKPWR_Msk (0x20) /*!< PS2CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_KBMCLKPWR_Pos (6) /*!< KBMCLKPWR (Bit 6) */
#define PERICLKPWR0_KBMCLKPWR_Msk (0x40) /*!< KBMCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PECICLKPWR_Pos (7) /*!< PECICLKPWR (Bit 7) */
#define PERICLKPWR0_PECICLKPWR_Msk (0x80) /*!< PECICLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PL0CLKPWR_Pos (8) /*!< PL0CLKPWR (Bit 8) */
#define PERICLKPWR0_PL0CLKPWR_Msk (0x100) /*!< PL0CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PL1CLKPWR_Pos (9) /*!< PL1CLKPWR (Bit 9) */
#define PERICLKPWR0_PL1CLKPWR_Msk (0x200) /*!< PL1CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM0CLKPWR_Pos (10) /*!< PWM0CLKPWR (Bit 10) */
#define PERICLKPWR0_PWM0CLKPWR_Msk (0x400) /*!< PWM0CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM1CLKPWR_Pos (11) /*!< PWM1CLKPWR (Bit 11) */
#define PERICLKPWR0_PWM1CLKPWR_Msk (0x800) /*!< PWM1CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM2CLKPWR_Pos (12) /*!< PWM2CLKPWR (Bit 12) */
#define PERICLKPWR0_PWM2CLKPWR_Msk (0x1000) /*!< PWM2CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM3CLKPWR_Pos (13) /*!< PWM3CLKPWR (Bit 13) */
#define PERICLKPWR0_PWM3CLKPWR_Msk (0x2000) /*!< PWM3CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM4CLKPWR_Pos (14) /*!< PWM4CLKPWR (Bit 14) */
#define PERICLKPWR0_PWM4CLKPWR_Msk (0x4000) /*!< PWM4CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM5CLKPWR_Pos (15) /*!< PWM5CLKPWR (Bit 15) */
#define PERICLKPWR0_PWM5CLKPWR_Msk (0x8000) /*!< PWM5CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM6CLKPWR_Pos (16) /*!< PWM6CLKPWR (Bit 16) */
#define PERICLKPWR0_PWM6CLKPWR_Msk (0x10000) /*!< PWM6CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM7CLKPWR_Pos (17) /*!< PWM7CLKPWR (Bit 17) */
#define PERICLKPWR0_PWM7CLKPWR_Msk (0x20000) /*!< PWM7CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM8CLKPWR_Pos (18) /*!< PWM8CLKPWR (Bit 18) */
#define PERICLKPWR0_PWM8CLKPWR_Msk (0x40000) /*!< PWM8CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM9CLKPWR_Pos (19) /*!< PWM9CLKPWR (Bit 19) */
#define PERICLKPWR0_PWM9CLKPWR_Msk (0x80000) /*!< PWM9CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM10CLKPWR_Pos (20) /*!< PWM10CLKPWR (Bit 20) */
#define PERICLKPWR0_PWM10CLKPWR_Msk (0x100000) /*!< PWM10CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PWM11CLKPWR_Pos (21) /*!< PWM11CLKPWR (Bit 21) */
#define PERICLKPWR0_PWM11CLKPWR_Msk (0x200000) /*!< PWM11CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_ESPICLKPWR_Pos (22) /*!< ESPICLKPWR (Bit 22) */
#define PERICLKPWR0_ESPICLKPWR_Msk (0x400000) /*!< ESPICLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_KBCCLKPWR_Pos (23) /*!< KBCCLKPWR (Bit 23) */
#define PERICLKPWR0_KBCCLKPWR_Msk (0x800000) /*!< KBCCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_ACPICLKPWR_Pos (24) /*!< ACPICLKPWR (Bit 24) */
#define PERICLKPWR0_ACPICLKPWR_Msk (0x1000000) /*!< ACPICLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_PMPORT0CLKPWR_Pos (25) /*!< PMPORT0CLKPWR (Bit 25) */
#define PERICLKPWR0_PMPORT0CLKPWR_Msk (0x2000000) /*!< PMPORT0CLKPWR (Bitfield-Mask: 0x01)*/
#define PERICLKPWR0_PMPORT1CLKPWR_Pos (26) /*!< PMPORT1CLKPWR (Bit 26) */
#define PERICLKPWR0_PMPORT1CLKPWR_Msk (0x4000000) /*!< PMPORT1CLKPWR (Bitfield-Mask: 0x01)*/
#define PERICLKPWR0_PMPORT2CLKPWR_Pos (27) /*!< PMPORT2CLKPWR (Bit 27) */
#define PERICLKPWR0_PMPORT2CLKPWR_Msk (0x8000000) /*!< PMPORT2CLKPWR (Bitfield-Mask: 0x01)*/
#define PERICLKPWR0_PMPORT3CLKPWR_Pos (28) /*!< PMPORT3CLKPWR (Bit 28) */
#define PERICLKPWR0_PMPORT3CLKPWR_Msk (0x10000000) /*!< PMPORT3CLKPWR (Bitfield-Mask: 0x01)*/
#define PERICLKPWR0_P80CLKPWR_Pos (29) /*!< P80CLKPWR (Bit 29) */
#define PERICLKPWR0_P80CLKPWR_Msk (0x20000000) /*!< P80CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_EMI0CLKPWR_Pos (30) /*!< EMI0CLKPWR (Bit 30) */
#define PERICLKPWR0_EMI0CLKPWR_Msk (0x40000000) /*!< EMI0CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR0_EMI1CLKPWR_Pos (31) /*!< EMI1CLKPWR (Bit 31) */
#define PERICLKPWR0_EMI1CLKPWR_Msk (0x80000000) /*!< EMI1CLKPWR (Bitfield-Mask: 0x01) */
/* ===================================== UARTCLK ====================================== */
#define UARTCLK_PWR_Pos (0) /*!< PWR (Bit 0) */
#define UARTCLK_PWR_Msk (0x1) /*!< PWR (Bitfield-Mask: 0x01) */
#define UARTCLK_SRC_Pos (1) /*!< SRC (Bit 1) */
#define UARTCLK_SRC_Msk (0x2) /*!< SRC (Bitfield-Mask: 0x01) */
#define UARTCLK_DIV_Pos (2) /*!< DIV (Bit 2) */
#define UARTCLK_DIV_Msk (0xc) /*!< DIV (Bitfield-Mask: 0x03) */
/* ===================================== ADCCLK ======================================= */
#define ADCCLK_PWR_Pos (0) /*!< PWR (Bit 0) */
#define ADCCLK_PWR_Msk (0x1) /*!< PWR (Bitfield-Mask: 0x01) */
#define ADCCLK_SRC_Pos (1) /*!< SRC (Bit 1) */
#define ADCCLK_SRC_Msk (0x2) /*!< SRC (Bitfield-Mask: 0x01) */
#define ADCCLK_DIV_Pos (2) /*!< DIV (Bit 2) */
#define ADCCLK_DIV_Msk (0x1c) /*!< DIV (Bitfield-Mask: 0x07) */
/* =================================== PERICLKPWR1 ==================================== */
#define PERICLKPWR1_EMI2CLKPWR_Pos (0) /*!< EMI2CLKPWR (Bit 0) */
#define PERICLKPWR1_EMI2CLKPWR_Msk (0x1) /*!< EMI2CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_EMI3CLKPWR_Pos (1) /*!< EMI3CLKPWR (Bit 1) */
#define PERICLKPWR1_EMI3CLKPWR_Msk (0x2) /*!< EMI3CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_EMI4CLKPWR_Pos (2) /*!< EMI4CLKPWR (Bit 2) */
#define PERICLKPWR1_EMI4CLKPWR_Msk (0x4) /*!< EMI4CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_EMI5CLKPWR_Pos (3) /*!< EMI5CLKPWR (Bit 3) */
#define PERICLKPWR1_EMI5CLKPWR_Msk (0x8) /*!< EMI5CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_EMI6CLKPWR_Pos (4) /*!< EMI6CLKPWR (Bit 4) */
#define PERICLKPWR1_EMI6CLKPWR_Msk (0x10) /*!< EMI6CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_EMI7CLKPWR_Pos (5) /*!< EMI7CLKPWR (Bit 5) */
#define PERICLKPWR1_EMI7CLKPWR_Msk (0x20) /*!< EMI7CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_I3C0CLKPWR_Pos (9) /*!< I3C0CLKPWR (Bit 9) */
#define PERICLKPWR1_I3C0CLKPWR_Msk (0x200) /*!< I3C0CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_I3C1CLKPWR_Pos (10) /*!< I3C1CLKPWR (Bit 10) */
#define PERICLKPWR1_I3C1CLKPWR_Msk (0x400) /*!< I3C1CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_I2CAUTOCLKPWR_Pos (11) /*!< I2CAUTOCLKPWR (Bit 11) */
#define PERICLKPWR1_I2CAUTOCLKPWR_Msk (0x800) /*!< I2CAUTOCLKPWR (Bitfield-Mask: 0x01)*/
#define PERICLKPWR1_MCCLKPWR_Pos (12) /*!< MCCLKPWR (Bit 12) */
#define PERICLKPWR1_MCCLKPWR_Msk (0x1000) /*!< MCCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_TMR0CLKPWR_Pos (13) /*!< TMR0CLKPWR (Bit 13) */
#define PERICLKPWR1_TMR0CLKPWR_Msk (0x2000) /*!< TMR0CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_TMR1CLKPWR_Pos (14) /*!< TMR1CLKPWR (Bit 14) */
#define PERICLKPWR1_TMR1CLKPWR_Msk (0x4000) /*!< TMR1CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_TMR2CLKPWR_Pos (15) /*!< TMR2CLKPWR (Bit 15) */
#define PERICLKPWR1_TMR2CLKPWR_Msk (0x8000) /*!< TMR2CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_TMR3CLKPWR_Pos (16) /*!< TMR3CLKPWR (Bit 16) */
#define PERICLKPWR1_TMR3CLKPWR_Msk (0x10000) /*!< TMR3CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_TMR4CLKPWR_Pos (17) /*!< TMR4CLKPWR (Bit 17) */
#define PERICLKPWR1_TMR4CLKPWR_Msk (0x20000) /*!< TMR4CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_TMR5CLKPWR_Pos (18) /*!< TMR5CLKPWR (Bit 18) */
#define PERICLKPWR1_TMR5CLKPWR_Msk (0x40000) /*!< TMR5CLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_RTMRCLKPWR_Pos (19) /*!< RTMRCLKPWR (Bit 19) */
#define PERICLKPWR1_RTMRCLKPWR_Msk (0x80000) /*!< RTMRCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR1_SLWTMR0CLKPWR_Pos (20) /*!< SLWTMR0CLKPWR (Bit 20) */
#define PERICLKPWR1_SLWTMR0CLKPWR_Msk (0x100000) /*!< SLWTMR0CLKPWR (Bitfield-Mask: 0x01)*/
#define PERICLKPWR1_SLWTMR1CLKPWR_Pos (21) /*!< SLWTMR1CLKPWR (Bit 21) */
#define PERICLKPWR1_SLWTMR1CLKPWR_Msk (0x200000) /*!< SLWTMR1CLKPWR (Bitfield-Mask: 0x01)*/
/* =================================== PERICLKPWR2 ==================================== */
#define PERICLKPWR2_RTCCLKPWR_Pos (0) /*!< RTCCLKPWR (Bit 0) */
#define PERICLKPWR2_RTCCLKPWR_Msk (0x1) /*!< RTCCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR2_WDTCLKPWR_Pos (1) /*!< WDTCLKPWR (Bit 1) */
#define PERICLKPWR2_WDTCLKPWR_Msk (0x2) /*!< WDTCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR2_PWRBTNCLKPWR_Pos (2) /*!< PWRBTNCLKPWR (Bit 2) */
#define PERICLKPWR2_PWRBTNCLKPWR_Msk (0x4) /*!< PWRBTNCLKPWR (Bitfield-Mask: 0x01) */
#define PERICLKPWR2_RC32KSRC_Pos (30) /*!< RC32KSRC (Bit 30) */
#define PERICLKPWR2_RC32KSRC_Msk (0xc0000000) /*!< RC32KSRC (Bitfield-Mask: 0x03) */
/* ====================================================================================== */
#define RTS5912_SCCON_SYS (0)
#define RTS5912_SCCON_I2C (2)
#define RTS5912_SCCON_UART (3)
#define RTS5912_SCCON_ADC (4)
#define RTS5912_SCCON_PERIPH_GRP0 (5)
#define RTS5912_SCCON_PERIPH_GRP1 (6)
#define RTS5912_SCCON_PERIPH_GRP2 (7)
#define I2C0_CLKPWR (I2CCLK_I2C0CLKPWR_Pos)
#define I2C1_CLKPWR (I2CCLK_I2C1CLKPWR_Pos)
#define I2C2_CLKPWR (I2CCLK_I2C2CLKPWR_Pos)
#define I2C3_CLKPWR (I2CCLK_I2C3CLKPWR_Pos)
#define I2C4_CLKPWR (I2CCLK_I2C4CLKPWR_Pos)
#define I2C5_CLKPWR (I2CCLK_I2C5CLKPWR_Pos)
#define I2C6_CLKPWR (I2CCLK_I2C6CLKPWR_Pos)
#define I2C7_CLKPWR (I2CCLK_I2C7CLKPWR_Pos)
#define I2C0_PLL (0x0 << I2CCLK_I2C0CLKSRC_Pos)
#define I2C0_RC25M (0x1 << I2CCLK_I2C0CLKSRC_Pos)
#define I2C1_PLL (0x0 << I2CCLK_I2C1CLKSRC_Pos)
#define I2C1_RC25M (0x1 << I2CCLK_I2C1CLKSRC_Pos)
#define I2C2_PLL (0x0 << I2CCLK_I2C2CLKSRC_Pos)
#define I2C2_RC25M (0x1 << I2CCLK_I2C2CLKSRC_Pos)
#define I2C3_PLL (0x0 << I2CCLK_I2C3CLKSRC_Pos)
#define I2C3_RC25M (0x1 << I2CCLK_I2C3CLKSRC_Pos)
#define I2C4_PLL (0x0 << I2CCLK_I2C4CLKSRC_Pos)
#define I2C4_RC25M (0x1 << I2CCLK_I2C4CLKSRC_Pos)
#define I2C5_PLL (0x0 << I2CCLK_I2C5CLKSRC_Pos)
#define I2C5_RC25M (0x1 << I2CCLK_I2C5CLKSRC_Pos)
#define I2C6_PLL (0x0 << I2CCLK_I2C6CLKSRC_Pos)
#define I2C6_RC25M (0x1 << I2CCLK_I2C6CLKSRC_Pos)
#define I2C7_PLL (0x0 << I2CCLK_I2C7CLKSRC_Pos)
#define I2C7_RC25M (0x1 << I2CCLK_I2C7CLKSRC_Pos)
#define I2C0_CLKDIV1 (0 << I2CCLK_I2C0CLKDIV_Pos)
#define I2C0_CLKDIV2 (1 << I2CCLK_I2C0CLKDIV_Pos)
#define I2C0_CLKDIV4 (2 << I2CCLK_I2C0CLKDIV_Pos)
#define I2C0_CLKDIV8 (3 << I2CCLK_I2C0CLKDIV_Pos)
#define I2C1_CLKDIV1 (0 << I2CCLK_I2C1CLKDIV_Pos)
#define I2C1_CLKDIV2 (1 << I2CCLK_I2C1CLKDIV_Pos)
#define I2C1_CLKDIV4 (2 << I2CCLK_I2C1CLKDIV_Pos)
#define I2C1_CLKDIV8 (3 << I2CCLK_I2C1CLKDIV_Pos)
#define I2C2_CLKDIV1 (0 << I2CCLK_I2C2CLKDIV_Pos)
#define I2C2_CLKDIV2 (1 << I2CCLK_I2C2CLKDIV_Pos)
#define I2C2_CLKDIV4 (2 << I2CCLK_I2C2CLKDIV_Pos)
#define I2C2_CLKDIV8 (3 << I2CCLK_I2C2CLKDIV_Pos)
#define I2C3_CLKDIV1 (0 << I2CCLK_I2C3CLKDIV_Pos)
#define I2C3_CLKDIV2 (1 << I2CCLK_I2C3CLKDIV_Pos)
#define I2C3_CLKDIV4 (2 << I2CCLK_I2C3CLKDIV_Pos)
#define I2C3_CLKDIV8 (3 << I2CCLK_I2C3CLKDIV_Pos)
#define I2C4_CLKDIV1 (0 << I2CCLK_I2C4CLKDIV_Pos)
#define I2C4_CLKDIV2 (1 << I2CCLK_I2C4CLKDIV_Pos)
#define I2C4_CLKDIV4 (2 << I2CCLK_I2C4CLKDIV_Pos)
#define I2C4_CLKDIV8 (3 << I2CCLK_I2C4CLKDIV_Pos)
#define I2C5_CLKDIV1 (0 << I2CCLK_I2C5CLKDIV_Pos)
#define I2C5_CLKDIV2 (1 << I2CCLK_I2C5CLKDIV_Pos)
#define I2C5_CLKDIV4 (2 << I2CCLK_I2C5CLKDIV_Pos)
#define I2C5_CLKDIV8 (3 << I2CCLK_I2C5CLKDIV_Pos)
#define I2C6_CLKDIV1 (0 << I2CCLK_I2C6CLKDIV_Pos)
#define I2C6_CLKDIV2 (1 << I2CCLK_I2C6CLKDIV_Pos)
#define I2C6_CLKDIV4 (2 << I2CCLK_I2C6CLKDIV_Pos)
#define I2C6_CLKDIV8 (3 << I2CCLK_I2C6CLKDIV_Pos)
#define I2C7_CLKDIV1 (0 << I2CCLK_I2C7CLKDIV_Pos)
#define I2C7_CLKDIV2 (1 << I2CCLK_I2C7CLKDIV_Pos)
#define I2C7_CLKDIV4 (2 << I2CCLK_I2C7CLKDIV_Pos)
#define I2C7_CLKDIV8 (3 << I2CCLK_I2C7CLKDIV_Pos)
#define UART0_CLKPWR (UARTCLK_PWR_Pos)
#define UART0_RC25M (0x0 << UARTCLK_SRC_Pos)
#define UART0_PLL (0x1 << UARTCLK_SRC_Pos)
#define UART0_CLKDIV1 (0 << UARTCLK_DIV_Pos)
#define UART0_CLKDIV2 (1 << UARTCLK_DIV_Pos)
#define UART0_CLKDIV4 (2 << UARTCLK_DIV_Pos)
#define UART0_CLKDIV8 (3 << UARTCLK_DIV_Pos)
#define ADC0_CLKPWR (ADCCLK_PWR_Pos)
#define ADC0_RC25M (0x0 << ADCCLK_SRC_Pos)
#define ADC0_PLL (0x1 << ADCCLK_SRC_Pos)
#define ADC0_CLKDIV1 (0 << ADCCLK_DIV_Pos)
#define ADC0_CLKDIV2 (1 << ADCCLK_DIV_Pos)
#define ADC0_CLKDIV3 (2 << ADCCLK_DIV_Pos)
#define ADC0_CLKDIV4 (3 << ADCCLK_DIV_Pos)
#define ADC0_CLKDIV6 (4 << ADCCLK_DIV_Pos)
#define ADC0_CLKDIV8 (5 << ADCCLK_DIV_Pos)
#define PERIPH_GRP0_GPIO_CLKPWR (PERICLKPWR0_GPIOCLKPWR_Pos)
#define PERIPH_GRP0_TACH0_CLKPWR (PERICLKPWR0_TACHO0CLKPWR_Pos)
#define PERIPH_GRP0_TACH1_CLKPWR (PERICLKPWR0_TACHO1CLKPWR_Pos)
#define PERIPH_GRP0_TACH2_CLKPWR (PERICLKPWR0_TACHO2CLKPWR_Pos)
#define PERIPH_GRP0_TACH3_CLKPWR (PERICLKPWR0_TACHO3CLKPWR_Pos)
#define PERIPH_GRP0_PS2_CLKPWR (PERICLKPWR0_PS2CLKPWR_Pos)
#define PERIPH_GRP0_KBM_CLKPWR (PERICLKPWR0_KBMCLKPWR_Pos)
#define PERIPH_GRP0_PECI_CLKPWR (PERICLKPWR0_PECICLKPWR_Pos)
#define PERIPH_GRP0_LEDPWM0_CLKPWR (PERICLKPWR0_PL0CLKPWR_Pos)
#define PERIPH_GRP0_LEDPWM1_CLKPWR (PERICLKPWR0_PL1CLKPWR_Pos)
#define PERIPH_GRP0_PWM0_CLKPWR (PERICLKPWR0_PWM0CLKPWR_Pos)
#define PERIPH_GRP0_PWM1_CLKPWR (PERICLKPWR0_PWM1CLKPWR_Pos)
#define PERIPH_GRP0_PWM2_CLKPWR (PERICLKPWR0_PWM2CLKPWR_Pos)
#define PERIPH_GRP0_PWM3_CLKPWR (PERICLKPWR0_PWM3CLKPWR_Pos)
#define PERIPH_GRP0_PWM4_CLKPWR (PERICLKPWR0_PWM4CLKPWR_Pos)
#define PERIPH_GRP0_PWM5_CLKPWR (PERICLKPWR0_PWM5CLKPWR_Pos)
#define PERIPH_GRP0_PWM6_CLKPWR (PERICLKPWR0_PWM6CLKPWR_Pos)
#define PERIPH_GRP0_PWM7_CLKPWR (PERICLKPWR0_PWM7CLKPWR_Pos)
#define PERIPH_GRP0_PWM8_CLKPWR (PERICLKPWR0_PWM8CLKPWR_Pos)
#define PERIPH_GRP0_PWM9_CLKPWR (PERICLKPWR0_PWM9CLKPWR_Pos)
#define PERIPH_GRP0_PWM10_CLKPWR (PERICLKPWR0_PWM10CLKPWR_Pos)
#define PERIPH_GRP0_PWM11_CLKPWR (PERICLKPWR0_PWM11CLKPWR_Pos)
#define PERIPH_GRP0_ESPI_CLKPWR (PERICLKPWR0_ESPICLKPWR_Pos)
#define PERIPH_GRP0_KBC_CLKPWR (PERICLKPWR0_KBCCLKPWR_Pos)
#define PERIPH_GRP0_ACPI_CLKPWR (PERICLKPWR0_ACPICLKPWR_Pos)
#define PERIPH_GRP0_PMPORT0_CLKPWR (PERICLKPWR0_PMPORT0CLKPWR_Pos)
#define PERIPH_GRP0_PMPORT1_CLKPWR (PERICLKPWR0_PMPORT1CLKPWR_Pos)
#define PERIPH_GRP0_PMPORT2_CLKPWR (PERICLKPWR0_PMPORT2CLKPWR_Pos)
#define PERIPH_GRP0_PMPORT3_CLKPWR (PERICLKPWR0_PMPORT3CLKPWR_Pos)
#define PERIPH_GRP0_P80_CLKPWR (PERICLKPWR0_P80CLKPWR_Pos)
#define PERIPH_GRP0_EMI0_CLKPWR (PERICLKPWR0_EMI0CLKPWR_Pos)
#define PERIPH_GRP0_EMI1_CLKPWR (PERICLKPWR0_EMI1CLKPWR_Pos)
#define PERIPH_GRP1_EMI2_CLKPWR (PERICLKPWR1_EMI2CLKPWR_Pos)
#define PERIPH_GRP1_EMI3_CLKPWR (PERICLKPWR1_EMI3CLKPWR_Pos)
#define PERIPH_GRP1_EMI4_CLKPWR (PERICLKPWR1_EMI4CLKPWR_Pos)
#define PERIPH_GRP1_EMI5_CLKPWR (PERICLKPWR1_EMI5CLKPWR_Pos)
#define PERIPH_GRP1_EMI6_CLKPWR (PERICLKPWR1_EMI6CLKPWR_Pos)
#define PERIPH_GRP1_EMI7_CLKPWR (PERICLKPWR1_EMI7CLKPWR_Pos)
#define PERIPH_GRP1_I3C0_CLKPWR (PERICLKPWR1_I3C0CLKPWR_Pos)
#define PERIPH_GRP1_I3C1_CLKPWR (PERICLKPWR1_I3C1CLKPWR_Pos)
#define PERIPH_GRP1_I2CAUTO_CLKPWR (PERICLKPWR1_I2CAUTOCLKPWR_Pos)
#define PERIPH_GRP1_MC_CLKPWR (PERICLKPWR1_MCCLKPWR_Pos)
#define PERIPH_GRP1_TMR0_CLKPWR (PERICLKPWR1_TMR0CLKPWR_Pos)
#define PERIPH_GRP1_TMR1_CLKPWR (PERICLKPWR1_TMR1CLKPWR_Pos)
#define PERIPH_GRP1_TMR2_CLKPWR (PERICLKPWR1_TMR2CLKPWR_Pos)
#define PERIPH_GRP1_TMR3_CLKPWR (PERICLKPWR1_TMR3CLKPWR_Pos)
#define PERIPH_GRP1_TMR4_CLKPWR (PERICLKPWR1_TMR4CLKPWR_Pos)
#define PERIPH_GRP1_TMR5_CLKPWR (PERICLKPWR1_TMR5CLKPWR_Pos)
#define PERIPH_GRP1_RTMR_CLKPWR (PERICLKPWR1_RTMRCLKPWR_Pos)
#define PERIPH_GRP1_SLWTMR0_CLKPWR (PERICLKPWR1_SLWTMR0CLKPWR_Pos)
#define PERIPH_GRP1_SLWTMR1_CLKPWR (PERICLKPWR1_SLWTMR1CLKPWR_Pos)
#define PERIPH_GRP2_RTC_CLKPWR (PERICLKPWR2_RTCCLKPWR_Pos)
#define PERIPH_GRP2_WDT_CLKPWR (PERICLKPWR2_WDTCLKPWR_Pos)
#define PERIPH_GRP2_WDTPWRBTN_CLKPWR (PERICLKPWR2_PWRBTNCLKPWR_Pos)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_ */

335
soc/realtek/ec/rts5912/reg/reg_system.h Normal file
View file

@ -0,0 +1,335 @@
/*
* Copyright (c) 2023 Realtek, SIBG-SD7
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_SYSTEM_H
#define ZEPHYR_SOC_REALTEK_RTS5912_REG_SYSTEM_H
/*
* @brief System Controller (SYSTEM)
*/
typedef struct {
union {
volatile uint32_t I3CCLK;
volatile uint32_t TMRRST;
};
volatile uint32_t I2CCLK;
volatile uint32_t TMRCLK;
volatile uint32_t PERICLKPWR0;
volatile uint32_t UARTCLK;
volatile uint32_t SYSCLK;
volatile uint32_t ADCCLK;
volatile uint32_t PERICLKPWR1;
volatile const uint32_t RESERVED[24];
volatile uint32_t SLPCTRL;
volatile const uint32_t RESERVED1[7];
volatile uint32_t VIVOCTRL;
volatile uint32_t LDOCTRL;
volatile uint32_t RC25MCTRL;
volatile uint32_t PLLCTRL;
volatile const uint32_t RESERVED2[12];
volatile uint32_t RC32KCTRL;
volatile const uint32_t RESERVED3;
volatile uint32_t PERICLKPWR2;
} SYSTEM_Type;
/* I3CCLK */
#define SYSTEM_I3CCLK_I3C0DIV_Pos (0UL)
#define SYSTEM_I3CCLK_I3C0DIV_Msk GENMASK(1, 0)
#define SYSTEM_I3CCLK_I3C1DIV_Pos (2UL)
#define SYSTEM_I3CCLK_I3C1DIV_Msk GENMASK(3, 2)
/* TMRRST */
#define SYSTEM_TMRRST_TMR0RST_Pos (4UL)
#define SYSTEM_TMRRST_TMR0RST_Msk BIT(SYSTEM_TMRRST_TMR0RST_Pos)
#define SYSTEM_TMRRST_TMR1RST_Pos (5UL)
#define SYSTEM_TMRRST_TMR1RST_Msk BIT(SYSTEM_TMRRST_TMR1RST_Pos)
#define SYSTEM_TMRRST_TMR2RST_Pos (6UL)
#define SYSTEM_TMRRST_TMR2RST_Msk BIT(SYSTEM_TMRRST_TMR2RST_Pos)
#define SYSTEM_TMRRST_TMR3RST_Pos (7UL)
#define SYSTEM_TMRRST_TMR3RST_Msk BIT(SYSTEM_TMRRST_TMR3RST_Pos)
#define SYSTEM_TMRRST_TMR4RST_Pos (8UL)
#define SYSTEM_TMRRST_TMR4RST_Msk BIT(SYSTEM_TMRRST_TMR4RST_Pos)
#define SYSTEM_TMRRST_TMR5RST_Pos (9UL)
#define SYSTEM_TMRRST_TMR5RST_Msk BIT(SYSTEM_TMRRST_TMR5RST_Pos)
/* I2CCLK */
#define SYSTEM_I2CCLK_I2C0CLKPWR_Pos (0UL)
#define SYSTEM_I2CCLK_I2C0CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C0CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C0CLKSRC_Pos (1UL)
#define SYSTEM_I2CCLK_I2C0CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C0CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C0CLKDIV_Pos (2UL)
#define SYSTEM_I2CCLK_I2C0CLKDIV_Msk GENMASK(3, 2)
#define SYSTEM_I2CCLK_I2C1CLKPWR_Pos (4UL)
#define SYSTEM_I2CCLK_I2C1CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C1CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C1CLKSRC_Pos (5UL)
#define SYSTEM_I2CCLK_I2C1CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C1CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C1CLKDIV_Pos (6UL)
#define SYSTEM_I2CCLK_I2C1CLKDIV_Msk GENMASK(7, 6)
#define SYSTEM_I2CCLK_I2C2CLKPWR_Pos (8UL)
#define SYSTEM_I2CCLK_I2C2CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C2CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C2CLKSRC_Pos (9UL)
#define SYSTEM_I2CCLK_I2C2CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C2CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C2CLKDIV_Pos (10UL)
#define SYSTEM_I2CCLK_I2C2CLKDIV_Msk GENMASK(11, 10)
#define SYSTEM_I2CCLK_I2C3CLKPWR_Pos (12UL)
#define SYSTEM_I2CCLK_I2C3CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C3CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C3CLKSRC_Pos (13UL)
#define SYSTEM_I2CCLK_I2C3CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C3CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C3CLKDIV_Pos (14UL)
#define SYSTEM_I2CCLK_I2C3CLKDIV_Msk GENMASK(15, 14)
#define SYSTEM_I2CCLK_I2C4CLKPWR_Pos (16UL)
#define SYSTEM_I2CCLK_I2C4CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C4CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C4CLKSRC_Pos (17UL)
#define SYSTEM_I2CCLK_I2C4CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C4CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C4CLKDIV_Pos (18UL)
#define SYSTEM_I2CCLK_I2C4CLKDIV_Msk GENMASK(19, 18)
#define SYSTEM_I2CCLK_I2C5CLKPWR_Pos (20UL)
#define SYSTEM_I2CCLK_I2C5CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C5CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C5CLKSRC_Pos (21UL)
#define SYSTEM_I2CCLK_I2C5CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C5CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C5CLKDIV_Pos (22UL)
#define SYSTEM_I2CCLK_I2C5CLKDIV_Msk GENMASK(23, 22)
#define SYSTEM_I2CCLK_I2C6CLKPWR_Pos (24UL)
#define SYSTEM_I2CCLK_I2C6CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C6CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C6CLKSRC_Pos (25UL)
#define SYSTEM_I2CCLK_I2C6CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C6CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C6CLKDIV_Pos (26UL)
#define SYSTEM_I2CCLK_I2C6CLKDIV_Msk GENMASK(27, 26)
#define SYSTEM_I2CCLK_I2C7CLKPWR_Pos (28UL)
#define SYSTEM_I2CCLK_I2C7CLKPWR_Msk BIT(SYSTEM_I2CCLK_I2C7CLKPWR_Pos)
#define SYSTEM_I2CCLK_I2C7CLKSRC_Pos (29UL)
#define SYSTEM_I2CCLK_I2C7CLKSRC_Msk BIT(SYSTEM_I2CCLK_I2C7CLKSRC_Pos)
#define SYSTEM_I2CCLK_I2C7CLKDIV_Pos (30UL)
#define SYSTEM_I2CCLK_I2C7CLKDIV_Msk GENMASK(31, 30)
/* TMRCLK */
#define SYSTEM_TMRCLK_TMR0DIV_Pos (0UL)
#define SYSTEM_TMRCLK_TMR0DIV_Msk GENMASK(3, 0)
#define SYSTEM_TMRCLK_TMR1DIV_Pos (4UL)
#define SYSTEM_TMRCLK_TMR1DIV_Msk GENMASK(7, 4)
#define SYSTEM_TMRCLK_TMR2DIV_Pos (8UL)
#define SYSTEM_TMRCLK_TMR2DIV_Msk GENMASK(11, 8)
#define SYSTEM_TMRCLK_TMR3DIV_Pos (12UL)
#define SYSTEM_TMRCLK_TMR3DIV_Msk GENMASK(15, 12)
#define SYSTEM_TMRCLK_TMR4DIV_Pos (16UL)
#define SYSTEM_TMRCLK_TMR4DIV_Msk GENMASK(19, 16)
#define SYSTEM_TMRCLK_TMR5DIV_Pos (20UL)
#define SYSTEM_TMRCLK_TMR5DIV_Msk GENMASK(23, 20)
#define SYSTEM_TMRCLK_TMR0PAUSE_Pos (24UL)
#define SYSTEM_TMRCLK_TMR0PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR0PAUSE_Pos)
#define SYSTEM_TMRCLK_TMR1PAUSE_Pos (25UL)
#define SYSTEM_TMRCLK_TMR1PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR1PAUSE_Pos)
#define SYSTEM_TMRCLK_TMR2PAUSE_Pos (26UL)
#define SYSTEM_TMRCLK_TMR2PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR2PAUSE_Pos)
#define SYSTEM_TMRCLK_TMR3PAUSE_Pos (27UL)
#define SYSTEM_TMRCLK_TMR3PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR3PAUSE_Pos)
#define SYSTEM_TMRCLK_TMR4PAUSE_Pos (28UL)
#define SYSTEM_TMRCLK_TMR4PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR4PAUSE_Pos)
#define SYSTEM_TMRCLK_TMR5PAUSE_Pos (29UL)
#define SYSTEM_TMRCLK_TMR5PAUSE_Msk BIT(SYSTEM_TMRCLK_TMR5PAUSE_Pos)
/* PERICLKPWR0 */
#define SYSTEM_PERICLKPWR0_GPIOCLKPWR_Pos (0UL)
#define SYSTEM_PERICLKPWR0_GPIOCLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_GPIOCLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_TACHO0CLKPWR_Pos (1UL)
#define SYSTEM_PERICLKPWR0_TACHO0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_TACHO1CLKPWR_Pos (2UL)
#define SYSTEM_PERICLKPWR0_TACHO1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO1CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_TACHO2CLKPWR_Pos (3UL)
#define SYSTEM_PERICLKPWR0_TACHO2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO2CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_TACHO3CLKPWR_Pos (4UL)
#define SYSTEM_PERICLKPWR0_TACHO3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_TACHO3CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PS2CLKPWR_Pos (5UL)
#define SYSTEM_PERICLKPWR0_PS2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PS2CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_KBMCLKPWR_Pos (6UL)
#define SYSTEM_PERICLKPWR0_KBMCLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_KBMCLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PECICLKPWR_Pos (7UL)
#define SYSTEM_PERICLKPWR0_PECICLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PECICLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PL0CLKPWR_Pos (8UL)
#define SYSTEM_PERICLKPWR0_PL0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PL0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PL1CLKPWR_Pos (9UL)
#define SYSTEM_PERICLKPWR0_PL1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PL1CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM0CLKPWR_Pos (10UL)
#define SYSTEM_PERICLKPWR0_PWM0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM1CLKPWR_Pos (11UL)
#define SYSTEM_PERICLKPWR0_PWM1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM1CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM2CLKPWR_Pos (12UL)
#define SYSTEM_PERICLKPWR0_PWM2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM2CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM3CLKPWR_Pos (13UL)
#define SYSTEM_PERICLKPWR0_PWM3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM3CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM4CLKPWR_Pos (14UL)
#define SYSTEM_PERICLKPWR0_PWM4CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM4CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM5CLKPWR_Pos (15UL)
#define SYSTEM_PERICLKPWR0_PWM5CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM5CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM6CLKPWR_Pos (16UL)
#define SYSTEM_PERICLKPWR0_PWM6CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM6CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM7CLKPWR_Pos (17UL)
#define SYSTEM_PERICLKPWR0_PWM7CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM7CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM8CLKPWR_Pos (18UL)
#define SYSTEM_PERICLKPWR0_PWM8CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM8CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM9CLKPWR_Pos (19UL)
#define SYSTEM_PERICLKPWR0_PWM9CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM9CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM10CLKPWR_Pos (20UL)
#define SYSTEM_PERICLKPWR0_PWM10CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM10CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PWM11CLKPWR_Pos (21UL)
#define SYSTEM_PERICLKPWR0_PWM11CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PWM11CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_ESPICLKPWR_Pos (22UL)
#define SYSTEM_PERICLKPWR0_ESPICLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_ESPICLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_KBCCLKPWR_Pos (23UL)
#define SYSTEM_PERICLKPWR0_KBCCLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_KBCCLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_ACPICLKPWR_Pos (24UL)
#define SYSTEM_PERICLKPWR0_ACPICLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_ACPICLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PMPORT0CLKPWR_Pos (25UL)
#define SYSTEM_PERICLKPWR0_PMPORT0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PMPORT1CLKPWR_Pos (26UL)
#define SYSTEM_PERICLKPWR0_PMPORT1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT1CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PMPORT2CLKPWR_Pos (27UL)
#define SYSTEM_PERICLKPWR0_PMPORT2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT2CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_PMPORT3CLKPWR_Pos (28UL)
#define SYSTEM_PERICLKPWR0_PMPORT3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_PMPORT3CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_P80CLKPWR_Pos (29UL)
#define SYSTEM_PERICLKPWR0_P80CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_P80CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_EMI0CLKPWR_Pos (30UL)
#define SYSTEM_PERICLKPWR0_EMI0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_EMI0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR0_EMI1CLKPWR_Pos (31UL)
#define SYSTEM_PERICLKPWR0_EMI1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR0_EMI1CLKPWR_Pos)
/* UARTCLK */
#define SYSTEM_UARTCLK_PWR_Pos (0UL)
#define SYSTEM_UARTCLK_PWR_Msk BIT(SYSTEM_UARTCLK_PWR_Pos)
#define SYSTEM_UARTCLK_SRC_Pos (1UL)
#define SYSTEM_UARTCLK_SRC_Msk BIT(SYSTEM_UARTCLK_SRC_Pos)
#define SYSTEM_UARTCLK_DIV_Pos (2UL)
#define SYSTEM_UARTCLK_DIV_Msk GENMASK(3, 2)
/* SYSCLK */
#define SYSTEM_SYSCLK_SRC_Pos (1UL)
#define SYSTEM_SYSCLK_SRC_Msk BIT(SYSTEM_SYSCLK_SRC_Pos)
#define SYSTEM_SYSCLK_DIV_Pos (2UL)
#define SYSTEM_SYSCLK_DIV_Msk BIT(SYSTEM_SYSCLK_DIV_Pos)
/* ADCCLK */
#define SYSTEM_ADCCLK_PWR_Pos (0UL)
#define SYSTEM_ADCCLK_PWR_Msk BIT(SYSTEM_ADCCLK_PWR_Pos)
#define SYSTEM_ADCCLK_SRC_Pos (1UL)
#define SYSTEM_ADCCLK_SRC_Msk BIT(SYSTEM_ADCCLK_SRC_Pos)
#define SYSTEM_ADCCLK_DIV_Pos (2UL)
#define SYSTEM_ADCCLK_DIV_Msk GENMASK(4, 2)
/* PERICLKPWR1 */
#define SYSTEM_PERICLKPWR1_EMI2CLKPWR_Pos (0UL)
#define SYSTEM_PERICLKPWR1_EMI2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI2CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_EMI3CLKPWR_Pos (1UL)
#define SYSTEM_PERICLKPWR1_EMI3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI3CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_EMI4CLKPWR_Pos (2UL)
#define SYSTEM_PERICLKPWR1_EMI4CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI4CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_EMI5CLKPWR_Pos (3UL)
#define SYSTEM_PERICLKPWR1_EMI5CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI5CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_EMI6CLKPWR_Pos (4UL)
#define SYSTEM_PERICLKPWR1_EMI6CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI6CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_EMI7CLKPWR_Pos (5UL)
#define SYSTEM_PERICLKPWR1_EMI7CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_EMI7CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_I3C0CLKPWR_Pos (9UL)
#define SYSTEM_PERICLKPWR1_I3C0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_I3C0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_I3C1CLKPWR_Pos (10UL)
#define SYSTEM_PERICLKPWR1_I3C1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_I3C1CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_I2CAUTOCLKPWR_Pos (11UL)
#define SYSTEM_PERICLKPWR1_I2CAUTOCLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_I2CAUTOCLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_MCCLKPWR_Pos (12UL)
#define SYSTEM_PERICLKPWR1_MCCLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_MCCLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_TMR0CLKPWR_Pos (13UL)
#define SYSTEM_PERICLKPWR1_TMR0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_TMR1CLKPWR_Pos (14UL)
#define SYSTEM_PERICLKPWR1_TMR1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR1CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_TMR2CLKPWR_Pos (15UL)
#define SYSTEM_PERICLKPWR1_TMR2CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR2CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_TMR3CLKPWR_Pos (16UL)
#define SYSTEM_PERICLKPWR1_TMR3CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR3CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_TMR4CLKPWR_Pos (17UL)
#define SYSTEM_PERICLKPWR1_TMR4CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR4CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_TMR5CLKPWR_Pos (18UL)
#define SYSTEM_PERICLKPWR1_TMR5CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_TMR5CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_RTMRCLKPWR_Pos (19UL)
#define SYSTEM_PERICLKPWR1_RTMRCLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_RTMRCLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Pos (20UL)
#define SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Pos)
#define SYSTEM_PERICLKPWR1_SLWTMR1CLKPWR_Pos (21UL)
#define SYSTEM_PERICLKPWR1_SLWTMR1CLKPWR_Msk BIT(SYSTEM_PERICLKPWR1_SLWTMR1CLKPWR_Pos)
/* SLPCTRL */
#define SYSTEM_SLPCTRL_SLPMDSEL_Pos (1UL)
#define SYSTEM_SLPCTRL_SLPMDSEL_Msk BIT(SYSTEM_SLPCTRL_SLPMDSEL_Pos)
#define SYSTEM_SLPCTRL_ESPIWKEN_Pos (2UL)
#define SYSTEM_SLPCTRL_ESPIWKEN_Msk BIT(SYSTEM_SLPCTRL_ESPIWKEN_Pos)
#define SYSTEM_SLPCTRL_PS2WKEN_Pos (3UL)
#define SYSTEM_SLPCTRL_PS2WKEN_Msk BIT(SYSTEM_SLPCTRL_PS2WKEN_Pos)
#define SYSTEM_SLPCTRL_I2CWKEN_Pos (4UL)
#define SYSTEM_SLPCTRL_I2CWKEN_Msk BIT(SYSTEM_SLPCTRL_I2CWKEN_Pos)
#define SYSTEM_SLPCTRL_GPIOWKEN_Pos (5UL)
#define SYSTEM_SLPCTRL_GPIOWKEN_Msk BIT(SYSTEM_SLPCTRL_GPIOWKEN_Pos)
/* VIVOCTRL */
#define SYSTEM_VIVOCTRL_VIN0MD_Pos (0UL)
#define SYSTEM_VIVOCTRL_VIN0MD_Msk BIT(SYSTEM_VIVOCTRL_VIN0MD_Pos)
#define SYSTEM_VIVOCTRL_VIN1MD_Pos (1UL)
#define SYSTEM_VIVOCTRL_VIN1MD_Msk BIT(SYSTEM_VIVOCTRL_VIN1MD_Pos)
#define SYSTEM_VIVOCTRL_VIN2MD_Pos (2UL)
#define SYSTEM_VIVOCTRL_VIN2MD_Msk BIT(SYSTEM_VIVOCTRL_VIN2MD_Pos)
#define SYSTEM_VIVOCTRL_VIN3MD_Pos (3UL)
#define SYSTEM_VIVOCTRL_VIN3MD_Msk BIT(SYSTEM_VIVOCTRL_VIN3MD_Pos)
#define SYSTEM_VIVOCTRL_VIN4MD_Pos (4UL)
#define SYSTEM_VIVOCTRL_VIN4MD_Msk BIT(SYSTEM_VIVOCTRL_VIN4MD_Pos)
#define SYSTEM_VIVOCTRL_VIN5MD_Pos (5UL)
#define SYSTEM_VIVOCTRL_VIN5MD_Msk BIT(SYSTEM_VIVOCTRL_VIN5MD_Pos)
#define SYSTEM_VIVOCTRL_VIN0STS_Pos (6UL)
#define SYSTEM_VIVOCTRL_VIN0STS_Msk BIT(SYSTEM_VIVOCTRL_VIN0STS_Pos)
#define SYSTEM_VIVOCTRL_VIN1STS_Pos (7UL)
#define SYSTEM_VIVOCTRL_VIN1STS_Msk BIT(SYSTEM_VIVOCTRL_VIN1STS_Pos)
#define SYSTEM_VIVOCTRL_VIN2STS_Pos (8UL)
#define SYSTEM_VIVOCTRL_VIN2STS_Msk BIT(SYSTEM_VIVOCTRL_VIN2STS_Pos)
#define SYSTEM_VIVOCTRL_VIN3STS_Pos (9UL)
#define SYSTEM_VIVOCTRL_VIN3STS_Msk BIT(SYSTEM_VIVOCTRL_VIN3STS_Pos)
#define SYSTEM_VIVOCTRL_VIN4STS_Pos (10UL)
#define SYSTEM_VIVOCTRL_VIN4STS_Msk BIT(SYSTEM_VIVOCTRL_VIN4STS_Pos)
#define SYSTEM_VIVOCTRL_VIN5STS_Pos (11UL)
#define SYSTEM_VIVOCTRL_VIN5STS_Msk BIT(SYSTEM_VIVOCTRL_VIN5STS_Pos)
#define SYSTEM_VIVOCTRL_VIN0POL_Pos (12UL)
#define SYSTEM_VIVOCTRL_VIN0POL_Msk BIT(SYSTEM_VIVOCTRL_VIN0POL_Pos)
#define SYSTEM_VIVOCTRL_VIN1POL_Pos (13UL)
#define SYSTEM_VIVOCTRL_VIN1POL_Msk BIT(SYSTEM_VIVOCTRL_VIN1POL_Pos)
#define SYSTEM_VIVOCTRL_VIN2POL_Pos (14UL)
#define SYSTEM_VIVOCTRL_VIN2POL_Msk BIT(SYSTEM_VIVOCTRL_VIN2POL_Pos)
#define SYSTEM_VIVOCTRL_VIN3POL_Pos (15UL)
#define SYSTEM_VIVOCTRL_VIN3POL_Msk BIT(SYSTEM_VIVOCTRL_VIN3POL_Pos)
#define SYSTEM_VIVOCTRL_VIN4POL_Pos (16UL)
#define SYSTEM_VIVOCTRL_VIN4POL_Msk BIT(SYSTEM_VIVOCTRL_VIN4POL_Pos)
#define SYSTEM_VIVOCTRL_VIN5POL_Pos (17UL)
#define SYSTEM_VIVOCTRL_VIN5POL_Msk BIT(SYSTEM_VIVOCTRL_VIN5POL_Pos)
#define SYSTEM_VIVOCTRL_REGWREN_Pos (30UL)
#define SYSTEM_VIVOCTRL_REGWREN_Msk BIT(SYSTEM_VIVOCTRL_REGWREN_Pos)
#define SYSTEM_VIVOCTRL_VOUTMD_Pos (31UL)
#define SYSTEM_VIVOCTRL_VOUTMD_Msk BIT(SYSTEM_VIVOCTRL_VOUTMD_Pos)
/* LDOCTRL */
#define SYSTEM_LDOCTRL_LDO2EN_Pos (3UL)
#define SYSTEM_LDOCTRL_LDO2EN_Msk BIT(SYSTEM_LDOCTRL_LDO2EN_Pos)
#define SYSTEM_LDOCTRL_LDO3EN_Pos (7UL)
#define SYSTEM_LDOCTRL_LDO3EN_Msk BIT(SYSTEM_LDOCTRL_LDO3EN_Pos)
/* RC25MCTRL */
#define SYSTEM_RC25MCTRL_EN_Pos (0UL)
#define SYSTEM_RC25MCTRL_EN_Msk BIT(SYSTEM_RC25MCTRL_EN_Pos)
#define SYSTEM_RC25MCTRL_CALCURR_Pos (1UL)
#define SYSTEM_RC25MCTRL_CALCURR_Msk GENMASK(7, 1)
/* PLLCTRL */
#define SYSTEM_PLLCTRL_EN_Pos (0UL)
#define SYSTEM_PLLCTRL_EN_Msk BIT(SYSTEM_PLLCTRL_EN_Pos)
#define SYSTEM_PLLCTRL_RDY_Pos (19UL)
#define SYSTEM_PLLCTRL_RDY_Msk BIT(SYSTEM_PLLCTRL_RDY_Pos)
/* RC32KCTRL */
#define SYSTEM_RC32KCTRL_EN_Pos (0UL)
#define SYSTEM_RC32KCTRL_EN_Msk BIT(SYSTEM_RC32KCTRL_EN_Pos)
#define SYSTEM_RC32KCTRL_CAL_Pos (1UL)
#define SYSTEM_RC32KCTRL_CAL_Msk GENMASK(7, 1)
/* PERICLKPWR2 */
#define SYSTEM_PERICLKPWR2_RTCCLKPWR_Pos (0UL)
#define SYSTEM_PERICLKPWR2_RTCCLKPWR_Msk BIT(SYSTEM_PERICLKPWR2_RTCCLKPWR_Pos)
#define SYSTEM_PERICLKPWR2_WDTCLKPWR_Pos (1UL)
#define SYSTEM_PERICLKPWR2_WDTCLKPWR_Msk BIT(SYSTEM_PERICLKPWR2_WDTCLKPWR_Pos)
#define SYSTEM_PERICLKPWR2_PWRBTNCLKPWR_Pos (2UL)
#define SYSTEM_PERICLKPWR2_PWRBTNCLKPWR_Msk BIT(SYSTEM_PERICLKPWR2_PWRBTNCLKPWR_Pos)
#define SYSTEM_PERICLKPWR2_RC32KSRC_Pos (30UL)
#define SYSTEM_PERICLKPWR2_RC32KSRC_Msk GENMASK(31, 30)
#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_SYSTEM_H */