soc: nxp: imxrt: imxrt7xx: add rt7xx soc files
add rt7xx files related to soc support basic clock enablement add common/Kconfig.xspi_xip file Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This commit is contained in:
parent
87579e8c78
commit
a6f2a0fa8a
14 changed files with 571 additions and 2 deletions
42
soc/nxp/common/Kconfig.xspi_xip
Normal file
42
soc/nxp/common/Kconfig.xspi_xip
Normal file
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@ -0,0 +1,42 @@
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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DT_CHOSEN_Z_FLASH := zephyr,flash
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DT_COMPAT_XSPI := nxp,xspi
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DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
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DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
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DT_FLASH_PARENT_IS_XSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_XSPI))
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DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
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if $(DT_FLASH_PARENT_IS_XSPI)
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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config FLASH_SIZE
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default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb)
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config FLASH_MCUX_XSPI_XIP
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bool
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default $(DT_FLASH_PARENT_IS_XSPI)
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select XIP
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help
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Allows the soc to safely initialize the clocks for the
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XSpi when planning to execute code in XSpi Memory.
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if FLASH_MCUX_XSPI_XIP
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config CODE_DATA_RELOCATION_SRAM
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default y
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config FLASH_MCUX_XSPI_XIP_MEM
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string
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prompt "Xspi drivers memory location"
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default "RAM"
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help
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Select the location to run the XSPI drivers when using
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the flash API.
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endif
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@ -69,7 +69,7 @@ if(CONFIG_SOC_SERIES_IMXRT118X)
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zephyr_compile_definitions(XIP_EXTERNAL_FLASH)
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endif()
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if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX)
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if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX OR CONFIG_SOC_SERIES_IMXRT7XX)
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zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld)
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zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER SECTIONS usb.ld)
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endif()
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@ -10,7 +10,13 @@ if SOC_FAMILY_NXP_IMXRT
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# can override the defaults given here
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rsource "*/Kconfig"
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if DT_HAS_NXP_IMX_FLEXSPI_ENABLED
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rsource "../common/Kconfig.flexspi_xip"
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endif
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if DT_HAS_NXP_XSPI_ENABLED
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rsource "../common/Kconfig.xspi_xip"
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endif
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# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
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# should be set elsewhere, since the determination of which SOC core
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@ -29,8 +35,13 @@ rsource "../common/Kconfig.rom_loader"
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choice BOOT_DEVICE
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prompt "Boot device"
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default BOOT_XSPI_NOR if DT_HAS_NXP_XSPI_ENABLED
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default BOOT_FLEXSPI_NOR
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config BOOT_XSPI_NOR
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bool "XPI serial NOR"
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depends on DT_HAS_NXP_XSPI_ENABLED
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config BOOT_FLEXSPI_NOR
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bool "FlexSPI serial NOR"
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depends on HAS_MCUX_FLEXSPI
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@ -49,6 +60,8 @@ config BOOT_SEMC_NAND
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endchoice # BOOT_DEVICE
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if BOOT_FLEXSPI_NOR
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config FLEXSPI_CONFIG_BLOCK_OFFSET
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hex "FlexSPI config block offset"
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default 0x0 if BOOT_FLEXSPI_NOR
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@ -59,6 +72,21 @@ config FLEXSPI_CONFIG_BLOCK_OFFSET
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sequence (optional), etc. The boot ROM expects FlexSPI configuration
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parameter to be presented in serial nor flash.
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endif # BOOT_FLEXSPI_NOR
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if BOOT_XSPI_NOR
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config XSPI_CONFIG_BLOCK_OFFSET
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hex "XSPI config block offset"
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default 0x0
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help
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XSPI configuration block consists of parameters regarding specific
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flash devices including read command sequence, quad mode enablement
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sequence (optional), etc. The boot ROM expects XSPI configuration
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parameter to be presented in serial nor flash.
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endif # BOOT_XSPI_NOR
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config IMAGE_VECTOR_TABLE_OFFSET
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hex "Image vector table offset"
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default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
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@ -9,11 +9,15 @@ __VECTOR_TABLE = CONFIG_ROM_START_OFFSET;
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__Vectors = __VECTOR_TABLE;
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#endif
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#if defined(CONFIG_BOOT_XSPI_NOR)
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. = CONFIG_XSPI_CONFIG_BLOCK_OFFSET;
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#else
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. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
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#endif
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#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT118X)
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KEEP(*(.boot_hdr.conf))
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#endif
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#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX)
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#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT7XX)
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KEEP(*(.flash_conf))
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#endif
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#if defined(CONFIG_SOC_SERIES_IMXRT118X)
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9
soc/nxp/imxrt/imxrt7xx/CMakeLists.txt
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9
soc/nxp/imxrt/imxrt7xx/CMakeLists.txt
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@ -0,0 +1,9 @@
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#
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# Copyright 2024 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if(CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SOC_MIMXRT798S_CM33_CPU1)
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add_subdirectory(cm33)
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endif()
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58
soc/nxp/imxrt/imxrt7xx/Kconfig
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soc/nxp/imxrt/imxrt7xx/Kconfig
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@ -0,0 +1,58 @@
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_MIMXRT798S_CM33_CPU0
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select CPU_CORTEX_M33
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select CLOCK_CONTROL
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select CPU_CORTEX_M_HAS_DWT
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select ARM
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select HAS_MCUX
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select HAS_MCUX_SYSCON
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select HAS_MCUX_CACHE
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select SOC_RESET_HOOK
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config SOC_MIMXRT798S_CM33_CPU1
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select CPU_CORTEX_M33
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select CLOCK_CONTROL
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select CPU_CORTEX_M_HAS_DWT
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select ARM
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select HAS_MCUX
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select HAS_MCUX_SYSCON
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if SOC_SERIES_IMXRT7XX
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if NXP_IMXRT_BOOT_HEADER
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config IMAGE_VECTOR_TABLE_OFFSET
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default 0x4000
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endif # NXP_IMXRT_BOOT_HEADER
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config GLIKEY_MCUX_GLIKEY
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default y
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bool "Use glikey MCUX Driver"
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config IMXRT7XX_CODE_CACHE
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bool "Code cache"
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default y if HAS_MCUX_CACHE
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help
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Enable code cache for XSPI region at boot. If this Kconfig is
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cleared, the CACHE64 controller will be disabled during SOC init
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config MCUX_CORE_SUFFIX
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default "_cm33_core0" if SOC_MIMXRT798S_CM33_CPU0
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default "_cm33_core1" if SOC_MIMXRT798S_CM33_CPU1
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endif # SOC_SERIES_IMXRT7XX
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29
soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig
Normal file
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soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MIMXRT798S_CM33_CPU0
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config ROM_START_OFFSET
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default 0x4000 if NXP_IMXRT_BOOT_HEADER
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config NUM_IRQS
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default 158
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 237500000 if CORTEX_M_SYSTICK
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endif # SOC_MIMXRT798S_CM33_CPU0
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if SOC_MIMXRT798S_CM33_CPU1
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config NUM_IRQS
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default 93
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 100000000 if CORTEX_M_SYSTICK
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endif # SOC_MIMXRT798S_CM33_CPU1
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config MFD
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default y
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depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED
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50
soc/nxp/imxrt/imxrt7xx/Kconfig.soc
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50
soc/nxp/imxrt/imxrt7xx/Kconfig.soc
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_IMXRT7XX
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bool
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select SOC_FAMILY_NXP_IMXRT
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config SOC_MIMXRT798S
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bool
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select SOC_SERIES_IMXRT7XX
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config SOC_MIMXRT798S_CM33_CPU0
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bool
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select SOC_MIMXRT798S
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config SOC_MIMXRT798S_CM33_CPU1
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bool
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select SOC_MIMXRT798S
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config SOC_SERIES
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default "imxrt7xx" if SOC_SERIES_IMXRT7XX
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config SOC
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default "mimxrt798s" if SOC_MIMXRT798S
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config SOC_PART_NUMBER_MIMXRT798SGAWAR
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bool
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config SOC_PART_NUMBER_MIMXRT798SGFOA
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bool
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config SOC_PART_NUMBER_MIMXRT758SGAWAR
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bool
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config SOC_PART_NUMBER_MIMXRT758SGFOA
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bool
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config SOC_PART_NUMBER_MIMXRT735SGAWAR
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bool
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config SOC_PART_NUMBER_MIMXRT735SGFOA
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bool
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config SOC_PART_NUMBER
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default "MIMXRT798SGFOA" if SOC_PART_NUMBER_MIMXRT798SGFOA
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default "MIMXRT798SGAWAR" if SOC_PART_NUMBER_MIMXRT798SGAWAR
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default "MIMXRT758SGFOA" if SOC_PART_NUMBER_MIMXRT758SGFOA
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default "MIMXRT758SGAWAR" if SOC_PART_NUMBER_MIMXRT758SGAWAR
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default "MIMXRT735SGFOA" if SOC_PART_NUMBER_MIMXRT735SGFOA
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default "MIMXRT735SGAWAR" if SOC_PART_NUMBER_MIMXRT735SGAWAR
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25
soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt
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25
soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt
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#
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# Copyright 2024 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_compile_definitions_ifdef(CONFIG_NXP_LP_FLEXCOMM LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1)
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zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
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zephyr_include_directories(.)
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zephyr_sources(soc.c)
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if(CONFIG_FLASH_MCUX_XSPI_XIP)
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zephyr_sources(flash_clock_setup.c)
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zephyr_code_relocate(FILES flash_clock_setup.c LOCATION ${CONFIG_FLASH_MCUX_XSPI_XIP_MEM}_TEXT)
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endif()
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zephyr_library_include_directories(
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${ZEPHYR_BASE}/kernel/include
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${ZEPHYR_BASE}/arch/${ARCH}/include
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)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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168
soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c
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168
soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c
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@ -0,0 +1,168 @@
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/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#ifdef CONFIG_HAS_MCUX_CACHE
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#include <fsl_cache.h>
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#endif
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static void enable_xspi_cache(CACHE64_CTRL_Type *cache)
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{
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/* First, invalidate the entire cache. */
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cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK |
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CACHE64_CTRL_CCR_GO_MASK;
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while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) {
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}
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/* As a precaution clear the bits to avoid inadvertently re-running this command. */
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cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK);
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/* Now enable the cache. */
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cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK;
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}
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static void disable_xspi_cache(CACHE64_CTRL_Type *cache)
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{
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cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK |
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CACHE64_CTRL_CCR_GO_MASK; /* First, clean XSPI cache. */
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while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) {
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}
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/* As a precaution clear the bits to avoid inadvertently re-running this command. */
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cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK);
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/* Now disable XSPI cache. */
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cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK;
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}
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static void flash_deinit(XSPI_Type *base, CACHE64_CTRL_Type *cache)
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{
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if (base == XSPI0) {
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/* Enable clock again. */
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CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK;
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} else if (base == XSPI1) {
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/* Enable clock again. */
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CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK;
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}
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base->MCR &= ~XSPI_MCR_MDIS_MASK;
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if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) {
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disable_xspi_cache(cache);
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}
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/* Wait until XSPI is not busy */
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while ((base->SR & XSPI_SR_BUSY_MASK) != 0U) {
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}
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/* Disable module. */
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base->MCR |= XSPI_MCR_MDIS_MASK;
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}
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static void flash_init(XSPI_Type *base, CACHE64_CTRL_Type *cache)
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{
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/* Enable XSPI module */
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base->MCR |= XSPI_MCR_MDIS_MASK;
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base->MCR |= XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK;
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for (uint32_t i = 0; i < 6; i++) {
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__NOP();
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}
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base->MCR &= ~(XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK);
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base->MCR |= XSPI_MCR_IPS_TG_RST_MASK | XSPI_MCR_MDIS_MASK;
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base->MCR &= ~XSPI_MCR_ISD3FA_MASK;
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base->MCR &= ~XSPI_MCR_MDIS_MASK;
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base->MCR |= XSPI_MCR_MDIS_MASK;
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base->MCR |= XSPI_MCR_ISD3FA_MASK;
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base->MCR &= ~XSPI_MCR_MDIS_MASK;
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base->MCR |= XSPI_MCR_MDIS_MASK;
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base->SMPR = (((base->SMPR) & (~XSPI_SMPR_DLLFSMPFA_MASK)) |
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XSPI_SMPR_DLLFSMPFA(FSL_FEATURE_XSPI_DLL_REF_VALUE_DDR_DELAY_TAP_NUM));
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base->MCR &= ~XSPI_MCR_MDIS_MASK;
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base->DLLCR[0] &=
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~(XSPI_DLLCR_SLV_DLL_BYPASS_MASK | XSPI_DLLCR_DLL_CDL8_MASK |
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XSPI_DLLCR_SLV_DLY_OFFSET_MASK | XSPI_DLLCR_SLV_FINE_OFFSET_MASK |
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XSPI_DLLCR_DLLRES_MASK | XSPI_DLLCR_DLL_REFCNTR_MASK | XSPI_DLLCR_FREQEN_MASK);
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base->DLLCR[0] &=
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~(XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK | XSPI_DLLCR_DLLEN_MASK);
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/* Enable subordinate as auto update mode. */
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base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK;
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/* program DLL to desired delay. */
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base->DLLCR[0] |=
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XSPI_DLLCR_DLLRES(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLE_RES) |
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XSPI_DLLCR_DLL_REFCNTR(
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FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLED_REF_COUNTER) |
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XSPI_DLLCR_SLV_FINE_OFFSET(0) | XSPI_DLLCR_SLV_DLY_OFFSET(0) |
|
||||
XSPI_DLLCR_FREQEN(1U);
|
||||
/* Load above settings into delay chain. */
|
||||
base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK;
|
||||
base->DLLCR[0] |= XSPI_DLLCR_DLLEN_MASK;
|
||||
base->DLLCR[0] &= ~XSPI_DLLCR_SLV_UPD_MASK;
|
||||
|
||||
while ((base->DLLSR & XSPI_DLLSR_SLVA_LOCK_MASK) == 0UL) {
|
||||
}
|
||||
|
||||
if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U) {
|
||||
enable_xspi_cache(cache);
|
||||
/* flush pipeline */
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
/* xspi_setup_clock run in RAM when XIP. */
|
||||
void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider)
|
||||
{
|
||||
if (base == XSPI0) {
|
||||
if ((CLKCTL0->XSPI0FCLKSEL != CLKCTL0_XSPI0FCLKSEL_SEL(src)) ||
|
||||
((CLKCTL0->XSPI0FCLKDIV & CLKCTL0_XSPI0FCLKDIV_DIV_MASK) != (divider - 1))) {
|
||||
/* Always deinit XSPI and init XSPI for the flash to make
|
||||
* sure the flash works correctly after the XSPI root clock
|
||||
* changed as the default XSPI configuration may does not
|
||||
* work for the new root clock frequency.
|
||||
*/
|
||||
flash_deinit(base, CACHE64_CTRL0);
|
||||
|
||||
/* Disable clock before changing clock source */
|
||||
CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK;
|
||||
/* Update XSPI clock. */
|
||||
CLKCTL0->XSPI0FCLKSEL =
|
||||
CLKCTL0_XSPI0FCLKSEL_SEL(src) | CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK;
|
||||
CLKCTL0->XSPI0FCLKDIV = CLKCTL0_XSPI0FCLKDIV_DIV(divider - 1);
|
||||
while ((CLKCTL0->XSPI0FCLKDIV) & CLKCTL0_XSPI0FCLKDIV_REQFLAG_MASK) {
|
||||
}
|
||||
/* Enable XSPI clock again */
|
||||
CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI0_MASK;
|
||||
|
||||
flash_init(base, CACHE64_CTRL0);
|
||||
}
|
||||
} else if (base == XSPI1) {
|
||||
if ((CLKCTL0->XSPI1FCLKSEL != CLKCTL0_XSPI1FCLKSEL_SEL(src)) ||
|
||||
((CLKCTL0->XSPI1FCLKDIV & CLKCTL0_XSPI1FCLKDIV_DIV_MASK) != (divider - 1))) {
|
||||
/* Always deinit XSPI and init XSPI for the flash to make sure the flash
|
||||
* works correctly after the XSPI root clock changed as the default XSPI
|
||||
* configuration may does not work for the new root clock frequency.
|
||||
*/
|
||||
flash_deinit(base, CACHE64_CTRL1);
|
||||
|
||||
/* Disable clock before changing clock source */
|
||||
CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK;
|
||||
/* Update XSPI clock. */
|
||||
CLKCTL0->XSPI1FCLKSEL =
|
||||
CLKCTL0_XSPI1FCLKSEL_SEL(src) | CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK;
|
||||
CLKCTL0->XSPI1FCLKDIV = CLKCTL0_XSPI1FCLKDIV_DIV(divider - 1);
|
||||
while ((CLKCTL0->XSPI1FCLKDIV) & CLKCTL0_XSPI1FCLKDIV_REQFLAG_MASK) {
|
||||
}
|
||||
/* Enable XSPI clock again */
|
||||
CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK;
|
||||
|
||||
flash_init(base, CACHE64_CTRL1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void xspi_clock_safe_config(void)
|
||||
{
|
||||
xspi_setup_clock(XSPI0, 0U, 1U);
|
||||
xspi_setup_clock(XSPI1, 0U, 1U);
|
||||
}
|
87
soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h
Normal file
87
soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h
Normal file
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
typedef uint32_t pinctrl_soc_pin_t;
|
||||
|
||||
#define IOPCTL_PIO_PUPDENA_MASK (0x10U)
|
||||
#define IOPCTL_PIO_PUPDSEL_MASK (0x20U)
|
||||
|
||||
#define IOPCTL_PIO_ODENA_MASK (0x400U)
|
||||
#define IOPCTL_PIO_ODENA_SHIFT (10U)
|
||||
#define IOPCTL_PIO_ODENA(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_ODENA_SHIFT)) & IOPCTL_PIO_ODENA_MASK)
|
||||
|
||||
#define IOPCTL_PIO_IBENA_MASK (0x40U)
|
||||
#define IOPCTL_PIO_IBENA_SHIFT (6U)
|
||||
#define IOPCTL_PIO_IBENA(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IBENA_SHIFT)) & IOPCTL_PIO_IBENA_MASK)
|
||||
|
||||
/* Please note there is no SLEWRATE attribution on IOPCTL2 */
|
||||
#define IOPCTL_PIO_SLEWRATE_MASK (0x80U)
|
||||
#define IOPCTL_PIO_SLEWRATE_SHIFT (7U)
|
||||
#define IOPCTL_PIO_SLEWRATE(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_SLEWRATE_SHIFT)) & IOPCTL_PIO_SLEWRATE_MASK)
|
||||
|
||||
/* Please note there is no FULLDRIVE attribution on IOPCTL2 */
|
||||
#define IOPCTL_PIO_FULLDRIVE_MASK (0x100U)
|
||||
#define IOPCTL_PIO_FULLDRIVE_SHIFT (8U)
|
||||
#define IOPCTL_PIO_FULLDRIVE(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FULLDRIVE_SHIFT)) & IOPCTL_PIO_FULLDRIVE_MASK)
|
||||
|
||||
#define IOPCTL_PIO_IIENA_MASK (0x800U)
|
||||
#define IOPCTL_PIO_IIENA_SHIFT (11U)
|
||||
#define IOPCTL_PIO_IIENA(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IIENA_SHIFT)) & IOPCTL1_PIO_IIENA_MASK)
|
||||
|
||||
/* Please note there is no AMENA attribution on IOPCTL2 */
|
||||
#define IOPCTL_PIO_AMENA_MASK (0x200U)
|
||||
#define IOPCTL_PIO_AMENA_SHIFT (9U)
|
||||
#define IOPCTL_PIO_AMENA(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_AMENA_SHIFT)) & IOPCTL_PIO_AMENA_MASK)
|
||||
|
||||
#define Z_PINCTRL_IOPCTL_PINCFG(node_id) \
|
||||
(IF_ENABLED(DT_PROP(node_id, bias_pull_down), \
|
||||
(IOPCTL_PIO_PUPDENA_MASK |)) /* pull down */ \
|
||||
IF_ENABLED(DT_PROP(node_id, bias_pull_up), \
|
||||
(IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |)) /* pull up */ \
|
||||
IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \
|
||||
IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \
|
||||
IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */ \
|
||||
IOPCTL_PIO_FULLDRIVE( \
|
||||
DT_ENUM_IDX(node_id, drive_strength)) | /* drive strength */ \
|
||||
IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \
|
||||
IOPCTL_PIO_AMENA( \
|
||||
DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
|
||||
|
||||
/* MCUX RT parts only have one pin type */
|
||||
#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF)
|
||||
#define Z_PINCTRL_IOCON_A_PIN_MASK (0)
|
||||
#define Z_PINCTRL_IOCON_I_PIN_MASK (0)
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
|
||||
DT_PROP_BY_IDX(group, pin_prop, idx),
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ */
|
27
soc/nxp/imxrt/imxrt7xx/cm33/soc.c
Normal file
27
soc/nxp/imxrt/imxrt7xx/cm33/soc.c
Normal file
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for NXP RT7XX platform
|
||||
*
|
||||
* This module provides routines to initialize and support board-level
|
||||
* hardware for the RT7XX platforms.
|
||||
*/
|
||||
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/linker/sections.h>
|
||||
#include <soc.h>
|
||||
|
||||
#ifdef CONFIG_SOC_RESET_HOOK
|
||||
|
||||
void soc_reset_hook(void)
|
||||
{
|
||||
SystemInit();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SOC_RESET_HOOK */
|
36
soc/nxp/imxrt/imxrt7xx/cm33/soc.h
Normal file
36
soc/nxp/imxrt/imxrt7xx/cm33/soc.h
Normal file
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 2024 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Board configuration macros for the MIMXRT7XX platform
|
||||
*
|
||||
* This header file is used to specify and describe board-level aspects for the
|
||||
* 'MIMXRT7XX' platform.
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <fsl_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void xspi_clock_safe_config(void);
|
||||
void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC__H_ */
|
|
@ -38,6 +38,12 @@ family:
|
|||
- name: mimxrt685s
|
||||
cpuclusters:
|
||||
- name: cm33
|
||||
- name: imxrt7xx
|
||||
socs:
|
||||
- name: mimxrt798s
|
||||
cpuclusters:
|
||||
- name: cm33_cpu0
|
||||
- name: cm33_cpu1
|
||||
runners:
|
||||
run_once:
|
||||
'--erase':
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue